RU2190914C1 - Power direction relay - Google Patents

Abstract

FIELD: relay protective gear. SUBSTANCE: relay has voltage converter, current converter, four comparators, pulse generator, four switches, two pulse shapers, two delay circuits, two reversing counters, two memory registers, binary code shaper, two digital comparators, and 2OR gate. EFFECT: enhanced speed of response. 2 dwg

Description

 The invention relates to the field of relay protection and can be used, in particular, for remote high-speed protection of power lines.

 A power direction switch [1] is known that uses an analogue method of comparing input values by using a module driver, which includes low-pass filters, an adder and a zero indicator, and therefore has low accuracy, low speed, and requires changes in the design of the relay if it is necessary to change the angle maximum sensitivity of the relay.

 The present invention allows to eliminate these disadvantages using a digital method for comparing input values in phase at each half-cycle of their succession. This is achieved by the fact that the relay has additionally introduced: four comparators, four keys, two pulse shapers, two delay elements, two reversible counters, a pulse generator, two memory registers, a binary code shaper, two digital comparators, a 2 OR element, and the voltage converter output connected with the compared input of the first comparator and with the inverse compared input of the second comparator, the output of the current converter is connected with the compared input of the third and with the inverse compared input of the fourth comp the output of the first comparator is connected to the control input of the first key, the output of the second comparator is connected to the control input of the second key, the output of the third comparator is connected to the control input of the third key, the output of the fourth comparator is connected to the control input of the fourth key, the output of the pulse generator is connected to the working inputs of four keys, the output of the first key is connected to the summing input of the first reversible counter, as well as to the first input of the first pulse shaper, the output of the second key is connected to the summing the second reversible counter, as well as with the first input of the second pulse shaper, the output of the third key is connected to the subtracting input of the first reversing counter, as well as to the second input of the first pulse shaper, the fourth key output is connected to the subtracting input of the second reversing counter, as well as with the second input of the second pulse shaper, the output of the first pulse shaper is connected to the recording input C of the first memory register and through the first delay element with the reset input R of the first reversal count The output of the second pulse shaper is connected to the recording input C of the second memory register and through the second delay element to the reset input R of the second reverse counter, the output of the first reverse counter is connected to the information input D of the first memory register, the output of the second reverse counter is connected to the information input D of the second memory register, the output of the first memory register is connected to the input A of the first digital comparator, the output of the second memory register is connected to the input A of the second digital comparator, the output The binary encoder is connected to the inputs B of the first and second digital comparators, the output B> of the first digital comparator is connected to the first input of the 2 OR element, the output B> of the second digital comparator is connected to the second input of the 2 OR element, the output of the 2 OR element is the output of the power direction relay.

 In FIG. 1 shows a functional diagram of the power direction switch, figure 2 is a timing diagram of its operation.

 The relay contains: a voltage converter (1), a current converter (2), four comparators (3-6), a pulse generator (7), four keys (8-11), two pulse shapers (12, 15), two delay elements ( 13, 16), two reverse counters (14, 17), two memory registers (18, 19), a binary code former (20), two digital comparators (21, 22), an OR element (23).

 The relay operates as follows.

The voltage signal (Fig. 2, U ₁ ) is supplied to the voltage converter (Fig. 1, 1), which is used for large-scale conversion of this signal into a voltage corresponding to the input level of the relay. The current signal (Fig. 2, U ₂ ) is supplied to the current transducer (Figs. 1, 2), which is used for large-scale conversion of current into a voltage corresponding to the input level of the relay, then the signal from the output of the voltage transformer goes to the compared input of the first comparator (Fig. 1, 3) and to the inverted compared input of the second comparator (Fig. 1, 4), from the output of the current converter, the signal goes to the compared input of the third comparator (Figs. 1, 5) and to the inverted compared input of the fourth comparator (Figs. 1, 6 ) The comparators, respectively, generate pulses at their output (Fig. 2, U ₃ , U ₄ , U ₅ , U ₆ ), equal in duration to the half-waves of the signals arriving at their inputs.

 The signals from the outputs of the first, second, third and fourth comparators are fed to the control inputs of the first, second, third and fourth keys (Fig. 1, 8-11), respectively. The working inputs of the four keys receive pulses from the output of the pulse generator (Fig.1, 7).

Thus, at the output of the keys, sequences of pulses will be formed, stacking during the existence of pulses from the corresponding comparators. The pulse sequence generated at the output of the first key goes to the summing input C _{1 of the} first reverse counter (Fig. 1, 14), as well as to the first input of the first pulse shaper (Fig. 1, 12), the pulse sequence generated at the output of the second key arrives at the summing input C _{1 of the} second reversible counter (Fig. 1, 17), as well as at the first input of the second pulse shaper (Fig. 1, 15), the pulse train generated at the output of the third key goes to the subtracting input C _{2 of the} first reverse with etchika and the second input of the first pulse shaper, a sequence of pulses formed on the fourth key output is supplied to the subtracting input C ₂ of the second up-down counter and a second input of the second pulse shaper.

The first and second pulse shapers form single pulses at their outputs along the trailing edge of each second input pulse. Reverse counters perform the calculation of the difference in the number of pulses received at their inputs C ₁ and C ₂ . The result of the difference between the outputs of the first (Fig. 2, U _ct1 ) and second (Fig. 2, U _ct2 ) reverse counters is supplied to the information inputs D of the first (Fig. 1, 18) and second (Fig. 1, 19) memory registers, respectively . Single pulses from the outputs of the first and second pulse shaping arrive at the recording inputs From the first and second memory registers, respectively, as well as through the first (Fig. 1, 13) and second (Fig. 1, 16) delay element to the reset inputs R of the first and second reverse counter respectively.

Thus, in the first and second memory registers, the phase difference is recorded in binary form, respectively, between the positive and negative half-waves of the input voltage and current signals, and also with a time delay, the counters are reset. The signal from the outputs of the first (Fig. 2, U _21A ) and second (Fig. 2, U _22A ) memory registers is supplied to the inputs A of the first (Fig. 1, 21) and second (Fig. 1, 22) digital comparators. At the inputs of the first and second digital comparators from the output of the binary code generator (Fig. 1, 20), the maximum permissible value of the phase difference between the input voltage and current values (Fig. 2, U _21B , U _22B ) is _received . If the binary number at the input B of one of the digital comparators exceeds the binary number at its input A, the pulse B is generated at the output B> of this digital comparator (Fig. 2, U _out ), which arrives at one of the two inputs of the 2 OR element (Fig. 1 , 23). The output of the 2OR element is the output of the power direction switch.

 Thus, the proposed power direction switch allows you to quickly and accurately determine the change in the direction of power flow.

Sourse of information
1. Vanin V. K., Pavlov G. M. Relay protection on the elements of computer technology. - L: Energoatomizdat. Leningrad branch, 1983, - 206 p.

Claims (1)

 A power direction switch comprising a voltage converter, a current converter, characterized in that four comparators, four keys, two pulse shapers, two delay elements, two reversible counters, a pulse generator, two memory registers, a binary code shaper, two digital comparator, element 2 OR, and the output of the voltage converter is connected to the compared input of the first comparator and to the inverse compared input of the second comparator, the output of the current converter with the compared input of the third and with the inverse compared input of the fourth comparator, the output of the first comparator is connected to the control input of the first key, the output of the second comparator is connected to the control input of the second key, the output of the third comparator is connected to the control input of the third key, the output of the fourth comparator is connected to the control input of the fourth key, the output of the pulse generator is connected to the working inputs of the four keys, the output of the first key is connected to the summing input of the first reversible counter, as well as to by the input of the first pulse shaper, the output of the second key is connected to the summing input of the second reversible counter, as well as to the first input of the second pulse shaper, the output of the third key is connected to the subtracting input of the first reversible counter, and the second input of the fourth key is connected with the subtracting input of the second reversible counter, as well as with the second input of the second pulse shaper, the output of the first pulse shaper is connected to the recording input C of the first register memory and through the first delay element with the reset input R of the first reverse counter, the output of the second pulse shaper is connected to the recording input C of the second memory register and through the second delay element with the reset input R of the second reverse counter, the output of the first reverse counter is connected to the information input D of the first memory register, the output of the second reversible counter is connected to the information input D of the second memory register, the output of the first memory register is connected to the input A of the first digital comparator, the output the second memory register is connected to the input A of the second digital comparator, the output of the binary code generator is connected to the input B of the first and second digital comparators, the output B> of the first digital comparator is connected to the first input of the 2 OR element, the output B> of the second digital comparator is connected to the second input of the 2 OR The output of the 2OR element is the output of the power direction switch.

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