RU2165114C1 - Method for multilayer metallization of integrated circuits - Google Patents

Abstract

FIELD: manufacture of integrated circuits and miscellaneous nanostructures. SUBSTANCE: method involves deposition of conducting pattern of interconnections for each level on source plate with active regions, deposition of interlayer insulating coatings, and formation of interlayer connections; all interlayer connections are made in the form of vertical conductors of different length evaporated before applying interlayer insulating coatings onto source plate prior to shaping conducting pattern of first and next metal layers; in the process all metal ion currents conveyed to source plate are subjected to spatial modulation by means of templates. EFFECT: facilitated procedure. 8 dwg

Description

 The invention relates to microelectronics and can be used in the manufacture of integrated circuits and nanostructures for various purposes.

 A known method of metallization of multilayer integrated circuits, including the formation in a silicon wafer with active regions of interlayer dielectric coatings and making through them interlayer conductive compounds (see the description of US patent N 5607880, H 01 L 21/44, NKI 437/195, 1997 [1 ]). The disadvantage of this method is the complexity of its implementation, which consists in the fact that its implementation uses photolithography techniques, which lead to the necessity of applying layers of photoresist, opening windows with selective etching to form masks, removing layers of photoresist after completion of the layer, and in the manufacture of multilayer circuits, these operations repeat many times.

 A known method of forming a multilayer metallization of microcircuits without using the operations of the photolithography method (see the description of US patent N 5569624, H 01 L 21/28, NCI 437/200, 1996 [2]). The known method involves the manufacture of semiconductor valves, the alloying of which is carried out by transferring the alloying impurities from the overlying specially prepared layer to the underlying, being doped, under the influence of radiation from an excimer laser. The disadvantage of this method is the limited application, since it is applicable only for the manufacture of valves and does not provide the formation of multilayer conductive compounds.

 The closest to the claimed in its technical essence and the achieved result is a known method of manufacturing integrated circuits, which ensures the formation of inter-level (interlayer) compounds in them (see the description of the patent of the Russian Federation N 1547611, H 01 L 21/28, 1996 [3]) . The known method provides that after the formation of ohmic and rectifying contacts to the created active areas, an interconnect pattern is formed at the first level, then an interlayer dielectric is applied, windows are opened in it and an interlayer connection is made, and then the next layer is formed. In this case, photolithography technology is used to form interlayer compounds.

 The disadvantage of this method is the complexity of its implementation, due to the use of photolithographic processes and the sequential implementation of interlayer connections, as a result of which the processed plate is repeatedly removed from the vacuum system to remove the photoresist and returned to it for subsequent operations.

 The inventive method of forming multi-level metallization is aimed at simplifying the process.

 This result is achieved by the fact that the method of forming multilevel metallization of integrated circuits involves forming interconnects at each level in the initial plate with active regions of the conductive pattern, applying interlayer dielectric coatings and forming interlayer compounds, while all interlayer compounds are formed before applying interlayer dielectric coatings and perform them in the form of vertical wires of various heights sprayed onto the original plate before the formation of conductive rice the first and subsequent layers of metallization, while all flows of metal ions directed to the original plate are subjected to spatial modulation using templates.

Distinctive features of the proposed method are:
- the implementation of all interlayer compounds prior to the application of interlayer dielectric coatings;
- the implementation of interlayer connections in the form of vertical wires of various heights, sprayed onto a silicon wafer;
- spatial modulation of the flow of metal ions directed to the processed silicon wafer;
- use of patterns for spatial modulation.

 The implementation of all interlayer connections prior to the application of interlayer dielectric coatings simplifies the technology of forming multilevel metallization, since there is no need to open the corresponding windows in the interlayer dielectric coatings and form conductive structures in them, since in the proposed method the vertical elements of the conductive structure made in the form of vertical wires-columns will penetrate a given number of layers of the microcircuit and interlayer coatings will be "strung" on them by re their application.

 The use of spatial modulation of the flow of metal ions directed to the plate being processed allows to significantly simplify the process of forming metallization layers, since there is no need to use the photolithography process and related operations. The formation of the conductive structure can be achieved by spatial modulation of the flow of metal ions used in the deposition of metal layers. And only the flux of dielectric ions does not need modulation, since when spraying it should cover the entire surface of the processed plate.

 Since the use of spatial modulation allows you to abandon the processes of photolithography and to carry out all stages of the technological cycle of multilayer metallization in a vacuum system, this also simplifies the implementation of the claimed method. An initial plate with formed active regions is placed in a vacuum system equipped with appropriate sources for spraying metals and dielectrics and, after all operations are completed, the finished microcircuit is removed without resorting to depressurization of the system during the manufacturing process, as is the case in the prototype.

 The simplest means of spatial modulation is a template placed in the path of the flow of particles, atoms or ions. Therefore, the use of templates simplifies the method.

 The essence of the claimed invention is illustrated by an example of its implementation and drawings. In FIG. 1-8 schematically shows a cross section of the manufactured microcircuit at various stages of the method.

 Example 1. In the General case, the method is implemented as follows (for example, a three-layer scheme).

 The initial plate of single-crystal silicon 1 with the formed active regions 2 is placed inside a vacuum installation, including an ion-projecting device and equipped with the necessary means for spraying metal and dielectric layers, which can be selected from among the known (see, for example, W. Till, J. Laxon, Integrated Circuits. M., Mir, 1985 [4]). Then, on the surface of the silicon wafer, in accordance with the topology of the manufactured microcircuit, vertical wires 3 of different heights are sequentially formed by spatial modulation of the metal ion beam as it passes through the patterns, which eliminates the use of masks from the resist (Fig. 1). The use of various patterns in the vacuum deposition of vertical wires ensures their corresponding location on the chip and their various heights.

 After the formation of vertical wires 3 of different heights, the plate is covered with the first layer of the interlayer dielectric 4 (Fig. 2). In this case, “caps” of a dielectric with a thickness equal to the thickness of the first dielectric layer are formed on the surface of the vertical wires. At subsequent stages of the process, the thickness of the “caps” of the dielectric increases in proportion to the number of layers of the dielectric and it is integrated into the common layer of variable thickness.

 At the next stage (Fig. 3), horizontal wires of the first level 5 are formed through a template. Similar operations of forming horizontal wires of the second 6 and third layer 7 are carried out through templates in accordance with the topology of the manufactured microcircuit. These operations are shown in FIG. 5 and 7.

 After the formation of horizontal wires in each of the metallization layers, the entire plate is covered with a dielectric layer 4 (Fig. 4, 6, 8). The manufacturing process of the microcircuit in a vacuum installation ends with the application of a dielectric layer covering the entire wiring, as shown in FIG. 8.

 According to the above algorithm, microcircuits with any number of layers can be formed.

 To carry out the operations constituting the method, known devices and materials can be used - metals for the formation of conductive structures (aluminum, copper, etc.), dielectrics for the formation of interlayer coatings, etc.

Claims (1)

 The method of forming multilevel metallization of integrated circuits, including the formation in the initial plate with active regions of the conductive pattern of interconnects at each level, the deposition of interlayer dielectric coatings and the formation of interlayer compounds, characterized in that all interlayer compounds are formed before applying interlayer dielectric coatings and are made in the form of vertical wires of various heights sprayed onto the source plate before forming a conductive pattern of the first and subsequent metallization layers, while all flows of metal ions directed to the original plate are subjected to spatial modulation using patterns.

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