RU2156542C1 - Device for evaluating quality of reception of binary signals - Google Patents

Abstract

FIELD: radio engineering, adaptive radio communication equipment. SUBSTANCE: state-of-the-art device has serial circuit of frequency detector, integrator, threshold gate and first register. In addition device has synchronization unit, which first output is connected to synchronization input of first register, and unit of modulo two adders. Said device has low reliability for evaluating quality of reception of binary signals. Goal of invention is achieved by introduced additional n-1 registers, unit of gates, reference signal storage unit, and adder. EFFECT: increased reliability for evaluating quality of reception of binary signals, increased functional capabilities. 2 dwg

Description

 The proposed device relates to the field of radio engineering and may find application in adaptive radio communication systems.

 The well-known "Analyzer of temporary distortion" of binary signals, described in the book Buchviner B. E. "Assessment of the quality of radio communications." M., Svyaz, 1974 on page 57, Fig. 2.18, in which the analysis zones are formed at the proposed element length symmetrically to its middle, and the decision on the transmitted symbol is made by checking the coincidence of the position of the fronts falling into each analysis zone.

 However, this device has a narrow measurement range.

 The "Signal Quality Control System" is also known according to the application of Japan N 60-5098 of 08.02.85, bull. N 7-128, in which the transmitted signal is encoded with a pseudo-random code, and decoded at the receiving side, while using the counter, the number of states of the decoding unit other than that fixed in the receiving device is counted. Based on the value calculated in the counter, the quality of the received signal is estimated.

 However, this device has low accuracy in assessing the quality of the received signal.

 The closest in technical essence to the proposed device is the device according to the patent of the Russian Federation N 2001529 "Method for assessing the quality of reception of binary signals and a device for its implementation" from 10/15/93, bull. N 37-38, adopted as a prototype.

Functional diagram of the prototype is presented in figure 1, where the following notation:
1 - frequency detector (BH);
2 - low-pass filter (low-pass filter);
3 - threshold block;
4 - register;
5 - synchronizer;
6 - inverter;
7 - block adders modulo two (SMD);
8 - a block for generating pulses of read permission (FIRS);
9 - block of elements OR NOT;
10 - block counters.

 The prototype device comprises series-connected BH1, LPF2, threshold block 3, register 4, block SMD7, block of elements OR-NOT 9 and block of counters 10, serially connected synchronizer 5 and block FIRS8, the output of which is connected to the second input of the block of elements OR-NOT 9, and an inverter 6, while the second output of the synchronizer 5 is connected to the second input of the register 4, the second output of which is connected to the input of the inverter 6, the output of the inverter 6 is connected to the second input of the SMD7 block, and the second input of the FIRS8 block is the input of the device.

 The prototype device operates as follows. The frequency-modulated signal is fed to the input of BH1, where it is converted into bipolar pulses, which are then fed to the input of the low-pass filter, which acts as an integrator, accumulated in it and fed to the input of threshold block 3. Here, a comparison is made with the threshold and a decision is made on the adopted symbol. The signal from the threshold block 3 is recorded using the clock pulses from the synchronizer 5, in the register 4, while the frequency of the recording clock pulses is taken several times higher than the clock frequency of the received information. From the outputs of register 4, the values of the signal samples (samples) are sent to the first inputs of the SMD7 block, and the second inputs of the SMD7 block receive a sample from the first output of the register 4, inverted by inverter 6. Thus, in the SMD7 block, the values of the signal samples are compared with the best. In the event of a mismatch (since the best reference is inverted), "1" appears at the output of the SMD7 block. The values of the results from the outputs of the SMD7 block go to the first inputs of the block of elements OR-NOT 9, and the second inputs of this block receive a read permission signal from the FIRS8 block, generated on the basis of pulses from the output of the synchronizer 5 and the reference frequency supplied to the second input of the FIRS8 block. The read enable signal for the temporary position is at the end of the binary element and represents a short pulse, which allows the passage of the comparison results from the SMD7 block to the input of the counter block 10, where it is fixed. In this case, the block of counters 10 counts bit by bit the results of the comparison on a segment of the information sequence, the duration of which is determined by the period of its calculation. Thus, the result of evaluating the quality of reception of a piece of information is formed by the end of the operation of the block of counters 10. Then, the block of counters 10 is reset to the initial state and the cycle of the prototype device is repeated again.

 However, the prototype device has low reliability of obtaining the results of evaluating the quality of reception of binary signals and narrow functionality.

 In order to improve the reliability of obtaining the results of evaluating the reception quality of binary signals and expanding the functionality in a device containing a series-connected frequency detector, an integrator, a threshold block and a first register, a block of adders modulo two and a synchronizer, the first output of which is connected to the synchronization input of the first register, in this case, the input of the frequency detector is the input of the device, (2..n) registers, (1 ... n) key blocks, a reference signal storage unit and an adder, etc. and the output of the threshold block is connected to the information inputs of (2 .... n) registers, (1 .... N) of the outputs of each of (1 ... n) registers are connected respectively to (1..N) information inputs of the corresponding (1 ... n) blocks of keys, the corresponding (1 ... N) outputs of which are combined and connected to the corresponding (1 ... N) first inputs of the block of adders modulo two, the output of the frequency detector is connected to the input of the synchronizer, the first output which is connected to the control input of the first block of keys, (2. ..n) the outputs of the synchronizer are connected to the synchronization inputs of the corresponding (2.. .n) registers and to the control inputs of the corresponding (2 ... n) key blocks, the nth output of the synchronizer is connected to the second input of the integrator, (1 ... N) the outputs of the reference signal storage unit are connected to the corresponding (1 ... N) second inputs of the adder block up to module two, the outputs of which are connected to the inputs of the adder, the outputs of the adder are the outputs of the device.

Functional diagram of the proposed device is presented in figure 2, where the following notation:
1 - frequency detector (BH);
2 - integrator;
3 - threshold block;
4 - synchronizer;
5 _{1 ... n} - registers;
6 _{1 ... n} - key blocks;
7 - block adders modulo two (SMD);
8 - reference signal storage unit (HES);
9 - adder.

The proposed device contains series-connected BH1, integrator 2 and threshold block 3, series-connected block XES8, block SMD7 and adder 9, the outputs of which are the outputs of the device, synchronizer 4, registers 5 _{1 ... n} and key blocks 6 _{1 ... n} wherein the output of the threshold block 3 is connected to the information inputs of the registers 5 _{1 ... n} , (1 .... N) of the outputs of each of which are connected respectively to the (1 ... N) information inputs of the corresponding key blocks 6 _{1 .. .n} , the corresponding outputs (1 ... N) of the key blocks 6 _{1 ... n are} combined and connected to the corresponding the corresponding (1 ... N) second inputs of the SMD7 block, the BH1 output is connected to the synchronizer input 4, (1 ... n) of which outputs are connected to the synchronization inputs of the corresponding registers 5 _{1 ... n} and the control inputs of the corresponding key blocks 6 _{1 ... n} , the nth output of the synchronizer 4 is connected to the second input of the integrator 2, the input BH1 is the input of the device.

The proposed device operates as follows. The frequency-modulated signal is fed to the input BH1, where it is converted into bipolar pulses, which then go to the input of the integrator 2 (low-pass filter), are accumulated in it on the interval of one bit of information and fed to the input of the threshold block 3. Then the value of the signal accumulated on the integrator 2 is reset at the end of each bit of information with the help of clock pulses coming from the synchronizer 4. In the threshold block 3, a comparison is made with the threshold and a decision is made about the received symbol "0" or "1". The signal from BH1, in addition, goes to synchronizer 4, where a set of clock pulses is generated, which follow with the frequency of information, but shifted relative to each other by time t _i = T / n, where T is the duration of the information bit, and n is an integer . The information sequence from block 3 then goes to the inputs of the registers 5 _{1 ... n} , where it is recorded using the corresponding clock pulses from the synchronizer 4. Thereby, a sampling of the time of each bit of the received information is performed and counts are written to the registers 5 _{1 ... n} ( sampling) a piece of information. In this case, the number of samples taken on one bit of information is n, and the duration of the information segment is determined by the length (bit capacity N) of an individual register of block 5. The signal samples recorded in registers 5 _{1 ... n} then come through the corresponding key blocks 6 _{1. ..n} , opening under the action of the same set of time-shifted clock pulses from synchronizer 4, to the SMD7 block, where they are compared with a reference signal of length N bits stored in the XES8 block. The comparison results are fed to the adder 9, where the number of discrepancies in the samples of the same type is calculated with the reference signal over the entire piece of information in N bits. Thus, the output of the adder 9 is constantly (with a period t _i ) the result of comparing N of the same type of samples with a reference signal, and the most reliable comparison result is a priori determined at the end of the binary signal element, where the signal value during accumulation on integrator 2 reaches its maximum value. Obviously, the values of the comparison results corresponding to the interval of the binary signal element have an unequal probability of coincidence with the most reliable comparison result, which allows us to take into account the analysis of the combination of signal distortions (both edge distortions and fragmentations). The results of comparison by groups of n values corresponding to a piece of processed information of length N bits continuously (with a period of T) are sent to the output of the device to the consumer.

 Such an algorithm for obtaining a signal quality estimate is equivalent to an algorithm for obtaining a quality estimate by comparing the samples taken on one bit of information with the best (last) corresponding end of integration implemented in the prototype.

 The proposed device is implemented physically based on elements and blocks, widely known from the technical literature.

 The technical efficiency of the proposed device in comparison with the prototype lies in a higher reliability of obtaining the results of evaluating the quality of signal reception and wider functionality.

 The first is ensured by the fact that the proposed device implements the principle of continuous formation of a quality assessment on a “moving” piece of information, in contrast to the prototype, where the formation of a quality assessment is carried out with a period determined by the cyclical nature of the counter 10, after which the accumulated quality assessment result is lost and then obtained only by the end of the next period of his account for another piece of information.

 The second one is learned due to the fact that if a known signal is recorded in the storage unit of the reference signal 8, it can also work as a signal search device, i.e. the principle of calculating the correlation function of the received signal with a given reference signal is implemented, which is not possible in the prototype.

Claims (1)

 A device for evaluating the quality of reception of binary signals, containing a series-connected frequency detector, integrator, threshold block and a first register, a synchronizer, the first output of which is connected to the synchronization input of the first register, and the adder block modulo two, while the input of the frequency detector is the input of the device, characterized the fact that p-1 registers, n key blocks, a reference signal storage unit and an adder are additionally introduced into the device, while the output of the threshold block is connected to information inputs (n-1) registers, N outputs of each of the n registers are connected respectively to N information inputs of the corresponding n key blocks, the corresponding N outputs of which are combined and connected to the corresponding N first inputs of the adder block modulo two, the output of the frequency detector is connected to the input of the synchronizer, the first output of which is connected to the control input of the first block of keys, (p-1) outputs of the synchronizer are connected to the synchronization inputs of the corresponding (p-1) registers and to the control inputs of the corresponding (p-1) blocks to In this case, the nth output of the synchronizer is connected to the second input of the integrator, N outputs of the reference signal storage unit are connected to the corresponding N second inputs of the adder unit modulo two, the outputs of which are connected to the inputs of the adder, the outputs of the adder are the outputs of the device.

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