RU2066932C1 - Device for control of tv receiver - Google Patents

Abstract

FIELD: TV devices. SUBSTANCE: device has SSC signal generator 1 and decoupling unit 2. Main station part of device has unit 3 which detects synchronization signals, unit 4 which detects control signals, control unit 5. Peripheral station part of device has unit 6, which detects synchronization signals, unit 7 which detects control signals, unit 8 which outputs response signal, unit 9 which requests digital and analog sensors, decoding unit 10, registers 11 and 15, digital-to-analog converter 12, shift register 13 and NOR gate 14. D flip-flop 33 which is introduced to output unit 8 provides possibility to exclude influence of duration of strobe pulse as well as influence of characteristics of delay gate 30 which is located in output 8, when strobe pulse is sent from output of multiplexer 36 which belongs to request unit 9. Device claim describes specific design of detection units 3, 4, 6, and 7, control unit 5, output unit 8 and request unit 9. EFFECT: increased precision of control. 3 dwg

Description

 The invention relates to television technology, can be used in television receivers and is an improvement of the known device described in application N 4151717 / 24-09, N 2046549 a positive decision from 13.12.86.

 The aim of the invention is to improve the accuracy of control, by increasing the accuracy of reading the status of analog sensors.

 In FIG. 1 is a structural electrical diagram of a television receiver control device.

 In FIG. 2 and 3 are timing diagrams explaining the operation of the device.

 The television receiver control device (Fig. 1) contains an SSC signal generator 1, an isolation unit 2, a synchronization signal allocation unit 3, a control signal allocation unit 4, a control unit 5 at a central station, a synchronization signal allocation unit 6, an allocation unit 7 control signals, response signal generating unit 8, digital and analog sensor interrogation unit 9, decryption unit 10, first register 11, first digital to analog converter unit 12 (DAC unit), shift register 13, OR-NOT 14 element, second re bar 15.

 The synchronization signal extraction unit 3 comprises a first SSC signal detector 16, a first SSC signal recovery unit 17.

 The control signal extraction unit 4 comprises a first comparator 18, a first reference voltage source 19.

 The control unit 5 comprises a first key 20, a microcomputer 21, an IR receiver 22, a keyboard unit 23.

 The synchronization signal extraction unit 6 comprises a second SSC signal recovery unit 24, a second SSC signal detector 25, a first AND element 26.

 The control signal extraction unit 7 comprises a second voltage reference source 27, a second comparator 28, and a trigger 29.

 The response signal generating unit 8 comprises a delay element 30, a second key 31, a second key 31, a second AND element 32. D-trigger 33.

 Block 9 polling digital and analog sensors contains a block 34 of the comparators. The second block 35 is a digital-to-analog converter DAC multiplexer 36.

 The SSC signal generator 1 generates a signal whose shape with the inputted control pulses is shown in FIG. 2A and 3A.

 Decoupling unit 2 is intended for decoupling the low-impedance output of the SSC signal generator 1 and the outputs of the keys 20 and 31.

 The first and second detectors 16 and 25 of the SSC signal are designed to separate the SSC signal into its constituent signals: A frame blanking pulse, B horizontal blanking pulse, C strobe pulse of the flash signals.

 Blocks 17 and 24 of the signal recovery can be made in the form of a low-pass filter (low-pass filter).

 The device operates as follows.

 The signal from the output of the SSC signal generator 1 through the isolation unit 2 and the first SSC signal recovery unit 17 (Fig. 2A and 3A) is input to the first SSC signal detector 16, signals A, B, C, from the output of which (Fig. 2e, d , c and 3d, d, c) are fed to the inputs of the microcomputer 21. The microcomputer 21 is synchronized by the signals A, B, C, in accordance with the program of work and received from the IR receiver 22 and the keyboard block 23, generates pulses ( Fig. 2b and 3b), which the first key 20 in the form of pulses of the control signal are input into the signal SSC.

 SSC signal recovery blocks 17 and 24 are designed to suppress these pulses before applying the SSC signal to the SSC signal detectors 16 and 25. The signal SSC, with the entered control pulses (Fig. 2A and 3A) is fed to the second comparator 28, to the gate input of which the signal A is received (Fig. 2e and 3d). As a result of comparing the SSC signal with the level of the second reference voltage source 27 and as a result of the gating by signal A at the first and second outputs of the comparator 28, the signal of FIG. 2e, and 3e, and) i.e. control pulses located in the active part of the lines in the interval of the quenching pulse, control pulses taken from the first output of the comparator 28 (Figs. 2e and 3e) set the trigger 29 to the "log. 1" state in the "log. 0" state at the S-input "trigger 29 returns on the trailing edge of the pulse B (Figs. 2d and 3d) supplied to its C-input, the D-input of trigger 29 is connected to the level of" log. 0 ".

 The output signal of the trigger 29 (Figs. 2g and 3g) is fed to the input of the shift register 13, to the synchronization input of which pulses from the output of the element And 26 (Figs. 2z and 3z) are received, when signals A and B coincide. As a result, in the register 13 of the shift after the end of the frame blanking pulse, a parallel code of the received control command is recorded, containing in one part N bits of the address of the actuator and located on the address output of the shift register 13, and in the second part of M bits of data output to the information output of the shift register 13 a. These M data bits are fixed in the actuator at the selected address after the end of the frame blanking pulse. The address of the actuator is decrypted by the decryption unit 10 and fed to the gate inputs of the register 11, the DAC unit 12, the register 15 and the DAC unit 35. The signal from the output of the element OR NOT 14 allowing information to be transmitted along the trailing edge of the pulse A is sent to the gate input of the decryption unit 10 (Fig. . 2k and 3k) when the BIT is in the zero state, the operation mode is selected at the first output of the second register 15. To expand the addressing capabilities of executive devices, the decryption unit 10 has additional inputs. The outputs of the register 11 are intended for switching in the Executive units. The outputs of block 12 DACs are designed to control analog blocks.

 One of the bits of the information output of the shift register 13 is for transmitting a bit for selecting a device operation mode. The setting of this category B "log. 1" puts the device in the mode of issuing information from a peripheral station to a central station. This discharge is fixed at the first output of the second register 15 by a gating pulse from the decryption unit 10.

 The transmission of information from the peripheral station 8 of the microcomputer 21 is carried out in three stages.

First, in the second block 35 of the DAC, the value of the parameter of interest to us is recorded. In the next frame quenching pulse, a command containing:
second register address 15,
operation mode selection bit in the "log. 1" state,
To bits of data transmitted through the second register 15 to the address inputs of the multiplexer 36.

 Information at the output of the register 15 appears on the trailing edge of the pulse A. The appearance of “log. 1” at the first output of the register 15 allows the passage of information from the multiplexer 36 to the input of the D-trigger 33.

 Direct input of information from a peripheral station occurs with the beginning of the next, third, frame blanking pulse.

 On the leading edge of the strobe pulse supplied to the synchronizing input of the D-trigger 33, the state of the input of the multiplexer 36 (Fig. 3l), supplied through the D-input to the output of the D-trigger 33 (Fig. 3m), is overwritten. Thus, before the arrival of the gate And 32 to the third input, the delayed gating pulse from the output of the delay element 30 (Fig. 3n), the state of the selected comparator from the block 34 of the comparators at the time corresponding to the start of the gate from microcomputer 21. The signal removed from the inverse output of the comparator 28 and delayed by the delay element 30 (Fig. 3n) whose trailing edge resets the second register 15, gates the passage of information from the output of the D-trigger 33 through the And 32 element. At the input of the key 31, which implements information on the SSC bus in the mode of transmitting information from the peripheral station to the central station, the delay element 30 delays the input signal for a time exceeding its duration, and the control pulse is introduced into the SSC signal by the central station. In this mode, it leads to the appearance of the same pulse after the first (Fig. 3b) only if there is a level of "log. 1" at the output of the D-trigger 33 (Fig. 3m), and therefore at the output of the multiplexer 36 (Fig. 3d) .

 Let us describe the structure of a command for transmitting information from a peripheral station.

 In the active part of the lines of the blanking pulse (except the first), a pulse is supplied that determines the moment of gating information from the output of multiplexer 36 (taking into account the delay time of element 30) to the first input of multiplexer 36 receives information from block 34 of comparators, the first input of which receives information from analog blocks of actuators, the second input of block 34 of the comparators is connected to the output of block 35 of the DAC. Thus, the status information of the analog and digital units can be transmitted to the central station. Using the comparator 18 and the reference voltage source 19, information is extracted for further processing in a microcomputer 21.

 The proposed device operates in two modes.

 The first transmission of control commands from the central station to the peripheral station.

 The second is to receive one BIT of information from a central station about the status of a digital or analog unit of a peripheral station. To do this, you need to transfer three commands.

 1. Write the value of the parameter of interest to block 35 DAC.

 2. Write in the register 15 the address of the comparator in block 34, the second input of which receives the parameter of interest to us.

 3. To give a pulse from the central station, gating the comparison in the comparator of the actual value of the parameter with the value recorded in block 35 of the DAC.

 For joint work of the central station with an external computer (for example, in a manufacturing process), a request pulse is generated in the active part of the first line of the blanking pulse of the external computer, which is analyzed by the micro-computer 21 in the central station “log. 1” and transfers the control function from the central station to an external computer.

 Using the introduced D-flip-flop makes it possible to increase the accuracy of reading analog sensors, since it eliminates the influence of the duration of the strobe pulse and the influence of the parameters of the delay element at the time of the gating of the multiplexer output.

Claims (1)

 A television receiver control device, characterized in that, in order to improve control accuracy by increasing the accuracy of reading analog sensors, a D-trigger is introduced into the response signal generation unit, while the first input of the response signal generation unit is connected to the second input of the second element And through D- the input of the D-trigger, the synchronizing input of which is connected to the input of the delay element.

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