RU2066936C1 - Device for control of tv receiver - Google Patents

Abstract

FIELD: TV devices. SUBSTANCE: device has SSC signal generator 1 and decoupling unit 2. Main station part of device has unit 3 which detects synchronization signals, unit 4 which detects control signals, control unit 5. Peripheral station part of device has unit 6, which detects synchronization signals, unit 7 which detects control signals, unit 8 which outputs response signal, unit 9 which requests digital and analog sensors, decoding unit 10, registers 11, 13, and 15, digital-to-analog converter 12, NOR gate 14, NOT gate 16, AND gate 17. Device operates in two modes. In first mode it sends control commands from main station to peripheral one. In second mode it receives one information bit at main station about state of digital or analog unit of final-control circuit at peripheral station. Device provides possibility to connect several main stations or external computers to information bus. Their concurrent operations are controlled by OR gate at information bus. This goal is achieved by introduced AND gate 17 and NOT gate 16. Other claims of invention describe specific design of unit 6 which detects synchronization signals, and generator 1. EFFECT: increased functional capabilities. 4 cl, 3 dwg

Description

 The invention relates to television technology, can be used in television receivers and is an improvement of the known device described in application N 4151717 / 24-09, a positive decision from 12/13/86.

 The aim of the invention is the expansion of functionality by providing control of various electronic equipment.

 In FIG. 1 is an electrical block diagram of a television receiver control device.

 In FIG. 2, 3 timing diagrams explaining the operation of the device.

 The television receiver control device (FIG. 1) comprises an SSC signal generator 1; junction block 2; at the central station, a synchronization signal extraction unit 3, a control signal allocation unit 4, a control unit 5; at the peripheral station, a synchronization signal extraction unit 6, a control signal extraction unit 7, a response signal generating unit 8, a digital and analog sensor polling unit 9, a decryption unit 10, a first register 11, a digital-to-analog converter (DAC) unit 12, a shift register 13, an element OR NOT 14, second register 15, first element NOT 16, third element AND 17.

 The synchronization signal extraction unit 3 comprises a first SSC signal recovery unit 18.

 The control signal extraction unit 4 comprises a first comparator 19, a first reference voltage source 20.

 The control unit 5 comprises a first key 21, a microcomputer 22, an IR receiver 23, a keyboard unit 24.

 The control unit 5 comprises a first key 21, a microcomputer 22, an IR receiver 23, a keyboard unit 24.

 The synchronization signal extraction unit 6 comprises a second SSC signal recovery unit 25, a first AND element 26, a second trigger 27, and a second element 28.

 Block 7 selection of control signals contains a second source 29 of the reference voltage, the second comparator 30, trigger 31.

 The response signal generating unit 8 comprises a delay element 32, a second key 33, a second AND element 34.

 Block 9 polling digital and analog sensors contains a block 35 of the comparators, digital-to-analog Converter 36 (DAC), the multiplexer 37.

 The control device of the television receiver operates as follows.

 Let the signal generator 1 is made in the form of a constant voltage source. The output voltage of the SSC signal generator 1 through the isolation unit 2 is supplied to the exchange bus and then through the first synchronization signal recovery unit 18 to the input of the micro-computer 22. The micro-computer 22 analyzes the state of the bus in accordance with the program of work and received from the IR receiver 23 and block 24 of the keyboard with a free command exchange bus. That is, if there is a constant level of “log. 1” on it, it starts to generate synchronization pulses with the control pulses introduced into them (Fig. 2b and 3b), which are entered by the first key 21 onto the control bus (Fig. 2a and 3a). Blocks 18 and 25 recovery of the synchronization signal are designed to suppress control signals and highlight the synchronization signal (Fig. 2B and 3B). One control pulse is introduced into one synchronization pulse. The so-called start pulse, which means the beginning of the transmitted group of bits (for example, the beginning of the byte), is necessarily introduced into the first synchronization pulse.

 The synchronization signal with the introduced control pulses is fed to the input of the second SSC signal recovery unit 25 (Figs. 2a and 3a), at the output of which sync pulses are obtained (Figs. 2c and 3c). The trailing edge of this signal supplied to the C-input of the second trigger 27, the inverse output of the second trigger 27 is set to the state "log. 1" (Fig. 2d and 3d). This allows the passage of synchronizing pulses to the output of the first element And 26 (Fig. 2e and 3d). The output of the second trigger 27 to the state “log. 1” is set by the S-input of signals from the output of the third element And 17, issued after receiving the entire sequence of clock pulses transmitted from the central station. In this case, the passage of clock pulses to the output of the And 26 element, blocking the operation of the second comparator 30 and through the OR element NOT 14 of the decryption unit 10, is blocked. The second element NOT 28 inverts the clock before feeding them to the clock input of the shift register 13.

 The synchronization signal with the introduced control pulses (Fig. 2A and 3A) is also fed to the second input of the second comparator 30, to the gate input of which the synchronization signal is output from the output of the first element And 26 (Fig. 2e and 3d). As a result of comparing the signal on the exchange bus with the voltage of the second reference voltage source 29 and gating, a signal is generated at the first and second outputs of the comparator 30 (Fig. 2e, l and 3e, l), that is, control pulses are emitted. The control pulses taken from the first output of the comparator 30 (Figs. 2e and 3e) set the inverse output of the trigger 31 to the "log. 1" state at the C-input (Figs. 2g and 3g). In the state "log. 0" of the trigger 31 is returned by the zero level of the synchronization signal supplied to its S-input. D-input of the trigger 31 is connected to the level of "log. 0". The output signal of the trigger 31 is fed to the input of the shift register 13, to the synchronization input of which an inverse synchronization signal is supplied, that is, the input of the shift information 13 is carried out on the trailing edge of the synchronization pulses. After the arrival of the last bit of information, i.e. the last pulse of the synchronization signal with the control signal entered, the start bit will appear at the first output of the shift register 13, that is, the level of “log. 1” (Figs. 2z and 3z). In this case, at the address and information outputs of the shift register 13, a parallel code of the received control command is recorded, containing respectively N address bits and M data bits. The address part of the code goes to the first address inputs of the decryption unit 10, and the data goes to the inputs of the execution units 11, 12, 15, 36. The address of the actuator is decrypted by the decryption unit 10 and goes to the gate inputs of the blocks 11, 12, 15 and 36. At the gate the input of the decryption unit 10 receives a signal from the output of the OR-NOT 14 element (Figs. 2k and 3k), allowing the formation of the output signal of the decryption unit 10 after entering all the information into the shift register 13, that is, when the start bit appears on the first output of this register (Fig. . 2z and 3z) and the zero state of the operating mode selection bit at the first output of the second register 15 and at a low level of the synchronizing signal (Figs. 2c and 3c). As you can see, the processing of information in the peripheral circuit occurs after receiving the entire sequence of bits, during the inactive part (low level) of the synchronizing pulse.

 The shift register 13 is reset by a signal from the output of the third element And 17 (Figs. 2i and 3i), supplied to the input of the unit to zero of register 13 if there is a “log. 1” at the first output of this register and along the leading edge of the synchronizing pulse (Fig. 2c and 3c), that is, after the address of the actuator is decrypted by the decryption unit 10. Thus, the preparation of the shift register 13 is carried out to receive the next sequence of bits.

 To expand the addressing capabilities of actuators, the decryption unit 10 has additional inputs.

 The outputs of the register 11 are intended for switching in the Executive units.

 The outputs of block 12 DACs are designed to control analog blocks.

 One of the bits of the information output of the shift register 13 is for transmitting a bit for selecting a device operation mode. Setting this category to "log. 1" puts the device in the mode of issuing information from a peripheral station to a central station. This discharge is fixed at the first output of the second register 15 by a gating pulse from the decryption unit 10.

 Information transfer from the peripheral station to the microcomputer 22 is carried out in three stages.

First, the value of the parameter of interest to us is recorded in the DAC 36. In the next package, a command containing:
second register address 15,
operation mode selection bit in the "log. 1" state,
To bits of data transmitted through the second register 15 to the address inputs of the multiplexer 37.

 Information at the output of the register 15 appears on the trailing edge of the last synchronizing pulse (Fig. 2e and 3d). The appearance of "log. 1" at the first output of the register 15 allows the passage of information from the multiplexer 37 to the second key 33.

 Direct transmission of information from a peripheral station is carried out in the third group of clock pulses.

 During one of the clock pulses, the microcomputer 22 gives out a gating pulse (Figs. 3a and 3b), which, through the inverse output of the comparator 30 (Fig. 3i) and the delay element 32 (Fig. 3m), gates the passage of information from the output of the multiplexer 37 (Fig. 3h) to the input of the key 33 (Fig. 3o). By the delay element 32, the input signal is delayed by a time exceeding its duration (Fig. 2m and 3m). The trailing edge of this pulse is reset to “log. 0” register 15. The second key 33 implements the information into the signal (Fig. 3a). Thus, the control pulse, introduced into the synchronization signal by the central station in the mode of transmitting information from the peripheral station, leads to the appearance of the second of the same pulse after the first only if there is a level of "log. 1" at the output of the multiplexer 37. When the output state of the multiplexer 37 in "log. 0" the introduction of the second impulse key 33 is not performed. By the presence or absence of a second pulse after the first micro-computer 22 determines the output state of the multiplexer 37.

 The first input of the multiplexer 37 receives information from the output of the block 35 of the comparators, the first input of which receives information from the analog blocks of the Executive circuit. The second input of the block 35 of the comparators is connected to the output of the DAC 36. Writing the value of the parameter of interest to the DAC 36 and submitting the corresponding address to the second register 15, you can enter the microcomputer 22, which together with the DAC 36, the block 35 of the comparators and the multiplexer 37 forms an analog- digital converter, status of the selected sensor. The outputs of the digital blocks of the Executive circuit are supplied to the second inputs of the multiplexer 37 and can be entered into the microcomputer 22 after setting the address in the register 15 and applying a gating pulse.

 The proposed device operates in two modes.

 The first transmission of control commands from the central station to the peripheral station.

The second is the receipt of one bit of information by the central station about the status of the digital or analog block of the Executive circuit of the peripheral station. To do this, pass three commands:
1) write in the DAC 36 the value of the parameter of interest;
2) write in the register 15 the address of the comparator in block 35, the second input of which receives the parameter of interest to us.

 3) give a pulse from the central station, gating the issuance of information about the comparison in the comparator of the actual value of the parameter with the value recorded in the DAC 36.

 In the proposed device, it is possible to connect several central stations or external computers to the exchange bus. Their joint work is possible thanks to the wired "or" function on the exchange bus. The function of arbitration between several operating central stations or computers is carried out as follows: the central station, which will first start the transmission of synchronizing pulses, occupies the exchange bus. The remaining central stations or computers analyze her condition and, in case of employment, await her release. If two central stations begin to transmit synchronization pulses simultaneously, then arbitration is carried out using the transmitted information. If the information matches, then both stations transmit it at the same time until one of the central stations in the next clock pulse introduces a control pulse, and the second does not. Then the second station, analyzing the state of the exchange bus, determines the mismatch of the information transmitted by it and the state of the bus. As a result, this station goes into standby mode, and the first continues to work. With the simultaneous joint operation of two or more central stations or computers, the duration of the synchronizing pulses is determined by the station that issues these pulses with the greatest duration.

 In addition to the case considered, the SSC signal generator 1 can be made in the form of a generator of periodic rectangular pulses, for example, horizontal quenching pulses in a television receiver. In this case, the operation algorithm of the device remains the same, except that now the microcomputer does not generate synchronizing pulses, but only control pulses, and the signals from the output of the SSC generator are used for synchronization.

Claims (4)

 1. The control device of the television receiver, characterized in that, in order to expand functionality by providing control of various electronic equipment at the peripheral station, the first element HE and the third element I are introduced, the output of which is connected to the combined additional inputs of the synchronization signal and shift register allocation unit , the additional output of which is connected to the combined input of the first element NOT and the first input of the third element AND, to the second input of which is connected the first output of the synchronization signal extraction unit, and the first input of the control signal extraction unit, the output of the first element NOT connected to the third input of the OR-NOT element.  2. The device of claim 1, characterized in that the synchronization signal extraction unit at the peripheral station is made in the form of series-connected second SSC signal recovery unit, the input of which is the first input of the synchronization signal extraction unit, the second trigger and the first element And, to the other input of which the first input of the second trigger is connected, the second input of which is an additional input of the synchronization signal extraction unit, as well as the second element NOT, whose input is combined with the first input of the second three and is the first output of the synchronization signal extraction block, the second and third outputs of which are respectively the outputs of the second element NOT and the first element I.  3. The device according to claim 1, characterized in that the SSC signal generator is made in the form of a constant voltage source.  4. The device according to claim 1, characterized in that the SSC signal generator is made in the form of a generator of periodic rectangular pulses.

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