RU2066933C1 - Device for control of tv receiver - Google Patents

Abstract

FIELD: TV devices. SUBSTANCE: device has SSC signal generator 1 and decoupling unit 2. Main station part of device has unit 3 which detects synchronization signals, unit 4 which detects control signals, control unit 5. Peripheral station part of device has unit 6, which detects synchronization signals, unit 7 which detects control signals, unit 8 which outputs response signal, unit 9 which requests digital and analog sensors, decoding unit 10, registers 11, 13, and 15, digital-to-analog converter 12, NOR gate 14, and D flip-flop 16. Device operates in two modes. Introduced D flip-flop 16 provides possibility to exclude wrong information reception by several peripheral stations which are connected in parallel when one of them sends information to main station. EFFECT: increased precision of control. 3 dwg

Description

 The invention relates to television technology, can be used in television receivers and is an improvement of the known device described in application N 4151717 / 24-09, a positive decision from 12/13/86, (2046549).

 The aim of the invention is to improve the accuracy of control by eliminating the reception of false information.

 In FIG. 1 is a structural electrical diagram of a television receiver control device.

 In FIG. 2 and 3 are timing diagrams illustrating the operation of the device.

 The television receiver control device (FIG. 1) comprises an SSC signal generator 1; isolation unit 2, at the central station: synchronization signal extraction unit 3, control signal extraction unit 4, control unit 5 at the peripheral station: synchronization signal extraction unit 6, control signal extraction unit 7, response signal generation unit 8, digital and polling unit 9 analog sensors, decryption unit 10, first register 11, digital to analog converter (DAC) block 12, shift register 13, OR-NOT 14 element, second register 15, D-trigger 16.

 The synchronization signal extraction unit 3 comprises a first SSC signal detector 17, a first SSC signal recovery unit 18.

 The control signal extraction unit 4 comprises a first comparator 19, a first reference voltage source 20.

 The control unit 5 comprises a first key 21, a microcomputer 22, an IR receiver 23, a keyboard unit 24.

 The synchronization signal extraction unit 6 comprises a second SSC signal recovery unit 25, a second SSC signal detector 26, a first AND element 27.

 The control signal extraction unit 7 comprises a second voltage reference source 28, a second comparator 29, and a trigger 30.

 The response signal generating unit 8 comprises a delay element 31, a second key 32, a second AND element 33.

 Block 9 polling digital and analog sensors contains a block 34 of the comparators, digital-to-analog Converter 35, the multiplexer 36.

 The control device of the television receiver operates as follows.

 The signal from the output of the SSC signal generator 1 through the isolation unit 2 and the first SSC signal recovery unit 18 (Figs. 2a and 3a) is input to the first SSC signal detector 17, the signals A, B, C from the output of which (Fig. 2e, d, c and 3 d, d, c) are fed to the inputs of the micro-computer 22. The micro-computer 22 is synchronized by signals A, B, C and, in accordance with the work program and received from the IR receiver 23 and the keyboard block 24, generates pulses ( Fig. 2b and 3b), which the first key 21 in the form of pulses of the control signal are input into the signal SSC. SSC signal recovery blocks 18 and 25 are designed to suppress these pulses before applying the SSC signal to the SSC signal detectors 17 and 26. The SSC signal with the entered control pulses (Figs. 2a and 3a) is supplied to the second comparator 29, to the gate input of which the signal A is received (Figs. 2e and 3d). As a result of comparing the SSC signal with the level of the second reference voltage source 28 and as a result of gating with signal A, a signal is generated at the first and second outputs of comparator 29 (Fig. 2e, and 3e, and), i.e. control pulses located in the active part of the lines in the interval of the frame blanking pulse. The control pulses taken from the first output of the comparator 29 (Figs. 2e and 3e) are set at the S-input of the trigger 30 to the state "log. 1". In the state "log. 0", the trigger 30 is returned on the trailing edge of the pulse B (Fig. 2d and 3d), supplied to the C-input of the trigger 30, the D-input of which is connected to the potential "log. 0". The output signal of the trigger 30 (Figs. 2g and 3g) is fed to the input of the shift register 13, to the synchronization input of which pulses from the output of the element And 27 (Figs. 2z and 3z) are received, when signals A and B coincide. As a result, in the register 13 of the shift after the end of the frame blanking pulse, a parallel code of the received control command is recorded, containing in one part N bits of the address of the actuator and located on the address output of the shift register 13, and in the second part of M bits of data output to the information output of the shift register 13 a. These M data bits are fixed in the actuator at the selected address after the end of the frame blanking pulse. The address of the actuator is decrypted by decryption unit 10 and fed to the gate inputs of blocks 11, 12, 15, and 35. A signal from output OR NOT 14 allowing information to be transmitted along the trailing edge of pulse A is sent to the gate input of decryption unit 10 (Figs. 2k and 3l) at the state of the operation mode selection bit at the first output of register 15 is zero. To expand the addressing capabilities of executive devices, decryption unit 10 has additional inputs. The outputs of the register 11 are intended for switching in the Executive units. The outputs of block 12 DACs are designed to control analog blocks.

 One of the bits of the information output of the shift register 13 is for transmitting a bit for selecting a device operation mode. Setting this category to "log. 1" puts the device in the mode of issuing information from a peripheral station to a central station. This discharge is fixed at the first output of the second register 15 by the gating pulse from the decryption unit 10 and at the input of the D-trigger 16 along the leading edge of the pulse A (Fig. 3k).

Information transfer from the peripheral station to the microcomputer 22 is carried out in three stages. First, the value of the parameter of interest to us is recorded in the DAC 35. In the next frame blanking pulse, a command is transmitted containing:
second register address 15,
operation mode selection bit in the "log. 1" state,
To bits of data transmitted through the second register 15 to the address inputs of the multiplexer 36.

 Information at the output of register 15 appears on the trailing edge of pulse A. The appearance of “log. 1” at the first output of register 15 allows the passage of information from multiplexer 36 to the second key 32.

 Direct input of information from a peripheral station occurs with the beginning of the next, third, frame blanking pulse.

 At the same time, a “log. 1” appears on the output of the D-flip-flop 16 (Fig. 3k), which, entering the zero input of the shift register 13, blocks the entry of false information into it.

 The inverse output of the comparator 29 through the delay element 31 gates the passage of information from the output of the multiplexer 36 to the input of the key 32 (Figs. 2i and 3i). By the delay element 31, the input signal is delayed by a time exceeding its duration (Figs. 2l and 3n). The trailing edge of this pulse resets to “log. 0” register 15. Key 32 implements information in the SSC signal. Thus, each control pulse introduced into the SSC signal by the central station, in the mode of transmitting information from the peripheral station, initiates the appearance of the second of the same pulse (Fig. 3o) after the first only if there is a level of "log. 1" at the output of the multiplexer 36 (Fig. . 3m).

 Let us describe the structure of a command for transmitting information from a peripheral station.

 In the active part of the lines of the blanking pulse (except the first), a pulse is supplied that determines the moment of gating information from the output of the multiplexer 36 (taking into account the delay time of block 31). The first input of the multiplexer 36 receives information from the block 34 of the comparators, the first input of which receives information from the analog blocks of the controlled circuit. The second input of the comparator unit 34 is connected to the output of the DAC 35. Thus, the status information of the analog and digital units can be transmitted to the central station.

 Using the comparator 19 and the reference voltage source 20, information is extracted for processing it in the microcomputer 22. With the arrival of the next, fourth, frame blanking pulse at the output of the D-trigger 16, the “log. 0” level is fixed, which unlocks the shift register 13 , thereby allowing the input of information into it.

The proposed device operates in two modes:
first transmission of control commands from the central station to the peripheral station,
the second receiving one bit of information from the central station about the status of the digital or analog unit of the peripheral station. To do this, pass three commands:
1) write in the DAC 35 the value of the parameter of interest;
2) write in register 15 the address of the comparator in block 34, the second input of which receives the parameter of interest to us;
3) apply a pulse from the central station, gating the comparison in the comparator of the actual value of the parameter with the value recorded in the DAC 35.

 To carry out joint work of the central station with an external computer (for example, in a manufacturing process), a request pulse is generated in the active part of the first line of the blanking pulse of the external computer, which is analyzed by the micro-computer 22 in the central station. "Log. 1" in the first line transfers control functions from the central station to the external computer.

 Using the introduced D-flip-flop eliminates the false reception of information by several peripheral stations connected in parallel if one of them transmits information to the central station.

Claims (1)

 A television receiver control device, characterized in that, in order to improve control accuracy by eliminating the reception of false information, a D-trigger is introduced at the peripheral station, the output of which is connected to an additional input of the shift register, the additional output of which is connected to the D-input of the D-trigger, to the C-input of which the output of the synchronization signal extraction unit is connected.

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