RU2048706C1 - Device for generation of two-pulse signal - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device has two modulo-two adders 2, 4, two flip-flops 1, 3, registers 10, 11, combinatorial function generator 9, low-pass filter 12, NOT gate 13. Introduced combinatorial function generator, registers, low-pass filter and NOT gate reduce emittance to environment. EFFECT: increased functional capabilities. 3 dwg

Description

 The invention relates to techniques for electrical communications, in particular to devices for generating a bi-pulse signal, and may find application in the transmission of signals over subscriber lines of digital telephone sets.

 A device for generating a bi-pulse signal is known, which contains differentiating blocks, triggers, AND elements, OR elements, and a delay unit included between the input information bus and the output bus.

 A disadvantage of the known device for generating a bi-pulse signal is the significant complexity of its design.

 A device for generating a bi-pulse signal is known, comprising a first trigger connected by a direct output to the first input of the first adder modulo two, the second trigger, the second adder modulo two, an input information bus, an input clock bus, an input cyclic signal bus and an output bus.

 The disadvantage of such a device for generating a bi-pulse signal is a significant level of radiation into the environment. It also does not allow to provide a sufficiently high accuracy of the formation of a consistent bi-pulse signal. In addition, the known device for obtaining the required speed requires significant energy consumption.

 The purpose of the invention is to reduce the level of radiation in the environment.

 To this end, a device for generating a bi-pulse signal containing a first trigger connected directly to the first input of the first adder modulo two, the second trigger, the second adder modulo two, the input information bus, the input clock bus, the input bus of the cyclic signal and the output bus , a shaper of the counting conversion signal is introduced, connected by the output to the information input of the first trigger and connected by the information input and clock input, respectively, with the input information bus and with the input the bottom bus of the clock signal connected to the first input of the second adder modulo two, connected to the synchronization input of the second trigger, which is connected by an information input to the output of the first adder modulo two and connected by the output to the output bus and to the second input of the first adder modulo two, the first a register connected by an information input to the input bus of the cyclic signal, a second register, a low-pass filter and an element NOT, with the first and second registers connected by outputs to other information inputs of the form of the signal converter of the counting conversion and are connected by the clock inputs to the input bus of the clock signal connected via a low-pass filter to the second input of the second adder modulo two, the output of which is connected via the NOT element to the synchronization input of the first trigger, and the information input of the second register is connected to the input information bus .

 In FIG. 1 shows one of the possible variants of the proposed device for generating a bi-pulse signal; in FIG. 2 is one of the possible options for its shaper signal combinatorial functions; in FIG. 3 time charts characterizing their work.

 The device comprises a first trigger 1 connected by a direct output to the first input of the first adder 2 modulo two, the second trigger 3, the second adder 4 modulo two, the input information bus 5, the input bus 6 of the clock signal, the input bus 7 of the cyclic signal and the output bus 8 .

 The device also comprises a combinatorial function signal generator 9 connected by an output to the information input of the first trigger 1 and connected by an information input and a clock input, respectively, to the information input bus 5 and to the clock input bus 6, the first and second registers 10 and 11, a low-pass filter 12 and element 13. The input bus 6 of the clock signal is connected to the first input of the second adder 4 modulo two, connected by the output to the synchronization input of the second trigger 3. The second trigger 3 is connected to information m input to the output of the adder 2 modulo two and is connected by a direct output to the output bus 8 and to the second input of the first adder 2 modulo two. The first and second registers 10 and 11 are connected by information inputs, respectively, to the input bus 7 of the cyclic signal and to the input bus 5 of the information. The outputs of the first, second and third bits of the first register 10 and the outputs of the first and second bits of the second register 11 are connected to other inputs of the shaper 9 of the signal of the combinatorial function. The clock inputs of the first and second registers 10 and 11 are connected to the input bus 6 of the clock signal connected via a low-pass filter 12 to the second input of the second adder 4 modulo two. The output of the second adder 4 modulo two is connected through the element HE 13 with the synchronization input of the first trigger 1.

а₁ v

v а

а₁ v а

v а₂а

а₁, где а₁, а₂, а₃, а₄, а₅, а₆ и а₇ входные сигналы, представляющие собой тактовый сигнал, информационный сигнал и результаты временного сдвига сигнала информации и циклового сигнала;

,

,

,

и

инверсионные значения соответственно входных сигналов а1, а₃, а₄, а₆ и а₇;
v знак логического сложения.Shaper 9 signal combinatorial function is designed to generate an output signal in accordance with the mathematical expression
Z a ₃ a ₆ a ₇ a ₁ v a ₅ a ₆ a

a ₁ v

v a

a ₁ v a

v a ₂ a

a ₁ , where a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ and a ₇ input signals, which are a clock signal, an information signal and the results of a temporary shift of the information signal and the cyclic signal;

,

,

,

and

inversion values, respectively, of the input signals a1, a ₃ , a ₄ , a ₆ and a ₇ ;
v sign of logical addition.

The combinatorial function signal generator 9, shown in FIG. 2 only as one of the possible variants of implementation, contains multiplexers 14, 15 and 16, an OR element 17, an AND-NOT element 18 and an HE element 19. The first address input (A ₀ ) of the multiplexer 14 coincides with the input of the combinatorial function signal generator 9 connected to the output of the first discharge of the second register 11 and connected to the second address input (A ₁ ) of the multiplexer 15 and to the first address input (A ₀ ) of the multiplexer 16. The second address input (A ₁ ) of the multiplexer 14, the first address stroke (A ₀₎ of the multiplexer 15 and the second address input (A ₁₎ of the multiplexer 16 coincide with the driver inputs 9 signal combinatorial function, connected respectively to the output of the second bit of the second register 11 to the input bus 5 information and to the output of the first rank of the first register 10. The prohibition inputs (V) of the multiplexers 14 and 15 coincide with the inputs of the combinatorial function signal generator 9, connected respectively to the outputs of the third and second bits of the first register 10 and to the inputs of the AND-NOT element 18. Fourth information input (X ₄ ) multiplexer 14, the first and second information inputs of the multiplexer 15, the second information input (X ₂ ) of the multiplexer
16 and the input of the element HE 19 coincides with the input of the shaper 9 of the combinatorial function signal connected to the input bus 6 of the clock signal. The output of the OR element 17 coincides with the output of the shaper 9 of the signal of the combinatorial function. The inputs of the OR element 17 are connected to the outputs of the multiplexers 14, 15 and 16. The first information input (X ₁ ) of the multiplexer 14 and the third information inputs (X ₃ ) of the multiplexers 15 and 16 are connected to the output of the element NOT 19. The second information input (X ₂ ) of the multiplexer 14 and the fourth information inputs (X ₄ ) of the multiplexers 15 and 16 are connected to the power bus 20. The third information input (X ₃ ) of the multiplexer 14 and the first information input (X ₁ ) of the multiplexer 16 are connected to a common bus 21.

 The work of the proposed device for generating a bi-pulse signal is as follows.

A clock signal with a period T, which is supplied via an input bus 6 of a clock signal (see Fig. 3, k), is fed directly to the first input of the second adder 4 modulo two, and to the second input through a low-pass filter 12, which creates a delay for the interval approximately equal to T / 2. With each transfer of the clock frequency signal, the second adder 4 modulo two generates positive pulses that form a double clock frequency signal close to the square wave (see Fig. 3, l). This double clock signal through the element 13 is fed to the synchronization input of the first trigger 1, to the information input of which a signal (see Fig. 3, m) is output from the output of the shaper 9 of the combinatorial function signal. This signal is delayed by the first trigger 1 on T / 2 and fed to the first input of the first adder 2 modulo two (see figure 3, n), which controls the counting
the double clock frequency conversion performed by the second trigger 3. In this case, the double clock signal is supplied to the second trigger synchronization input from the output of the second adder 4 modulo two, the signal from the output of the first adder 2 modulo two is fed to the information input of the second trigger 3, and the signal from the direct output of the second trigger 3 is fed to the second input of the first adder 2 modulo two (see figure 3, p) and to the output bus 8. The second trigger 3 operates in the counting mode, if the signal at the output of the shaper 9 signal la combinatorial functions has a logic-one level, and a flip-flop mode, if the output signal shaper 9 combinatorial functions has a logic-zero level.

 In the shaper 9 of the signal of the combinatorial function, the signals from the output of the third bit of the first register 10, from the output of the second bit of the first register 10 and from the output of the AND-NOT 18 element are respectively sent to the prohibition inputs of the multiplexers 14, 15 and 16 (see Fig. 3, g, e, and). Due to this, and also due to such a structure of the cyclic synchronization signal, in which it has the form of single zero bursts separated by series of single bursts (for example, a periodically repeating combination 11111110), the multiplexers 14, 15 and 16 work strictly alternately, namely, the multiplexer 16 only works during the time interval when the signals at the outputs of the second and third bits of the first register 10 (see Fig. 3, e, g) have a value of logical one, the multiplexer 15 only works during the clock interval when cash at the output of the second bit of the first register 10 (see Fig. 3, f) has a logical zero value, and the multiplexer 14 only works during the clock interval when the signal at the output of the third bit of the first register 10 (see Fig. 3, g) has a logical zero value.

The first and second address inputs (A ₀ and A ₁ ) of the multiplexer 16 are fed signals from the outputs of the first category, respectively, of the second and first registers 11 and 10 (see Fig. 3, b, d), and the first, second, third and fourth information inputs (X ₁ , X ₂ , X ₃ and X ₄ ) of the multiplexer 16 are respectively supplied with a logic zero level (common bus 21), a clock signal from the input bus 6 of the clock signal (see figure 3, k), the output signal element NOT 19 and the level of the logical unit (bus 20 power). The operation of the multiplexer 16 is equivalent to reading the information signal from the output of the first bit of the second register 11 (see Fig. 3, b) in the first half of the clock period and reading the loop signal from the output of the first bit of the first register 10 in the second half of the clock period.

Information signals are sent to the first and second address inputs (A ₀ and A ₁ ) of the multiplexer 15, respectively, with the input information bus 5 (see Fig. 3, a) and the output of the first bit of the second register 11 (see Fig. 3, b) and the first, second, third and fourth information inputs (X ₁ , X ₂ , X ₃ and X ₄ ) of the multiplexer 15 are respectively fed a clock signal (see figure 3, k), the signal from the output of the element NOT 19 and the level logical unit. Due to this, at the output of the multiplexer 15, during one clock period, combinations of two signals of equal duration are formed, each of which corresponds to one of the address combinations, namely, the address combination "00" corresponds to the output combination "10", the address combination "01" output combination " 10 ", address combination" 10 "output combination" 01 "and address combination" 11 "output combination" 11 ".

Information signals are sent to the first and second address inputs (A ₀ and A ₁ ) of the multiplexer 14, respectively, from the outputs of the first and second bits of the second register 11 (see Fig. 3, b, c), and to the first, second, third and fourth information the inputs (X ₁ , X ₂ , X ₃ and X ₄ ) are respectively fed a signal from the output of the element NOT 19, the level of the logical unit, the level of the logical zero and the clock signal (see figure 3, k). Due to this, at the output of the multiplexer 14, combinations of two characters of equal duration are formed, each of which corresponds to one of the address combinations, and the address combinations “01”, “11” correspond to the address combinations “00”, “01”, “00” and “10” , "00" and "10".

 The output signals of the three multiplexers are combined in an OR element 17, the output of which is the output signal of the control signal of the counting conversion.

 At the output of trigger 3, a binary balanced bi-pulse signal is formed in which there is no accumulation of predominance of premises of one kind or another when transmitting zero premises of a cyclic signal (see Fig. 3, d).

 This is ensured by the formation in three-clock intervals, counting the one in which the zero sending of the cyclic signal is transmitted (clock intervals N 7, 10, 13, 16 in Fig. 3), combinations containing the same number, i.e. 3, logical zero and one characters. These clock intervals are indicated by arrows in FIG. 3. In each of the remaining clock intervals of duration T, one symbol of both types is contained.

 The first and second registers 10 and 11 can be performed on type 561IR2 microcircuits, the first and second triggers 1 and 3 on type 561TM2 microcircuits, and the adders 2 and 4 modulo two on type 561LP2 microcircuits.

 Multiplexers 14, 15 and 16 can be performed on type 561KP1 microcircuits, and elements NOT 13 and 19 and element HE 18 on type 561LA7 microcircuits.

 Technical and economic efficiency of the proposed device is associated with a decrease in the level of radiation in the environment. The latter, ceteris paribus, can significantly reduce the cost of using the device.

Claims (1)

 A DEVICE FOR FORMING A BI-PULSE SIGNAL containing a first trigger connected by a direct output to the first input of the first adder modulo two, the second trigger, the second adder modulo two, characterized in that a signal shaper of combinatorial function, first, second registers, low-pass filter and element NOT, and the output of the low-pass filter is connected to the first input of the second adder modulo two, the output of the signal shaper of the combinatorial function is connected to the information input of the first trigger, the input is blue whose resonance is connected to the output of the element NOT, the input of which and the synchronization input of the second trigger are connected modulo two to the output of the second adder, the second input of which, the low-pass filter input, the clock inputs of the registers and the first input of the signal shaper of the combinatorial function are the device’s clock input, information input which are the second input of the signal generator of the combinatorial function and the information input of the second register, the first and second outputs of which are connected to the third and fourth inputs of the form signal combiner of the combinatorial function, the fifth, sixth, seventh inputs of which are connected to the corresponding outputs of the first register, the information input of which is the input of the device cycle signal, the output of the first adder modulo two is connected to the information input of the second trigger, the output of which is connected to the second input of the first adder by module two and is the output of the device.

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