RU1809537C - Frequency-modulated code converter - Google Patents

Abstract

The invention relates to computing. Its use in information transmission equipment allows to increase speed. The converter contains a delay element 2 and triggers 4,5. Thanks to the introduction of elements NOT 1,3,6 elements AND 7 and an expander of 8 pulses, the pulses supplied to the inputs of the triggers 4,5 are not shorter than half the clock cycle of the input FM signals, the half-cycle of which may therefore be equal to the minimum working duration of the input pulses of the triggers 4, 5. 2 C.p. f-ly, 3 ill.

Description

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The invention relates to computer technology, is intended for converting a frequency-manipulated (FM) code into a code without returning to zero (BVN) and can be used in information transmission equipment.

The aim of the invention is to increase the speed of the converter.

In FIG. 1 is a structural diagram of a claimed converter (example of a specific embodiment); Fig. 2 shows possible embodiments of a pulse expander.

The converter contains the first element 1 NOT, the delay element 2, the second element 3 NOT D-flip-flops 4,5, the third element 6 NOT, the element 7 AND, and the pulse expander 8. . . :. .. -. - .. ...,

The pulse expander 8 can be implemented in various ways.

The pulse expander in figure 2 contains the first and second elements 9, 10 OR and the first and second delay elements 11,12 .:

The pulse expander of FIG. 3 contains an OR element 13.

The converter operates as follows.

The input of the converter receives information in the FM code. Delay element 2 delays the input information by approximately 3T / 4, where T is the cycle time (for more precise delay time requirements, see below). At trigger 4, the input signal is clocked by a delayed signal, at trigger 5, an inverted input signal is clocked by an inverted delayed signal from element 3 NOT. Element b does NOT invert the signal generated by trigger 4, Element 7 AND performs logical multiplication of the signals arriving at it, generating signals, each pulse in which corresponds to a single bit of the input FM information, but has a duration equal to half a clock cycle (for single bits following zero bits) or equal to a beat (for single bits following single bits - for example, in a packet of single bits).

The pulse expander 7 broadens the pulses with a duration of half the duration of the full cycle duration, as a result of which the B8H code is generated.

In the proposed converter, the pulses of the signals supplied to the inputs of the triggers are not shorter than a half clock cycle of the input FM information, therefore it is capable of converting FM information having a half-cycle duration equal to the minimum working duration of the input pulses of the triggers. Thus, the proposed converter is characterized by a higher speed in comparison with the prototype converter.

It should be emphasized that the proposed converter performs the conversion of the FM code into an IOM code, not necessarily requiring clock pulses for this purpose. In those cases where a sequence of clock pulses is required for the operation of the equipment for further processing of the DIA code connected to the output of the proposed converter, this sequence can be easily obtained using an isolator or a filter of clock pulses, the input of which is connected to the input of the proposed converter.

Claims (3)

1. The frequency-modulated code converter, comprising a delay element, the input of which is the input of the converter, and the first and second D-flip-flops, with the exception of the fact that, in order to increase the speed of the converter, the first - the third elements are NOT entered, the AND element and the pulse expander, the information input of the first D trigger and the input of the first element are NOT connected to the converter input, the output of the delay element is directly and through the second element NOT connected to the clock input of the first and inf the input of the second D-flip-flop, the output of the first element is NOT connected to the clock input of the second D-flip-flop, the inverse output of which is connected to the first input of the And element, the direct output of the first D-flip-flop through the third element is NOT connected to the second input of the And element, whose output is connected to the output of the converter through a pulse expander. 2. The Converter according to claim 1, with the exception that the pulse expander contains OR elements and delay elements, the input of the first delay element and the first input of the first OR element are combined and are the input of the expander, the output of the first delay element is connected to the second input of the first OR element, the output of which is directly and through the second delay element connected to the inputs of the second OR element, b (the stroke of which is the output of the expander. 3. The converter according to claim 1, with the fact that the pulse expander contains a delay element and an OR element, the first input of which is combined with the input of the delay element and is the input of the expander, the first and second outputs the third inputs of the OR element, the output of the co-, delay element is connected to the second and the second is the output of the expander. FIG. 0k / e. j