RU2042185C1 - Device for generation of video signal - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has address generators 1, 2, 3, commutator 4, memory unit 5, video signal generation unit 6, comparison unit 7. EFFECT: simplified design. 4 dwg

Description

 The invention relates to automation, computer and television technology and can be used in graphic information display systems with output to a television-type indicator device.

 The purpose of the invention is the simplification of the device.

 In FIG. 1 shows a functional diagram of a device; in FIG. 2 functional block diagram of RAM; in FIG. 3 blocks of comparison; in FIG. 4 television image of volumetric geometric objects.

 The device comprises a first 1, a second 2 and a third 3 address drivers, a switch 4, a RAM block 5, a video signal generation block 6, a comparison block 7. The address generator comprises registers 8, 9 and 10, an adder 11, a switch 12. There are a second 13, a third 14 and a fourth 15 control inputs, a fourth group of 16 information inputs, a second information input 17, a first control input 18, a first information input 19 and a sync input 20, information inputs of the first 21, second 22 and third 23 groups.

 Block 5 of the RAM contains drives 24-27, the element OR 28. Position 29 denotes its address input, 30 inputs enable reading (sampling), 31 block output.

 Block 7 comparison contains registers 32-35, comparators 36-39.

The formulas for the affine mapping of three-dimensional space to three-dimensional space are as follows:
x _zu a ₁ x _e + b ₁ y _e + s ₁ z _e + δ ₁
y _zu a ₂ x _e + b ₂ y _e + s ₂ z _e + δ ₂ (1)
z _zu a ₂ x _e + b ₃ y _e + s ₃ z _e + δ ₃
In the case of a raster scan of the image, affine mappings of the plane onto the screen plane are
x ⁱ _zu A ₁ x _e ^j + B ₁ ⁱ ;
_zu y ⁱ A _{e 2} x ⁱ + a ₂ ^i. (2)
Similarly, for the volume of expression (1) are reduced to
x ⁱ _zu A ₁ x _e ⁱ + B ₁ ⁱ ;
_zu y ⁱ A _{e 2} x ⁱ + a ₂ ^i; (3)
z ⁱ _zu = A ₃ x _e ⁱ + B ₃ ⁱ .

 The device operates as follows.

A microprocessor calculator (not shown) during the display of one frame performs the calculation of the coefficients A ₁ ⁱ , B ₁ ⁱ , depending on the relative position of the simulated image and the observer's visual system, the numerical values of which are recorded in the registers before the next i-th scan line is displayed 8 and 9.

The full address of the current memory block of the random access memory block is determined by the value of the coordinates x ⁱ , y ⁱ , z ⁱ , which are formed by the same shapers 1, 2 and 3.

Generator 1 the coordinates x _zu operates as follows.

The calculated values of the coefficients of the projective transformation A ₁ , B ₁ , recorded respectively in registers 8 and 9 in the intervals of the SGI and KGI, are set at the first information input of the adder 11, which, depending on the value of the sign digit at its control input, is configured to either sum or subtraction, at the information input of the register 10, passing through the switch 12, which during the SGI and OIG connects its second information input to the information input of the register 10.

 During the display of the i-th scan line of the image, the output of the adder 11 is connected to the information input of the register 10, made on TT-triggers, the information is recorded on the front of the pulses acting on its control input, and the output to its output on their decline.

The sum A ₁ x _e ^j + B ₁ ⁱ (see (3)) is formed at the output of the register 10, which, acting on the second information input of the adder 11, is added to the value A ₁ and gives the result A ₁ x _e ^{j + 1} + B ₁ ⁱ , which after a time interval equal to the period of the frequency acting on the control input of the register 10, is copied to its output. At the output of the shaper 1 is formed x ^{i, j} _zu equal to the expression (3).

Similarly, at the outputs of the shapers 2, 3 coordinates y _z , z _z , values y _z ^{i, j} , z _z ^{i, j are formed} . The values of A ₂ ⁱ , B ₂ ⁱ , A ₃ ⁱ , B ₃ ^i, respectively, are entered at the inputs of groups 22 and 23, which are entered into the registers of the shapers 2 and 3 by the control signals received respectively at the control inputs of these groups 22 and 23. Switch 4 serves to connect the address inputs of the RAM block 5 during the display of information to the outputs of the shapers 1, 2 and 3, and during the initial entry of information into the RAM block 5 to the bus of the microcomputer recording address.

 In block 6 of the formation of the video signal, the information signal from the output of block 5 is summed with the signal of the television clock on the input 20, and is fed to the output of the shaper of the video signal.

 Bitmaps of plane images, for example, shown in FIG. 4. Through the OR element 28, information from that drive is transmitted to the output of block 5, at the control input of which there is a permission signal. These control signals are generated in block 7.

The first inputs of comparators 36-39 are _zu signals x ^{i, j} or y _zu ^{i, j,} z _zu ^{i, j,} and on the second data stored in the registers 32-35 signs respective faces that are entered prior to image display and correspond to the geometrical arrangement in the three-dimensional coordinate system x, y, z of its faces. In the case shown in FIG. 3, these values will be x0; z is 0; xx ₁ ; yy ₁ .

Thus, the three-dimensional value of the current coordinates x _zy , y _zy , _zzu generated according to expressions (3) by the corresponding shapers 1, 2, 3 is converted into two-dimensional coordinate values (row and column numbers) of drives 24-27.

 The inventive device allows you to exclude from its structure N processors that process each face separately, and perform geometric transformations transforming, depending on the image angle, into exact analytical dependencies describing these transformations (see expression (1)).

 The proposed technical solution allows to perform with high accuracy the geometric transformations of the images formed on the television screen.

Claims (1)

 A DEVICE FOR FORMING A VIDEO SIGNAL, comprising first to third address formers, a switch, a random access memory block, the output of which is connected to the information input of the video signal conditioning unit, the output of which is the device output, the address input of the random access memory unit is connected to the output of the switch, the first and second information inputs which are connected respectively to the outputs of the first and second address formers, information and control inputs from the first to third address formers are I, respectively, information inputs from the first to third groups and control inputs from the first to third groups of the device, the information input and the write control input of the RAM block are the first information and control inputs of the device, the third information input and the control input of the switch are respectively the second information and control the inputs of the device, the sync input of the video signal generating unit is the third control input of the device, the first sync input of which The first control inputs of the address shapers are different, characterized in that it contains a comparison unit, the outputs of which are connected to the read enable inputs of the RAM block, the information inputs of the first group of the comparison block are connected to the outputs of the address shapers, the information inputs of the second group of the comparison block are information inputs of the fourth group devices, the second sync input of which are the second control inputs of the address formers, the fourth information input of the switch is connected Inen with the output of the third address former.

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