RU2028660C1 - Modulo-seven adder - Google Patents

Abstract

FIELD: computer engineering and microelectronics. SUBSTANCE: adder has nine equivalence gates, three modulo-two sum gates, inputs of high-, medium-, and low-order bits of first and second operands, outputs of high-, medium-, and low-order bits of result. Modulo-seven adder functions as follows. High-order bit x1, medium-order bit x2, and low-order bit x3 of first operand X=4x1+2x2+x3 as well as high-order bit y1, medium-order bit y2, and low-order bit y3 of second operand Y=4y+2y2+y3 arrive at inputs. Values of high-order bit r1, medium order bit r2, and low-order bit r3 of result (modulo-seven sum of input operands) R=(X+Y)mod7=4r1+2r+2+r3 are shaped across outputs. Here we have x_i∈ 10{0,1} y_i ∈{0,1} r_i∈ {0,1} 0 ≅ X ≅ 7, O ≅ Y ≅ 7, O ≅ R ≅ 7. EFFECT: enlarged functional capabilities. 1 dwg, 1 tbl

Description

 The invention relates to computing and microelectronics and can be used in the construction of devices operating in a system of residual classes.

 Known adder modulo seven, containing elements OR-NOT, AND, OR [1].

 The disadvantage of the adder is the low speed.

 The closest in functionality and design technical solution to the proposed one is an adder modulo seven, containing addition elements modulo two, OR, AND, OR-NOT [2].

 A disadvantage of the known adder modulo seven is the low speed.

 The drawing shows a diagram of the adder modulo seven.

 The adder contains nine elements of equivalence 1-9, three elements of addition modulo two 10, 11 and 12, inputs of the first (senior) 13, second (middle) 14 and third (minor) 15 bits of the first operand, inputs of the first (senior) 16, second (middle) 17 and third junior) 18 bits of the second operand, outputs of the first (senior) 19, second (middle) 20 and third (junior) 21 bits of the result.

 The output of the i-th (i = 1,2,3) addition element modulo two is connected to the output of the i-th bit of the result, and its j-th (j = 1,2,3) input is connected to the output (3i + j- 3) th element of equivalence. The first input 13 of the first operand is connected to the inverse input of the k-th (k = 1.9) equivalence element, the fourth input of the second addition element modulo two 11 and the fourth input of the third addition element modulo two 12. The second input 14 of the first operand connected to the first direct input of the first element of equivalence 1, first direct input of the third element of equivalence 3, first direct input of the fourth element of equivalence 4, first direct input of the fifth element of equivalence 5, first direct input of the seventh element of equivalence 7, p the first direct input of the eighth equivalence element 8 and the fifth input of the second addition element modulo two 11. The third input 15 of the first operand is connected to the second direct input of the first equivalence element 1, the first direct input of the second equivalence element 2, the second direct input of the fifth equivalence element 5, the first direct input of the sixth element of equivalence 6, second direct input of the eighth element of equivalence 8, first direct input of the ninth element of equivalence 9 and fifth input of the third element of addition modulo two 12. The first input 16 of the second operand is connected to the second direct input of the fourth element of equivalence 4, the third direct input of the seventh element of equivalence 7, the third direct input of the eighth element of equivalence 8, the second direct input of the ninth element of equivalence 9 and the fourth input of the first addition element modulo two 10. The second input 17 of the second operand is connected to the second direct input of the second element of equivalence 2, the second direct input of the third element is equal to 3, the third direct input of the fifth equivalence element 5, the third direct input of the seventh equivalence element 7, the third direct input of the ninth equivalence element 9 and the sixth input of the second addition element modulo two 11. Third input 18 of the second operand connected to the third direct input of the first element of equivalence 1, the third direct input of the second element of equivalence 2, the fourth direct input of the fourth element of equivalence 4, the second direct input of grained equivalence element 6, the fourth input of the eighth direct equivalence element 8, the ninth input of a fourth direct equivalence element 9 and the sixth input of the third element addition modulo two 12.

The adder modulo seven works as follows. At the inputs 13, 14 and 15, respectively, the senior x1, middle x2 and junior x3 bits of the first operand X = 4x1 + 2x2 + x3; at inputs 16, 17 and 18, respectively, the highest y1, the middle y2, and the lower y3 bits of the second operand Y = 4y1 + 2y2 + y3. At the outputs 19, 20, and 21, the values of the highest r1, middle r2, and lower r3 bits of the result are formed (the modulo sum is seven input operands) R = (X + Y) mod7 = 4r1 + + 2r2 + r3. Moreover, x _i ∈ {0, 1}, y _i ∈ {0, 1}, r _i ∈ {0, 1}, 0≅X≅7, 0 ,Y≅7, 0≅R≅7; i = 1, 2, 3.

, x2, y2)⊕ R(

, x2, x3,y3)⊕ R(

, x3, y2, y3);

2

x

, x3, y3)⊕ R(

, x2, x3,y1,y2)⊕

3

1

x

, x2, y1, y2)⊕ R(

, x2, x3,y1, y3)⊕
где R(˙) - функция равнозначности.The operation of the adder modulo seven is described by the following relationships:
r1 = y1 ⊕ R (

, x2, y2) ⊕ R (

, x2, x3, y3) ⊕ R (

, x3, y2, y3);

2

x

, x3, y3) ⊕ R (

, x2, x3, y1, y2) ⊕

3

1

x

, x2, y1, y2) ⊕ R (

, x2, x3, y1, y3) ⊕
where R (˙) is the equivalence function.

The values of the functions implemented by the adder r _i , i = 1,2,3 are shown in the table.

 A design feature of the adder is the formation of residual codes equal to 111 on some sets of input variable codes. This is permissible since 0mod7 = 7mod7, or in the binary number system 000mod7 = 111mod7, and the total operands are received at the inputs of the adder. This approach has significantly improved performance and simplified the design of the adder modulo seven.

Claims (1)

 A MODULATOR SUMMER SUM contains three addition elements modulo two, the first input of the first of which is connected to the input of the first bit of the second operand of the adder, the first and second inputs of the second addition element modulo two are connected to the inputs of the second bits of the first and second operands of the adder, first and the second inputs of the third addition element modulo two are connected to the inputs of the third digits of the first and second operands of the adder, respectively, characterized in that it contains nine elements of equivalence, the moves of the first, second and third of which are connected respectively to the second, third and fourth inputs of the first addition element modulo two, the outputs of the fourth to sixth and seventh to ninth equivalence elements are connected to the third to fifth inputs of the second and third addition elements respectively modulo two, the sixth inputs of which are connected to the input of the first bit of the first operand of the adder and with the inverse inputs of all elements of equivalence, the outputs of the addition elements modulo two are connected to the outputs of the corresponding bits of the result of the adder, the second input of the first operand of the adder is connected to the first direct inputs of the first, third, fourth, fifth, seventh and eighth elements of equivalence, the third input of the first operand of the adder is connected to the first direct inputs of the second, sixth and ninth and second direct inputs of the first , fifth and eighth equivalence elements, the first input of the second operand of the adder is connected to the second direct inputs of the fourth, seventh and ninth and third direct inputs of the fifth and of the seventh equivalence elements, the second input of the second operand of the adder is connected to the second direct inputs of the second and third, third direct inputs of the fourth, seventh and ninth and fourth direct inputs of the fifth equivalence elements, the third input of the second operand of the adder is connected to the third direct inputs of the first and second, fourth direct the inputs of the fourth, eighth and ninth and the second direct input of the sixth element of equivalence.

Images