RU2007760C1 - Device for decreased redundancy of measuring information - Google Patents

Abstract

FIELD: devices for information transmission. SUBSTANCE: device has serial-to-parallel code converter 1, redundancy decrease unit 2, memory unit 10, synchronization signals generator 11, register 16, pulse counter 23 and parallel-to- serial code converter 17. Two decoders 18 and 20, OR gate 15, switches 12, 13, 19, flip-flop 22, inverter 21 and registers 14 are introduced to accomplish the goal of invention. EFFECT: increased reliability and increased precision. 2 cl, 2 dwg

Description

 The invention relates to the transmission of information and can be used to reduce redundancy of information and the formation of a common stream for transmission over a communication channel.

 A device for reducing excess information (L. I "Aerospace telemetry", Military Publishing, M., 1968, p. 199-207, Fig. 4.17), containing a comparison unit, memory blocks, adder, counter, timer, key, a buffer storage device, a decoder, a decoder and a control unit, while the inputs of the comparison unit are connected to the outputs of the first and second memory units. This device converts the input stream of information words into a stream of significant samples, each of which differs from the previous one by more than the value of the predefined tolerance. The device also provides the accumulation of significant samples in the buffer memory and the regulation of the tolerance depending on the degree of filling of the buffer memory.

 The disadvantages of this device are the large amount of overhead address-time information that accompanies significant samples, the complicated procedure for determining the amplitude of the samples obtained due to the need to take into account the dynamics of tolerance changes, the uncertainty of the situation with a long absence of significant samples (either the actual absence of significant samples, or device failure).

 A device for reducing redundancy, comprising comparison blocks, memory blocks, a timer, an integrator, a delay block, keys, OR elements, increment calculators and a ban element, while the inputs of the first comparison block are connected to the outputs of the first memory block and the second comparison block, and the output the timer is connected to the input of the first key. This device provides a reduction in redundancy of information on complex algorithms with increased information content.

 The disadvantages of this device are a large amount of service address-time information, complicated selection criteria for significant samples, which reduces the flow of samples, but complicates the device, and this prevents its use in small-sized moving objects. In addition, the uncertainty of the situation associated with the long absence of significant samples has not been eliminated.

 A device is known for reducing the redundancy of measurement information in an adaptive multi-channel data transmission system, comprising a first memory register, the output of which is connected through a comparison unit to the output of the first memory unit, the first and second address inputs of which are connected to the corresponding inputs of the second memory unit and to the corresponding outputs of the counter , the first timer output through the serial to parallel converter is connected to the information input of the device, the second output is connected to the sync the input of the first memory register and the word input of the converter in series to the parallel input, the third output is connected to the counter setup input, and the fourth timer input is connected to the clock inputs of the second and third memory registers and the word input of the parallel converter to the serial input, the output of which is the information input of the device, the first the counter output is connected to the information input of the third memory register, the first and second information inputs of the second memory block are connected respectively with inputs of the upper and lower values of the device tolerances, the fourth memory register, and the control unit.

 This device provides the selection of significant samples and reducing the redundancy of the measurement information, while slightly reduced the amount of service address-time information due to the grouping of significant samples.

 This device for the intended purpose, the achieved result, the technical nature and coincidence with the proposed technical solution for the largest number of signs selected prototype.

 The disadvantages of this device are: firstly, there is still a large amount of service address-time information, the forced restriction of growth of which reduces the possibility of increasing the accuracy of the timing of significant samples, which worsens the accuracy of measurements, and secondly, the uncertainty of the situation with a long absence of significant samples, when it is not clear whether the device failed or is there really no significant sample, thirdly, crowding out of some groups of significant samples of compressed qi information poll-crystal parallel transmission of other parameters, which leads to loss of information.

 The aim of the invention is to increase the reliability and accuracy of measurements.

 The goal is achieved by the fact that in the known device for reducing redundancy of measurement information containing a redundancy reduction unit, the first information inputs of which are connected to the corresponding outputs of the serial to parallel converter, the input of which is the input bus of the device, the output bus of which is the output of the parallel to serial converter , a memory unit whose outputs are connected to the corresponding second information inputs of the reduction unit is redundant A, clock generator, the first and second outputs of which are connected respectively to the clock input of the serial code converter to parallel and to the word input of the parallel code converter to serial, the first register and pulse counter are two decoders, an OR element, a trigger, an inverter, a second register, three keys , the output of the first of which is connected to the counting input of the pulse counter, the control input is combined with the control input of the redundancy reduction unit and connected to the trigger output, the first and the information input of which is combined with the zeroing input of the pulse counter and is connected to the third output of the clock generator, the fourth, fifth and sixth outputs of which are connected respectively to the information input of the first key, the second information input of the trigger and the clock input of the parallel code converter to serial, the first information input of which is connected with the output of the first register, and the second information input connected to the output of the second register and combined with the input of the first decoder, the output which through an inverter is connected to the control input of the second key, the information input of which is combined with the sync inputs of the redundancy reduction unit and the second register, with the word input of the serial code to parallel converter and connected to the second output of the clock generator, and the output of the second key is connected to the sync input of the first register and is the output of the "flag" of the device, and the first output of the redundancy reduction unit is connected to the first input of the OR element, the output of which is connected to the information input ohm of the second register, and the second input with the output of the third key, the control input of which is connected to the output of the second decoder, the inputs of which are combined with the corresponding information inputs of the first register, the corresponding first address inputs of the redundancy reduction unit and connected to the outputs of the least significant bits of the pulse counter, the output of the highest the discharge of which is connected to the second address input of the redundancy reduction unit and the information input of the third key, while the second outputs of the redundancy reduction unit and connected to the information inputs of the memory block.

 In FIG. 1 shows a diagram of a device; and in FIG. 2 - time diagrams of his work.

 The device comprises a serial code to parallel converter 1, a redundancy reduction unit 2 made on comparison unit 3, keys 4, 5, adders 6 and 7, register 8, memory unit 9, memory unit 10, clock generator 11, keys 12 and 13, register 14, OR element 15, register 16, parallel-to-serial code converter 17, decoder 18, key 19, decoder 20, inverter 21, trigger 22, pulse counter 23.

 The device operates as follows.

 The information input of the device receives a stream of cyclic samples of constant length corresponding to the output of a multi-channel cyclic switch (Fig. 2-1). After conversion to parallel code in the converter 1, parallel cyclic samples are stored in the memory register 8, updated word by word (Fig. 2-2), and fed to the first information input of the comparison unit 3. A signal about the presence of a substantial sample (Fig. 2-10) is received at the second information input of the comparison unit 3 from the output of the first memory unit 10, as a result of which the key 4 is opened and the input current sample arrives with a double word frequency, the stream of reference signals, the odd of which are the sum of the value of the previous significant sample of the channel with the value of the upper tolerance, and even - the sum of the value of the previous significant sample of the same channel with the value of the lower tolerance (Fig. 2-3). The reference signals stored in the memory unit 10 are generated using adders 6, 7 and the memory unit 11, in which the upper and lower tolerance values recorded in it through the first and second information inputs are constantly stored. Two groups of reference signals in the memory unit 10 are stored respectively in cells with odd and even address values and are read respectively in the first and second half of each word interval. The formation of the read addresses of the reference signals from the output of the memory unit 10 is as follows. Using the frequency of the device’s cycle of operation (third output of the generator 11, Fig. 2-4) and a multiple of the cycle frequency of the samples arriving at the input of the device (fifth output of the generator 11 (Fig. 2-5), respectively, arriving at the second and first information inputs of the trigger 22, a key control signal 5 and 12 is generated (Fig. 2-6), the duration of which corresponds to the duration of one cycle of input samples. This cycle (for example, one of 16-256 cycles that together make up the device’s operation cycle) is the so-called “shadow” "the cycle in which the source cyclic samples are not subjected to the operation of reducing redundancy, that is, they are a priori read “significant” and all go to the output of the device.This aims to make sure that the device is working properly, and the possible absence of significant samples between the shadow cycle samples of each device operation cycle indicate about their actual absence, and secondly, with the beginning of the shadow cycle, the address-time binding of each significant sample is associated. In this case, a different address-time code has each initial cyclic sample throughout the entire cycle of the device. For example, during compression of 256 channels (8 bits) in the input cycle of samples and 256 cycles of samples in the device cycle (8 bits), the address-time code of each position that contains the initial cyclic sample in the device cycle corresponds to 16 bits, t i.e., twice the typical duration of the informational part of the sample (8 bits). Measures to reduce the output address-time information will be described below.

 When the key 12 is opened, counting pulses from the output of the generator 11 arrive at its output, according to which, after installation, at the beginning of each cycle of the device’s operation, the counter 23 generates information reading addresses from memory blocks 10 and 9 (Figs. 2–7 are the least significant bits) addresses, Fig. 2-8 - senior ranks). During the shadow cycle, the address of the zero cell is formed, in which the zero reference word is "stored" (Fig. 2-9). When comparing with the zero word any current sample arriving at the first information input of the comparison unit 3, from the output of the unit 3 necessarily goes to the output of this key. A similar signal is generated when comparing the reference signals with the current samples, if the latter are outside the tolerance, i.e., exceed the reference signal corresponding to the upper tolerance value, or are lower than the reference signal corresponding to the lower tolerance value (Fig. 2-11). From the output of the first key 4, the flow of significant choices and cyclic samples of the shadow cycle through the OR element 15 is fed to the information input of the register 16. Through the key 5, only the flow of one significant samples passes (Fig. 2-12), since only for them the inputs of the adders 6 and 7, signals of tolerance values are received (FIGS. 2-13 and 2-14, respectively). At the outputs of these adders, reference signals are generated representing, respectively, the sum of the current significant sample and the values of the upper and lower tolerances. Synchronously with the arrival of a significant sample in register 16, the lower bits of the address-time code corresponding to the position of this significant sample on the interval of the device’s cycle of operation are received in register 14. To reduce the total amount of address-time information, its high-order bits are transmitted in a dedicated information channel. In the original cyclic stream (Fig. 2-1), a zero word is transmitted in this channel. The address code of the dedicated channel is decrypted using a decoder 20, which generates a control signal for opening the key 19 (Fig. 2-15). The corresponding high-order bits of the address, common to the entire group of low-order bits, pass through the key 19 (Fig. 2-16), the OR element 15 and, together with significant samples and samples of the shadow cycle, are written to register 16 (Fig. 2-17), reading information the output of which is made with the word frequency of the input stream (Fig. 2-18). The read signal of the corresponding address-time code is generated using the first decoder 18, which selects zero words (i.e., words that are not significant samples), an inverter 21 and a key 13, which transmits word frequency pulses only if there are significant samples and sets of the shadow cycle. The output signal of the key 13 is also the output of the flag of a substantial sample of the device. The information output of the device receives sequentially a stream of information samples, which is a combination of a stream of significant samples, samples of shadow cycles and samples of information channels with high-order information of the address-time code (Fig. 2-19). In this case, significant samples and a sample with an address-time code is accompanied by word-by-word time-address information with a non-zero value. (56) Copyright certificate of the USSR N 1462392, cl. G 08 C 19/28, 1987.

 USSR author's certificate N 815935, cl. H 04 J 6/00, 1979.

Claims (2)

 1. A DEVICE FOR REDUCING THE REDUNDANCY OF THE MEASURING INFORMATION, comprising a redundancy reduction unit, the first information inputs of which are connected to the corresponding outputs of the serial to parallel converter, the input of which is the input bus of the device, whose output bus is the output of the parallel to serial converter, memory block, outputs which is connected to the corresponding second information inputs of the redundancy reduction unit, a clock generator, trans the second and second outputs of which are connected respectively to the clock input of the serial code converter to parallel and to the word input of the parallel code converter to serial, first register and pulse counter, characterized in that two decoders, an OR element, a trigger, an inverter, a second register are introduced into it three keys, the output of the first of which is connected to the counting input of the pulse counter, the control input is combined with the control input of the redundancy reduction unit and connected to the trigger output, the first information the ion input of which is combined with the zero input of the pulse counter and is connected to the third output of the clock generator, the fourth, fifth and sixth outputs of which are connected respectively to the information input of the first key, the second information input of the trigger and the clock input of the parallel code to serial converter, the first information input of which is connected with the output of the first register, and the second information input is connected to the output of the second register and combined with the input of the first decoder, the output of which first through the inverter is connected to the control input of the second key, the information input of which is combined with the sync inputs of the redundancy reduction unit and the second register, with the word input of the serial code converter in parallel and connected to the second output of the clock generator, and the output of the second key is connected to the sync input of the first register and is the output of the "flag" of the device, and the first output of the redundancy reduction unit is connected to the first input of the OR element, the output of which is connected to the information input w register, and the second input - with the output of the third key, the control input of which is connected to the output of the second decoder, the inputs of which are combined with the corresponding information inputs of the first register, corresponding to the first address inputs of the redundancy reduction unit and are connected to the outputs of the least significant bits of the pulse counter, high-order output which is connected to the second address input of the redundancy reduction unit and the information input of the third key, while the second outputs of the redundancy reduction unit are connected inens with the first information inputs of the memory block, the second information inputs of which are connected to the corresponding inputs of the pulse counter.  2. The device according to claim 1, characterized in that the redundancy reduction unit is made on a register, a comparison unit, two keys, two adders and a memory unit, the information inputs of which are the information bus of the redundancy reduction unit, the address inputs are the first and second address inputs of the block redundancy reduction, and the first and second outputs of the memory block are connected to the first information inputs of the first and second adders, respectively, the second information inputs of which are the trigger signal bus, outputs - the second outputs of the unit, and the clock inputs are combined and connected to the output of the first key, the control input of which is the control input of the redundancy reduction unit, and the information input is the first output of the redundancy reduction unit and is connected to the output of the second key, the information input of which is combined with the first input of the comparison unit and connected to the output of the register, the input of which and the second input of the comparison unit are respectively the first and second information inputs of the redundancy reduction unit, and the output is The comparison is connected to the control input of the second key, while the register clock is the clock input of the redundancy reduction unit.

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