RU2004133967A - MULTI-CHANNEL REWINDABLE DIGITAL RECEIVING TRACT - Google Patents

Claims (9)

1. A multi-channel reprogrammable digital receive path, comprising an input interface, a first and second analog-to-digital converter, connected in series between the input interface and at least two identical signal channels in the path, configured to perform the functions of analog-to-digital conversion, heterodyning, decimation and channel filtering of the input signal, and each of the channels used in series connected local oscillator, multiplexer and, unit signal decimation, and there is also at least one first filter-decimation unit, each of which channels is configured to use at least two routers designed to distribute signals, and all channels are configured to output the processed signal through a common output interface, to to which they are connected, and the receiving path also includes a control register and a synchronization unit, adapted for controlling the process of receiving, processing and transmitting a signal, characterized in that each of the channels further includes a second filtering-decimation unit and a signal amplitude-phase correction unit connected in series to the storage-issuing unit, the synchronization unit being able to synchronize independently the operation of at least two devices, and each of routers are made with the ability to not only switch the inputs and outputs of the blocks, but also, if necessary, to sum the signals of any two channels, moreover, the path yuchaet digital inputs executed in parallel analogue-digital converter adapted to receive input of a real or complex signal and transmitting it for further processing in a path to bypass the analog to digital converters. 2. The receiving path according to claim 1, characterized in that the decimation unit of the signal includes two filtering branches, each of which includes a first filter connected in series, including a first decimator and a first scaling unit, a first multiplexer, a second filter including a second decimator and a second block scaling, the second multiplexer, and the first scaling units and the second scaling units are interconnected via a logical "or" device. 3. The receiving path according to claim 2, characterized in that the second filter is configured to programmatically change the filter properties from 4th to 6th order, inclusive. 4. The receiving path according to claim 1, characterized in that the router includes a demultiplexer connected to complex adders constructed using an adder and a multiplexer, the number of complex adders corresponding to the number of signal transmission channels in the path, and the channel outputs are connected to the switch device. 5. The receiving path according to claim 1, characterized in that the first and second filtering-decimation blocks include a complex filter using the same coefficient memory and two independent data memory systems. 6. The receiving path according to claim 5, characterized in that a filter with a finite impulse response is used as a complex filter. 7. The receiving path according to claim 1, characterized in that it further comprises at least one ADC. 8. The receiving path according to claims 1 to 7, characterized in that at least two additional identical data channels are used, connected in parallel with existing data channels. 9. The receiving path according to any one of claims 1 to 7, characterized in that it is made in the form of a specialized integrated circuit.