KR101555215B1 - Apparatus and method of chaning sampling rate using first-in first-out module - Google Patents

Abstract

An apparatus and method for changing a sampling rate using a FIFO module are disclosed. N image rejection filters sequentially receiving digital signals sampled at a predetermined sampling rate and sequentially outputting the digital signals; A first-in first-out (FIFO) module for receiving a digital signal output from the N IR filters and sequentially outputting the input digital signal; M anti-aliasing filters for sequentially receiving and outputting the digital signals output from the FIFO module; And a summer for summing and outputting the digital signals output from the AA filter. The digital signal output to the summer is formed of a digital signal changed to a sampling rate having a N / M ratio with respect to the predetermined sampling rate. According to the above apparatus and method for changing the sampling rate using the FIFO module, the N sampling rate is changed to the N / M ratio by inserting the FIFO module in the middle of the N IR filters and the M AA filters. The sampling rate can be easily and simply changed. Also, the sampling rate can be changed immediately without increasing the sampling rate.

Description

[0001] APPARATUS AND METHOD OF CHANNING SAMPLING RATE USING FIRST-IN FIRST-OUT MODULE [0002]

The present invention relates to an apparatus and method for changing a sampling rate in digital signal processing, and more particularly, to a sampling rate change using a first-in first-out (FIFO) module And more particularly,

Conventionally, a process of interpolation and decimation is generally used in a process of changing a sampling rate in digital signal processing.

When the sampling rate is lowered, the sampling rate is increased by interpolation and then lowered by decimation.

In this case, if the sampling rate is changed to the N / M ratio with respect to the original sampling rate, the process is not complicated for simple integer ratios, but if the numerator and denominator values are large, such as 73/101, There is a problem that it becomes complicated and difficult. This will be described in more detail with reference to FIG.

1 is a block diagram of an apparatus for changing a sampling rate by an interpolation and decimation process according to the related art.

1 (b), the conventional sampling rate changing apparatus includes an interpolation module 10, an IR rejection filter 20, an AA filter (anti-aliasing filter) 30 and a decimation module and a decimation module 40.

1 (a) shows a process of changing a signal through each module of FIG. 1 (b).

The ratio of the interpolation to the decimation may be various ratios according to the digital signal. First, the circled signals are sampled at 150 Msps (mega samples per second) in FIG. 1 (a).

Here, the interpolation module 10 performs interpolation to raise the sampling rate to 300 Msps and add further squares.

Then, an unnecessary signal is removed by filtering through the IR filter 20, and a high frequency noise signal is removed through the AA filter 30. The sampling rate is still maintained at 300 Msps.

Then, the decimation module 40 performs decimation to output a d (k) signal of 100 Msps to change the sampling rate to a 2/3 ratio of 150 Msps.

As described above, conventionally, interpolation and decimation are repeated. If the N / M ratio is as simple as 2/3, it can be processed quickly in the FPGA.

However, when the N / M ratio is changed to a complex N / M ratio such as 73/101, the throughput is large and the processing speed is delayed. Accordingly, the processing is not possible in a field-programmable gate array (FPGA), and a method of changing the a (n) signal to an analog signal and re-sampling the signal is used.

Thus, the calculation itself is not possible depending on the sampling rate. For example, in the case of 73-times interpolation, the interpolated signal is a signal of 10.950 Gbps, which makes it impossible to perform real-time operation processing in current FPGA or DSP (digital signal processing).

Further, since it is necessary to change to an analog signal, there arises a problem that the operation degree is complicated and the processing speed is delayed.

An object of the present invention is to provide a sampling rate changing apparatus using a FIFO module.

It is another object of the present invention to provide a sampling rate changing method using a FIFO module.

According to an aspect of the present invention, there is provided an apparatus for changing a sampling rate using an FIFO module, the apparatus comprising: an N image rejection filter for sequentially receiving and sequentially outputting sampled digital signals at a predetermined sampling rate; ; A first-in first-out (FIFO) module for receiving a digital signal output from the N IR filters and sequentially outputting the input digital signal; M anti-aliasing filters for sequentially receiving and outputting the digital signals output from the FIFO module; And a summer for summing and outputting digital signals output from the AA filter.

Here, the digital signal output to the adder may be a digital signal changed to a sampling rate having an N / M ratio with respect to the predetermined sampling rate.

On the other hand, the N / M ratio can be 2/3.

On the other hand, in order to change the N / M ratio, the control module may be further configured to select and activate the N IR filters and the M AA filters, respectively.

The sampling rate changing apparatus may be configured as a field-programmable gate array (FPGA).

According to another aspect of the present invention, there is provided a method of changing a sampling rate using a FIFO module, the method comprising sequentially receiving N digital signals sampled at a predetermined sampling rate by N IR filters, Outputting; A first-in first-out (FIFO) module receiving a digital signal output from the N IR filters and sequentially outputting the input digital signal; M AA filters (anti-aliasing filters) sequentially receive and output the digital signals output from the FIFO module; And summing the digital signals output from the AA filter and outputting the summed signals.

At this time, the digital signal output to the adder may be a digital signal changed to a sampling rate having an N / M ratio with respect to the predetermined sampling rate.

The N / M ratio may be 2/3.

Meanwhile, in order to change the N / M ratio, the control module may be configured to select and activate the N IR filters and the M AA filters, respectively.

According to the above apparatus and method for changing the sampling rate using the FIFO module, the N sampling rate is changed to the N / M ratio by inserting the FIFO module in the middle of the N IR filters and the M AA filters. The sampling rate can be easily and simply changed. Also, the sampling rate can be changed immediately without increasing the sampling rate.

There is no need to change the sampling rate by changing the digital signal back to the analog signal. Even if you want to change the N / M ratio to a complicated one, the FPGA or DSP can be processed in real time.

1 is a block diagram of an apparatus for changing a sampling rate by an interpolation and decimation process according to the related art.
2 is a block diagram of an apparatus for changing a sampling rate using a FIFO module according to an embodiment of the present invention.
3 is a flowchart of a method of changing a sampling rate using a FIFO module according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail to the concrete inventive concept. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an apparatus for changing a sampling rate using a FIFO module according to an embodiment of the present invention.

Referring to FIG. 2, an apparatus for changing a sampling rate using a FIFO module 100 according to an embodiment of the present invention includes an image rejection filter 110, a FIFO A first-in first-out module 120, an anti-aliasing filter 130, a summer 140, and a control module 150.

The sampling rate changing apparatus 100 may use the N IR filters 110, the FIFO module 120, and the M AA filters 130 without interpolating the sampling rate to set the sampling rate of the input digital signal to the N / M ratio . ≪ / RTI >

No matter how large the number of N and M, the sampling rate can be changed very simply as digital signal without changing to analog signal.

In addition, real-time operation can be performed even when FPGA is implemented.

Hereinafter, the detailed configuration will be described.

The IR filter 110 is configured so as to output N digital signals sampled at a predetermined sampling rate, sequentially, in the form of N concatenated connections. Here, the sampling rate of a (n) is illustrated as 150 Msps.

The FIFO module 120 may be configured to receive the digital signals output from the N IR filters 110 connected in parallel and sequentially output the digital signals first.

Next, the AA filter 130 sequentially receives and outputs the digital signals output from the FIFO module 120, and M pieces of the digital signals are connected in parallel.

In this case, the FIFO module 120 is inserted between the IR filter 110 and the AA filter 130 to sequentially input and output a plurality of input / output lines, thereby changing the frequency of the signal, that is, the sampling rate . Therefore, the sampling rate can be easily changed as digital signals.

The summer 140 sums and outputs the digital signals output from the AA filter 130.

Since N is 2 and M is 3, 150 Msps is changed to 100 Msps.

That is, the digital signal output from the summer 140 becomes a digital signal changed to a sampling rate having a N / M ratio with respect to a predetermined sampling rate of a (n).

The control module 150 may be configured to select and activate the N IR filters 110 and the M AA filters 130, respectively, in order to change the N / M ratio.

That is, assuming that N and M are 100, respectively, the control module 150 can freely adjust the change rate by activating 70 IR filters 110 and activating 92 AA filters 130.

Meanwhile, the sampling rate changing apparatus 100 may be configured as a field-programmable gate array (FPGA).

3 is a flowchart of a method of changing a sampling rate using a FIFO module according to an embodiment of the present invention.

Referring to FIG. 3, N IR filters (image rejection filters) 110 sequentially receive digital signals sampled at a predetermined sampling rate and sequentially output them (S101).

Next, the first-in first-out (FIFO) module 120 receives the digital signals output from the N IR filters 110 and sequentially outputs the input digital signals in turn (S102).

Next, M AA filters (anti-aliasing filters) 130 sequentially receive and output the digital signals output from the FIFO module 120 (S103).

Next, the summer 140 adds up the digital signals output from the AA filter 1300 and outputs the sum (S104).

Here, the digital signal outputted to the summer 140 becomes a digital signal changed to a sampling rate having a N / M ratio with respect to a predetermined sampling rate.

And the N / M ratio can be 2/3.

Next, in order to change the N / M ratio, the control module 150 controls to select and activate the N IR filters 110 and the M AA filters 130, respectively (S105).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. There will be.

10: Interpolation module
20: IR filter
30: AA filter
40: Decimation module
110: IR filter
120: FIFO module
130: AA filter
140: Totalizer
150: Control module

Claims (7)

N image rejection filters sequentially receiving digital signals sampled at a predetermined sampling rate and sequentially outputting the digital signals;
A first-in first-out (FIFO) module for receiving a digital signal output from the N IR filters and sequentially outputting the input digital signal;
M anti-aliasing filters for sequentially receiving and outputting the digital signals output from the FIFO module;
And a summer for summing and outputting digital signals output from the AA filter,
The digital signal outputted to the adder
Wherein the sampling rate is a digital signal changed to a sampling rate having an N / M ratio with respect to the predetermined sampling rate. 2. The method of claim 1, wherein the N /
Wherein the sampling rate is 2/3. The method according to claim 1,
Further comprising a control module for controlling the N IR filters and the M AA filters to select and activate the N IR filters and the M AA filters to change the N / M ratio. 2. The apparatus of claim 1,
And a field-programmable gate array (FPGA). Sequentially receiving digital signals sampled at a predetermined sampling rate by N IR filters and sequentially outputting the digital signals;
A first-in first-out (FIFO) module receiving a digital signal output from the N IR filters and sequentially outputting the input digital signal;
M AA filters (anti-aliasing filters) sequentially receive and output the digital signals output from the FIFO module;
Summing the digital signals output from the AA filter and outputting the digital signals;
The digital signal outputted to the adder
Wherein the sampling rate is a digital signal changed to a sampling rate having an N / M ratio with respect to the predetermined sampling rate. 6. The method of claim 5, wherein the N /
2/3 < / RTI > 6. The method of claim 5,
Further comprising the step of controlling the control module to select and activate the N IR filters and the M AA filters, respectively, in order to change the N / M ratio. .

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