RU198255U1 - SILICON STRUCTURE WITH DIELECTRIC INSULATION FOR HIGH VOLTAGE ICs - Google Patents

Abstract

The utility model relates to the design of silicon structures with dielectric insulation for high-voltage microcircuits, namely for microcircuits with a supply voltage of more than 100 V. The technical result of the utility model is to increase the yield of suitable ones by reducing the influence of the variation in the thickness of the pockets on the parameters of high-voltage microcircuits. The specified technical result is achieved by the fact that the known silicon structure with dielectric insulation for high-voltage microcircuits, consisting of a silicon-based substrate, insulated by a dielectric from the substrate of silicon monocrystalline pockets with a hidden layer doped with arsenic, and emerging on the working surface of the structure along the side walls of the pockets, additionally contains a hidden layer at the bottom of the pockets, doped with phosphorus with a dose in the range (2.5-3.5) ⋅10 ions / cm with a depth greater than the depth of arsenic by 4-6 microns. 1 ill.

Description

The proposed utility model relates to the design of silicon structures with dielectric insulation for high-voltage circuits, namely, circuits with a supply voltage of more than 100 V.

Silicon structure with dielectric insulation for high-voltage circuits, consisting of a silicon-based substrate, insulated by a dielectric from a substrate of silicon single-crystal pockets with a hidden layer (see the book "Bipolar Integrated Circuits with Dielectric Isolation", Nikishin VI, Synorov V.F. , Tarasov A.P. Voronezh: Publishing House of Voronezh State University, 1980, p. 13).

To obtain a hidden layer, the surface of the wafer is doped with one of the n-type impurities, namely antimony, phosphorus or arsenic, before forming pockets of a silicon structure with dielectric insulation (KSDI).

When doping with antimony, the hidden layer has a surface resistance of 12-30 Ohm / □, which is not enough for modern transistors operating at high currents. When doping with phosphorus, the resistance of the hidden layer can be obtained up to 3-5 Ohm / □, however, during heat treatment the thickness of the hidden layer increases to 12-15 microns, which requires an increase in the depth of the pockets. When doping with arsenic, the resistance of the hidden layer can be obtained up to 2-4 Ohm / □, and the thickness of the hidden layer up to 4-6 μm. However, during the formation of pockets in monocrystalline silicon with a hidden layer of phosphorus or arsenic, a heavily doped silicon surface is rasterized and, as a result, the exact shape of the pocket topology is lost.

This drawback was eliminated in a silicon structure with dielectric insulation for high-voltage microcircuits, consisting of a silicon-based substrate insulated by a dielectric from a silicon single-crystal pockets substrate with a hidden layer of doped arsenic and extending to the working surface of the structure along the side walls of the pockets (see, for example, the brochure: Reviews on electronic technology. Series 3. Issue No. 4 (1304). Silicon structures with dielectric insulation for microelectronic products. Bryukhno N. A., Zharkovsky E. M., Kontseva Yu.A., Sakharov Yu.G. M .: Central Research Institute "Electronics", 1987, p. 31).

The disadvantage of this structure is that the accuracy of obtaining the thickness of single-crystal pockets is small and is about 6 microns. With a minimum thickness of the pocket, there is a marriage in the breakdown voltage of high-voltage structures formed in the pockets. If you increase the nominal thickness of the pockets for the technological stock, for example, by 6 microns, then with the maximum thickness of the pockets, the voltage drop across the transistors in the open state will increase, which will also reduce the yield.

The technical result of the proposed utility model is to increase yield by reducing the influence of the variation in the thickness of pockets on the parameters of high-voltage microcircuits.

The specified technical result is achieved by the fact that the known silicon structure with dielectric insulation for high-voltage circuits, consisting of a silicon-based substrate, insulated by a dielectric from the substrate of silicon single-crystal pockets with a hidden layer doped with arsenic, and exiting onto the working surface of the structure along the side walls of the pockets, contains a hidden layer at the bottom of the pockets doped with phosphorus in the range (2.5-3.5) ⋅10 ¹³ ions / cm ² and a depth greater than the arsenic depth by 4-6 μm.

At doses lower than 2.5 × 10 ¹³ ions / cm ^{2, the} influence of phosphorus increases the direct voltage drop of the transistors in the open state. At doses greater than 3.5 x 10 ¹³ ions / cm ^{2, a} hidden phosphorus layer reduces the breakdown voltage on transistors when they are closed. Because Since the hidden layer at the bottom of the pockets doped with phosphorus in the range (2.5-3.5) ⋅10 ¹³ ions / cm ² does not affect the etching rate of silicon, the formation of isolated pockets does not cause raster and loss of shape of the pockets. At phosphorus occurrence depths lower than the arsenic depth by 4 μm, the effect of the phosphorus layer on the parameters of high-voltage structures does not affect. Depths of phosphorus, large depths of arsenic at 6 microns, are not advisable, because in this case, it will be necessary to increase the thickness of single-crystal pockets.

Figure 1 shows a section of a complementary transistor formed on the proposed silicon structure with dielectric insulation for high-voltage circuits.

With reference to FIG. 1 marked:

1 - silicon single crystal pocket;

2 - a hidden layer doped with phosphorus;

3 - a hidden layer doped with arsenic and emerging on the working surface of the structure along the side walls of the pocket;

4 - side wall of the pocket;

5 - insulating dielectric (silicon dioxide);

6 - polysilicon substrate;

7- insulating and masking oxide on the working side of the structure;

8 - the base of the bipolar transistor;

9 - emitter of a bipolar transistor;

10 - metallization of a bipolar transistor;

x - the difference in the depths of the hidden layer of phosphorus and arsenic.

The following describes the main steps in the manufacture of a complementary transistor formed on the proposed silicon structure with dielectric insulation for high-voltage circuits.

Ion implantation of phosphorus with an energy of 60 keV and a dose of 3.0 × 10 ¹³ ions / cm ^{2 is} carried out on single-crystal silicon wafers of [100] orientation of n-type conductivity with a resistivity of 10 Ω⋅cm over the entire surface. Then the impurity is heat treated in an atmosphere of oxygen at a temperature of 1200 ° C for 4 hours. Thus, in the proposed structure, in the bottom part of the silicon single-crystal pocket 1, a hidden layer doped with phosphorus 2 is formed with a surface resistance of 200-300 Ohm / □.

In the next step, the plates are oxidized for 15 minutes at a temperature of 1150 ° C in dry oxygen, then 35 minutes in water vapor and 20 minutes again in dry oxygen. In the resulting silicon dioxide film by the method of photolithography, windows are formed through which grooves with a depth of 41-43 microns are etched. After removal of the oxide film, ion implantation of arsenic is carried out with an energy of 60 keV and a dose of 1.8 × 10 ¹⁶ ions / cm ² . Impurities are distilled in an oxygen atmosphere at a temperature of 1220 ° C for 3 hours. As a result, a hidden layer is formed, doped with arsenic 3, which extends to the working surface of the structure along the side walls of the pocket 4 with a surface resistance of not more than 5 Ohm / □. Next, on the obtained silicon wafer relief, a protective film of silicon dioxide 5 is grown by thermal oxidation at 1200 ° С according to the following regime: 60 min in dry oxygen, 270 min in water vapor, and 20 min in dry oxygen. To align the relief and form a support layer on the plates, polycrystalline silicon is deposited, from which the polysilicon substrate 6 is obtained, at a temperature of 1180-1200 ° C to a thickness of at least 380 μm. Then, the polysilicon surface of the plates is ground until a smooth surface is obtained. Silicon single-crystal regions with a hidden layer are isolated by removing the single crystal outside the relief from the back of the wafers.

On the obtained structure of integrated circuits with dielectric isolation of components by local oxidation through a silicon nitride mask, a layer of silicon dioxide with a thickness of 1.3-1.5 μm is formed, which acts as an insulating and masking oxide on the working side of structure 7. Then through windows in ionic oxide By implanting boron and phosphorus, base 8 and emitter 9 regions of the high-voltage bipolar transistor are formed. After all high-temperature treatments, the depth difference between the hidden layer of phosphorus and arsenic x is 4-6 microns.

Before the formation of contact windows, a layer of an interlevel dielectric consisting of pyrolytic oxide 0.25 μm thick and phosphorosilicate glass 0.5-0.7 μm thick is applied to the surface of the plates. In the obtained layer by plasma-chemical etching, contact windows are formed to the regions of high-voltage transistors. Then, aluminum metallization of the bipolar transistor 10 is formed with a thickness of 1.6-1.8 μm.

Table 1 shows the measurement results of bipolar transistors on the same silicon structures with dielectric insulation, differing only in dose and difference in the depths of phosphorus and arsenic x. Depths of phosphorus, large depths of arsenic at 6 microns, are not advisable, because in this case, it will be necessary to increase the thickness of single-crystal pockets.

Thus, it was experimentally confirmed that for an additional layer doped with phosphorus, the optimal dose range is (2.5-3.5) ⋅10 ¹³ ions / cm ² and the depth is greater than the arsenic depth by 4-6 μm (sample 5). Reducing the doping dose increases the direct voltage drop, increasing the dose reduces the breakdown voltage of the bipolar transistor, and the difference in depth x less than 4 microns reduces the technical result of the utility model.

Claims (1)

Silicon structure with dielectric insulation for high-voltage microcircuits, consisting of a silicon-based substrate, insulated by a dielectric from a silicon single-crystal pockets substrate with a hidden layer doped with arsenic and facing the working surface of the structure along the side walls of the pockets, characterized in that the bottom of the pockets additionally contains hidden a layer doped with phosphorus with a dose in the range (2.5-3.5) ⋅10 ¹³ ions / cm ² and a depth greater than the depth of arsenic by 4-6 microns.

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