RU1833868C - Random numbers generator - Google Patents

Abstract

The invention relates to computer technology and is intended to simulate arbitrary distributions according to the normal law. The purpose of the invention is the expansion of functionality by modeling arbitrary empirical distribution laws in accordance with the normal law. The generator contains a uniformly distributed random number sensor, an adder, a subtractor, a multiplier, comparison circuits, registers, a decoder, a block for setting distribution parameters, a synchronizer, keys, switches, blocks of delay elements, OR elements, and a group of elements I. 1 ill., 1 table.

Description

The invention relates to computer technology, serves to simulate arbitrary distributions according to the normal law, and is intended for use in digital devices as a prefix.

The purpose of the invention is to expand the functionality of the device by modeling arbitrary empirical distribution laws in accordance with the normal law.

It is known that a complex-looking histogram cannot always be approximated using a suitable curve that obeys any distribution law. Therefore, it is advisable to replace such a histogram with a weighted sum of normal distribution zabbns, i.e., present it as a dependence

f3aK (x) Ј PI fi (x),

i 1

where Pi is the probability of the distribution fi (x).

Each of the distributions fj (x) is characterized by its mean value mxi and variance Dxi. To break down an arbitrary distribution law into normal components, it is most logical to use a simple graphical method, which consists in the fact that any distribution curve (obtained on the basis of statistical data) can be easily represented as a sequence of isosceles triangles. At the same time, split in such a way that, when the abscissa corresponding to them is added, a curve will be obtained, as close as possible to the real one. The triangular distribution is rather accurately replaced by the normal law with equal dispersion. It is also known that the dispersion of the distribution over the isosceles triangle with base 2a is -, i.e.

ё

00

with

o °

about

00

Dxi

and

6

Gi

After decomposing an arbitrary into normal components, we can write that

th

mxi PI;

Dx

pxi + mxi) Pi - mx;

where mxi and PI are determined from the graph.

"

Moreover, Pi gG a Si is the area of the 1st tray, 2iSl

square (Si hi ai;

where hi, ai is the height and base of the l-th triangle).

Therefore, having the values mxi, Pi, Dxi and using the modeling dependence (1)

x Gx Y5 (V «| -3) + mi;

an arbitrary empirical distribution law can be reduced to normal. For the case when I TGZ, the generator is shown in the drawing.

The generator contains a sensor 1 evenly distributed random numbers, an adder 2, a subtractor 3, a multiplier 4, comparison circuits 5 and 6, registers 7-17, a decoder 18, a synchronizer 19, keys 20-29, switches 30-33, blocks 34- 35 delay elements, delay element 36, elements 37-41 OR, group of elements 42-44 AND, input 45 of the installation to the initial state of the device, input 46 of the installation to the initial state of the synchronizer 19, input 47 of the start of the device, outputs 48-52 of the synchronizer , input 53 start synchronizer 19, information outputs 54 devices, registers 7-15 form a block for setting distribution parameters.

The generator operates as follows.

First, the generator is initialized by applying a signal to input 45. Upon receipt of this signal, the synchronizer 19, registers 7-16, is reset, code 001 is entered into register 17.

After that, the coefficients PI (I 1,2), b, mxi (i - 1-, 3), ai (I 1., 3) are entered into registers 7-15. The chains are shown in FIG. 1 are not shown. It should be noted that the coefficients Pi and P2 are entered. Pi + P2. The generator is ready for operation. By applying a signal to input 47, it starts. The signal, passed through the OR elements 37, starts the sensor 1, which enters the input 53 of the synchronizer 19 and starts it, as well as

sends to the second inputs of the keys 25-28, standing at the inputs of the comparison circuits 5 and b, and the random number a from the information output of the sensor 1, as well as the coefficients Pi and Pr from the registers 7 and 8, are respectively sent to the comparison circuits 5 and 6. The signals from the outputs of the comparison circuits 5 and 6 are fed to the first and second inputs of the decoder 18. At one of its two outputs in accordance with the table

A signal appears that fixes one of the codes in register 17: 001, 010, 100.

Fixation occurs as follows. If conditions 1 are fulfilled (see table), then at the outputs of the decoder 18 the signal

is absent and the code 001 is stored in register 17. It is set when the device is reset to the initial state by the signal at input 45.

If conditions 2 are satisfied, then the signal from the decoder 18 is set to zero the first bit of the register 17 through the elements 41 OR, and the second bit is entered 1, thus, the code 010 is recorded in the register 17.

Similarly, when condition 3 is fulfilled, the code 100 is fixed in the register 17, while the first bit of the register is also set to zero by the signal from the other output of the decoder 18 through the OR element 41.

as a result of fixing the code in the register 17, an interval is determined to which a uniformly distributed random number a refers.

The signal from the output of 48 synchronizer

19 through the OR element 37, the sensor 1 is started and a random number a and the contents of the register 16 (in the first cycle, O) are supplied to the adder 2 through the switches 32 and 33. The sum

Si a + O

is delayed in block 35 delay elements during the translation of the register 16 to zero. By the signal from the output 49 of the synchronizer 19 through the OR element 40, the register 16 is set to O, and by the signal from the output 50, the sum Si from the block 35 of the delay elements is entered via the key 24 into the register 16.

Next, outputs 48, 49, 50 of the synchronizer 19 again reappear in sequence. The device operates in a similar way, as a result of which a sum is generated in register 16

32% + Si and further successively obtained

Зз Sa + 03; 84 Зз + «4; Ss s4 +

+ "In; Se Ss + OD.

After the formation of Se, a signal appears at the output 51 of the synchronizer 19. By

a difference is formed by this subtractor 3

S Se - b

(S and coefficient b (b 3) come through the keys 22 and 23 to the subtractor 3) and also the result of subtraction S and the coefficient ai through the keys 20 and 21 of the elements And go to the multiplier 4. One of the coefficients a is selected by supplying a code the number (i) of the interval stored in the register 17 to the switch 30. The code of the number of the interval is issued through the elements 42-44 AND of the group by the signal from the output 51 of the synchronizer 19 coming through the elements 38 OR to the second inputs of the elements AND 42-44 of the group consisting at the outputs of the register 17,

Result of Multiplication Ss S ai

after a delay in the block 34 delay elements together with the operand fhxi on a signal from the output 52 of the synchronizer 19 is fed to the adder 2 through the switch 33 switching.

One of the mxi is also sampled by supplying the interval number code (I) (by a signal from the output 52 of the synchronizer 19 to the second inputs of the elements 42-44 AND of the group to the switch 31.

Summation Result

x Se + rhxi

through the key 29 And the signal also from the output 52 of the synchronization 19 is issued to the information outputs 54 of the device.

The signal from the output 52 of the synchronizer 19 through the element 40 OR register 16 is set to O.

Upon a signal from the output of delay element 36, through element 39 OR, register 17 is set to state L001,

Upon repeated calls, the operation of the generator is similar and it begins by applying a trigger signal to input 47, since the coefficients in registers 7-15 are stored, and registers 16, 17 and synchronizer 19 are in the initial state.

Thus, the use of the invention allows to expand the functionality of the device by modeling arbitrary distributions according to the normal law.

Claims (1)

The claims A random number generator comprising a sensor of uniformly distributed random numbers, a first register, a subtractor, a sealant, an adder and a first key, characterized in that, in order to expand the functionality by generating numbers with a probability distribution, which are a composition of normal distributions, it contains a block for setting distribution parameters, a second register, four switches, a synchronizer, a decoder, two 5 comparison circuits, the second to tenth keys, a group of AND elements, delay elements, two delay blocks and three OR elements, the first, second and third outputs of the distribution parameter setting unit 0 are connected respectively to the first, second and third information inputs of the first switch, the fourth, fifth and sixth outputs of the distribution parameter setting unit are connected respectively 5 with the first, second and third information inputs of the second switch, the first, second and third control inputs of which are connected to the corresponding control inputs of the first switch and to the outputs of the first, second and third elements AND groups, the first inputs of which are connected to the corresponding bit the outputs of the first register, the discharge inputs of the installation of which are connected to the outputs of the decoder, the first input of which is connected to the output More than the first comparison circuit, the first input of which is connected to the output of the first key cha, the information input of which is connected to 0 by the seventh output of the distribution parameter setting unit, and the control is input to the generator start input and connected to the control inputs of the second, third and fourth keys, the input 5 of the start of the synchronizer and the first ode of the first OR element, the output of which is connected to the prohibiting input of the sensor of uniformly distributed random numbers, the output of which is connected to the first information input of the third switch and information inputs of the third and fourth keys, the outputs of which are connected to the second information inputs, respectively, of the first and second 5 comparison circuits, output More than the second comparison circuit is connected to the second input of the decoder, and the first information input is connected to the output of the second key, the information input of which is connected to the eighth 0 by the output of the distribution parameter setting unit, the first synchronizer output is connected to the second input of the first OR element, the first control inputs of the third and fourth switches, the outputs of which are connected to the information inputs of the adder, the output of which is connected to the input of the first delay unit and the information input of the fifth key , the output of which is the information output of the generator, the second output of the synchronizer is connected to the first input of the second OR element, the output of which is connected to the input of the installation in O second register, the bit outputs of which are connected to the information input of the sixth key and the first information input of the fourth switch, the third output of the synchronizer is connected to the control input of the seventh key, the information input of which is connected to the output of the first delay unit, and the output to the bit inputs of the installation of the second register , the fourth synchronizer output is connected to the first input of the third OR element and the control inputs of the sixth, eighth, ninth and ten keys, the information input of the eighth key is connected is connected with the ninth output of the distribution parameter setting unit, and the output is with the input Turns off the switch, the Reduced input of which is connected to the information output of the sixth key, and the output - with the information input of the ninth key, whose output is connected to the first input of the multiplier, the second input of which is connected with the information input of that key, the information input of which is connected to the output of the first switch, the output of the multiplier is connected to the input of the second delay unit, the output of which is connected to the second information input of the fourth switch, the fifth output of the synchronizer is connected to the second inputs of the second and third OR elements, the control input of the fifth key, the second control inputs of the third and fourth switches and the input of the delay element, the output of which is connected to the preset input of the first register, the output of the second switch is connected to the second information input of the third switch, the output of the third OR element is connected to the second inputs of the elements AND groups.