JPS63132532A - Polynomial dividing circuit for extended galois field - Google Patents

Abstract

PURPOSE:To obtain a polynomial dividing circuit which enables the variation of even the degree of a dividing polynomial by varying the coefficients of the dividing polynomial g(x). CONSTITUTION:When the coefficients g0-ge of the respective terms of the dividing polynomial g(x) are written in registers R0, R1... Re-1, and Re, the coefficients g0-ge of the dividing polynomial g(x) are set in respective multiplying coefficient multipliers KA and dividing coefficient multipliers KV respectively, and the dividing coefficient multipliers KV to which the vectors of the coefficients of a polynomial f(x) to be divided are inputted from an input terminal (a) in the order of higher-degree terms fn-f0 divide the output vector of the multiplication processing unit Ue-1 by the vector of the coefficient of the terminal of the highest order of the polynomial g(x) to be divided set by the register Re and output the results. Consequently, the polynomial dividing circuit is obtained which inables the variation of the coefficients of the dividing polynomial g(x).

Description

[Detailed description of the invention] [Technical field] Extended Galois field GF (2') used in calculations with error correction codes or polynomial calculations for decoding Reed-Solomon codes, used in recording/reproducing devices using optical discs or signal transmission. Regarding the polynomial division circuit above.

[Prior art]

A polynomial division circuit conventionally used for encoding cyclic codes, etc., has a polynomial whose coefficients and variables are all “1”.
Or, it is performed on the Galois field CF (2) of "0", and a conventional polynomial division circuit is shown in FIG.

The division circuit shown in FIG. 10 includes an EOR circuit EX' to which an input signal is applied from one input terminal and a signal from the coefficient multiplier F to the other input terminal, and the output of this EOR circuit is applied for one bit time. It is constructed by cascading unit processing circuits each consisting of a latching delay circuit Re' as many as the degree of the polynomial serving as the divisor, and the other end of the coefficient multiplier is connected to the output of this division circuit. The transfer function is set to 1 or 0 depending on whether the value of each term of the polynomial g (X) serving as the divisor is 1 or 0.

As shown in the figure, by sequentially inputting the divider polynomial f (x) to this division circuit starting from the higher-order terms, the quotient polynomial Q (X) is sequentially output from the output side starting from the higher-order terms, and from each delay circuit. obtains the value of each term of the remainder polynomial R(x), but these polynomials f (x), g(x), Q(x
) and R(X) are all “0” or “1”
” is.

In such conventional polynomial division circuits, division on the extended Galois field CF (2''') was not possible, so the division was processed by a microprocessor. is the exclusive OR of vector patterns, and multiplication and division are performed by adding and subtracting exponents of the exponent representation of the primitive light α, so
Since conversion between vector representation and power representation must be frequently performed, processing by software has the drawback of extremely slow processing speed.

Furthermore, the polynomial division circuit as described above uses the polynomial g (
Since the coefficients of each term in x) are set to 1 or 0, there is a problem in that it lacks versatility.

〔the purpose〕

The present invention enables division on an extended Galois field to be executed by hardware to improve speed and perform stable processing independent of software, and also to make the divisor polynomial variable.

〔composition〕

The configuration of the present invention will be explained based on examples.

Here, the dividend polynomial f (x), the divisor polynomial g (X)
, quotient polynomial 2〇 (x), and remainder polynomial R(x) respectively f(
X)= f, 10 f, x+ f2x" +=-...-
・+f, −, x″−' 10fhx”, −・−・
(1) g(X)=go 10g+x+gm x2
i・＋・＋＋＋・++ ga−+ X＠−' 10g,
z@・・・・・・(2)Q(”)=Qo+
Q t X + q2 X2+ ””・+ql, -
@-, xll-@-' +qh-a X'-@・(
a) R(x) = ro + r, x + r2 x'
+−−−−−=・−+rs−1x@−1・・・・・・
・Assuming (4), the coefficient of each term f o ”” f i+
go −g@ )Q O””qh−@ + r@〜r,
-1 is the number of m bits indicated by α1, and this α is the primitive light of the extended Galois field GF (2m).

Hereinafter, the number of m bits will be referred to as one word.

Note that as an example of the extended Galois field GF (2m), m=
4, that is, the elements of CF (2') are shown in the table below by associating the power expression by α, which is the root of the minimum polynomial 1+x+x', and the vector expression.

The coefficients of each term of the dividend polynomial are elements on the extended Galois field as shown in the table above, and are input to the polynomial division circuit as data words in vector representation.

FIG. 1 is a diagram showing an embodiment of a polynomial division circuit that performs calculations in vector representation and makes the coefficients of the division polynomial variable.
Register Ro, Re...Rm=1 +Re
is written with the coefficients of each term of a divisor polynomial output from a microprocessor (not shown), etc., and the coefficient of the highest order term of the divisor polynomial is held in register R0 and set in a division coefficient unit Kv, which will be described later. Coefficients of terms other than the highest order are stored in register R@-I in order from the coefficient of the term with the highest order.
Each multiplication coefficient unit K, which will be described later, is held in Re and Re, respectively.
Set to A.

Multiplication processing unit) UO~U, -1 is the divisor polynomial g (X)
The number of stages one step less than the number of terms is connected in cascade, and each multiplication processing unit)U. -U, -1 correspond to the input of m bits of vector representation (hereinafter referred to as vector) constituting each coefficient of the input dividend polynomial f (x), during the transmission period of one word of the EOR circuit. m sets of delay latches Re are provided for delaying the corresponding one unit time τ.

Furthermore, these multiplication processing units include a division coefficient unit K, which will be described later.
The coefficient g of the corresponding term of the divisor polynomial g (x) set by the registers Re, Rt...R1-1 is added to the vector of coefficients of the quotient polynomial It is equipped with a multiplication coefficient unit Ka that multiplies vectors, and the vector outputted by this multiplication coefficient unit KA is
The modeniro 2 is supplied to the OR circuit E for each bit of the vector.
Perform the addition of .

In the division coefficient unit, is the multiplication processing unit U, -1
The vector outputted by is divided by the vector of coefficients of the highest order term of the divisor polynomial g (x) set by the register R0, and the result is output.

FIG. 2 is a diagram illustrating the configuration of the multiplication coefficient unit KA and division coefficient unit in more detail. The connected vector-exponent conversion circuit 1 and exponent-vector conversion circuit 2 are connected via an exponent addition circuit 3, and the exponent of the coefficient of the divisor polynomial set from the register Re-Re is added to the exponent addition circuit. A vector inputted to one input terminal of the multiplier 3 and inputted to the multiplication coefficient unit KA is converted into a corresponding exponent by the vector-exponent conversion circuit 1 and inputted to the other side of the exponent addition circuit 3. This exponent addition circuit 3 performs modenilo (2m-1) addition of the two input exponents, outputs the resulting exponent to the exponent-vector conversion circuit 2, and inputs it to the multiplication coefficient unit KA. The vector obtained by multiplying the vector by the coefficient of the divisor polynomial is output from the exponent-vector conversion circuit 2.

The division coefficient unit Kv, as shown in FIG. The result of dividing the input vector by the coefficient of the divisor polynomial is obtained by subtracting the exponent of the coefficient of the divisor polynomial modulo (2m-1) from the exponent of the vector, and converting the resulting exponent to a vector and outputting it. is obtained as a vector.

In FIG. 1, registers Ro, Re...R
e-1 and the coefficient g of each term of the divisor polynomial g(x) in register R0. - When g6 is written, each multiplication coefficient unit has
The coefficient go = g- of the above-mentioned divisor polynomial g (x) is set in the division coefficient unit Kv, and the vector of coefficients of the dividend polynomial f (x) is set from the input terminal a to the higher-order term f0 ~
They are input in the order of f0.

As an initial state, each delay latch Re is reset, so the vector that is first output from the multiplication processing unit U=+, divided by and output to the division coefficient unit is 0, and this “0” is input, multiplication is performed in each multiplication coefficient unit KA, and each bit value inputted to one side of each EOR circuit Ex is "0".Therefore, the vectors sequentially input from input terminal a are multiplied by each multiplication coefficient unit KA. ) Ll, -,
The delay latch has a coefficient f. are latched into each delay latch in that order until the vector is latched.

As mentioned above, f is applied to the delay latch of the multiplication processing unit) U, -. When the vector of f is latched and the vector of f is output from this delay latch in the next operation, the division coefficient unit Kv
is divided by the vector of g, by the quotient polynomial 〇 (X
) is output.

This output q. For example, the vector of -0 is input to the multiplication coefficient unit of the multiplication processing unit U0, and from this multiplication coefficient unit, the vector of the multiplication result of go and Ql'l-@ is input to EOR.
It is output to one input terminal of the OR circuit. Similarly, a vector of the multiplication results of the coefficients of each term of the divisor polynomial and the above-mentioned q, .

At this time, the delay latch of each multiplication processing unit outputs the vector held by each delay latch in the same way as the delay latch of the multiplication processing unit U-1, and the EOR circuit of each subsequent multiplication processing unit outputs the vector held by the delay latch of the multiplication processing unit U-1. A bitwise exclusive OR is performed with the vector output from the multiplication coefficient unit as shown in FIG. 2, and the resulting vector is latched into each delay latch.

That is, through the above single operation, the delay latch of each multiplication processing unit holds the remainder coefficient when the coefficient of the highest order term of the quotient polynomial is calculated, while the remainder coefficient from the division coefficient unit Kv is held in the delay latch of each multiplication processing unit. The coefficient of the highest order term of the quotient polynomial is output as a vector.

Since the orders of the dividend polynomial and the divisor polynomial are known, the order of the quotient polynomial is also known. Therefore, if the above operation is repeated as many times as the number of terms in the quotient polynomial, the coefficients of each term in the quotient polynomial will be output as vectors in order from the highest degree to the division coefficient unit. The coefficients of each term of the remainder polynomial are obtained as a vector in the latch.

FIG. 3 is a diagram showing an embodiment of a polynomial division circuit that performs calculations using exponents of power expression and makes the coefficients of the divisor polynomial variable.

Multiplication processing unit)U. '~Us-1' are connected in cascade, with the number of steps less than the number of terms of the divisor polynomial g(x), as explained above in connection with FIG. an adder E' that adds the exponents modulo (2m-1) of two coefficients, and a register D that delays one unit time T corresponding to the transmission period of one word, and further includes a division coefficient unit K. Model colloid (2m
-1) and outputs the result to the adder E'.

Register RO'rR1'...Re-1'rR@
' is written with the exponent of the coefficient of each term of the divisor polynomial outputted from a microprocessor (not shown), etc., and the exponent of the coefficient of the highest order term of the divisor polynomial is held in the register R% and set in the division coefficient unit Kv'. In addition, the exponents of the coefficients of terms other than the highest order are held in registers R''-1' * R1' I R0' in order from the exponent of the coefficient of the term with the highest order, and are set in each multiplier coefficient unit KA'. Ru.

The above-mentioned division coefficient unit Kv' is the above-mentioned multiplication processing unit U=+
The exponent of the coefficient of the highest order term of the divisor
-1) and output the resulting index.

Further, the input side of this polynomial division circuit is equipped with a vector-exponent converter Cv that converts the input vector into an exponent of the corresponding power expression, and furthermore, the output side of this polynomial division circuit is equipped with a vector-exponent converter Cv that converts the input vector into an exponent of the corresponding power expression. An exponent-vector converter Cs that converts an exponent into a corresponding vector and outputs it, and an output of each register D of each multiplication processing unit and a division coefficient unit Kv
It is provided with a selector S for selectively inputting the output of the index-vector converter C5 to the index-vector converter C5.

FIG. 4 shows the division coefficient unit Kv′ and the multiplication coefficient unit KA.
′ and the configuration of adder E′ in detail.
The division coefficient unit Kv' in a) converts the subtracted value obtained by the subtraction circuit 10, which performs subtraction modulo (2'-1) between the exponent of the exponent of the divided coefficient and the exponent of the exponent of the exponent of the division coefficient, to the exponent of the division result. It is output as an exponent of the expression, and the multiplication coefficient unit KA shown in ω) in the same figure is an adder circuit 2 that performs mode niro (2'-1) addition of the exponent of the power expression of the two coefficients to be multiplied.
The added value obtained by 0 is output as the exponent of the power expression of the multiplication result. Further, the adder E' in FIG. 2C includes an exponent-vector conversion circuit 303. which converts each of the two exponents to be added into m bits of a corresponding vector representation.
302, the exclusive OR of each bit of the vector outputted by these two exponent-vector conversion circuits is outputted from the EOR circuits EXI to Ex, and this outputted m-bit vector is converted to the vector-exponent conversion circuit. 40 to convert it into a corresponding exponent and output it. Note that in order to perform these conversions, a conversion table configured by ROM or wiring logic may be provided.

The polynomial division circuit shown in FIG. 3 is configured such that the vector calculation described in connection with FIG. 1 is performed by exponent calculation in each multiplication processing unit and division coefficient unit.

Therefore, the coefficients fh-1*fR-2, etc. of the terms of the lowest order of the dividend polynomial f(3) are sequentially input as vectors to the vector-exponent converter C7. Then, the exponent corresponding to each vector is output from this vector-exponent converter Cv, and the exponent corresponding to each vector is outputted to the first stage multiplication unit) UO'.
are sequentially input to the first rI! The calculation of the coefficient corresponding to the calculation on the vector performed by the polynomial division circuit of J is
This is performed by performing calculations on the corresponding exponents.

In other words, the exponents of the coefficients of each term of the high polynomial (x) are sequentially output to the selector S in the calculation process, starting with the high-order terms, and after the calculation is completed, the exponents of the coefficients of each term of the remainder polynomial R(x) are output to the selector S in order. An exponent is held in each register D.

Therefore, in the calculation process, the selector S inputs the output of the division coefficient unit K v ' to the exponent-vector converter C3, and after the calculation is completed, the selector S is switched and each register D
The outputs of the index-vector converter C8 are sequentially inputted, and the coefficients of each term of the quotient polynomial Q(X) or the remainder polynomial R(X) are output as vectors from the output terminal of the index-vector converter C3. be done.

FIG. 5 shows the polynomial division circuit explained in connection with FIG. Cv output and each register OS-+~Do
The division coefficient unit Kv includes a selector S' that selectively outputs the output of the adder E' to the adder E', and a demultiplexer DM that selectively outputs the output of the adder E' to the registers D, -1 to D0. The multiplication coefficient unit KA' which adds the exponent of the coefficient of the divisor polynomial to the output of ', has the corresponding registers D, -1 to D0 as the multiplication processing unit selected by the demultiplexer DM. The configuration is such that the exponents of the coefficients of the divisor polynomial are output from the random access memory M and set.

This random access memory M and division coefficient unit Kv'
The exponent of the coefficient of each term of the divisor polynomial output from a microprocessor (not shown) is written in the register Re/ connected to the register Re/, and the coefficients of the terms other than the highest order of the divisor polynomial written in the random access memory As mentioned above, the exponent of Output and set.

In this circuit, for example, the coefficient q of the highest order term of the quotient polynomial Q (X) described in connection with FIG. -8, the exponent of the coefficient f of the highest order term of the dividend polynomial f (x) is output from register D, -3 to the division coefficient unit Kv', and the output from this division coefficient unit Kv' is Multiplying factor KA
'. At this time, the selector S' and the demultiplexer DM conduct the output terminal of the register D, -2 and the input terminal of the register D, -1 via the adder E', and at the same time connect the random access memory M to the multiplier coefficient unit KA'.
The coefficient g of the next term of the highest degree of the division polynomial is outputted from , and the exponent of -1 is output from the division coefficient unit Kv by this multiplication coefficient unit KA'.
Adds the exponent output by ' and the exponent of coefficient g, -9, and outputs this added value and the added value of the exponent output from register D, -2 from adder E' and holds it in register D, -1. do.

If this operation is performed between registers D and -8 to Do toward register Do, the highest order coefficient q of the quotient polynomial. The exponent of −1 is input to the division coefficient unit, and is input from ' to the exponent-vector converter C3 via the selector S'. is output, and the remaining coefficients of the polynomial at that time are held as exponents in the registers D0 to D, -1.

If the above operation is repeated as many times as necessary, and after the calculation is completed, each register D, -1 to D0 is sequentially selected by the selector S' and the contents of the register are supplied to the exponent-vector converter C8, then the quotient polynomial Q (X) and remainder polynomial R
The coefficients of each term in (X) are output as a vector.

6 and 7 have the same functions as the respective polynomial division circuits described with respect to FIGS. 1 and 3,
A polynomial division circuit is shown in which the required number of multiplication processing units is connected in cascade using a switch circuit Sv, and the position at which the dividend polynomial is input can be selected, thereby making it possible to vary the degree of the division polynomial g (x). It is a diagram.

That is, in the polynomial division circuit of the present invention, the multiplication processing units are cascaded in a number that is one less than the number of terms in the divisor polynomial, that is, the degree of the divisor polynomial, and the coefficients of the divisor polynomial are made variable. As described above, a polynomial division circuit for a divisor polynomial of a desired degree can be configured by the switch circuit Sw.

For example, in FIG. 6, when dividing by the following divisor polynomial (t<e), the order t is input to the switch circuit Sv, and the multiplication processing unit U, -.

Input line l from . and the output line 0° to the division coefficient unit Kv, and the input line from the multiplication processing unit Ll-2! , -1 and the multiplication processing unit) output line 0. to U-+. Input lines 1e-t from multiplication processing units) U and -t by sequentially connecting -2, etc. 1 and multiplication processing unit) Output line 0°-2 to LL-t++,
1, and the division polynomial f (x) is inputted from the output line 01-5 of the switch circuit Sw to the multiplication processing unit U, . At this time, the coefficients of the divisor polynomial are set in order from the division coefficient unit Kv to each multiplication coefficient unit KA.

The circuit shown in Fig. 7 is a modification of the circuit shown in Fig. 6 in which division is performed by an exponent, and a vector-exponent converter Cv and an exponent-vector converter C3 are provided on the input side and the output side, respectively. The operation of this circuit does not require any special explanation as can be seen from the explanations regarding FIGS. 6 and 3.

The circuit described in FIG. 5 above performs calculations using exponents, and has one adder and one multiplication coefficient unit to operate in a time-division manner. Alternatively, FIG. 8 shows a polynomial division circuit which is further provided with a function of making the degree of the divisor polynomial g (x) variable as explained in connection with FIG.

In FIG. 8, the first selector SI and the demultiplexer DM synchronize to connect their respective human output lines, and connect adjacent registers 0 corresponding to each multiplication processing unit in FIG. 2 selector S2 and adder E
′ is used to connect sequentially in a time-sharing manner. The first select signal applied to the first selector SI and demultiplexer DM sets the number of registers to be cascaded in a time-division manner, that is, the order of the divisor polynomial, and at the same time, the order of the divisor polynomial is set in advance from the random access memory M. The written coefficients of the divisor polynomial are read out and sent to the multiplier KA'
is output to.

The second selector S2 selectively adds the output of the first selector S to which the second select signal is applied and the exponent of the coefficient of the dividend polynomial output from the vector-exponent converter C7. When the input terminal of the first stage register of the register D connected in cascade in the time-sharing manner is selected by the demultiplexer DM, the exponent of the coefficient of the dividend polynomial is output to the adder E'. In other cases, the first selector SI and adder E' are connected to perform the calculation.

It is clear that by configuring this polynomial division circuit as described above, division can be performed in the same manner as described with reference to FIGS. 5 and 6 above.

In the embodiment described above, the adder E' in the polynomial division circuit for calculating exponents shown in FIGS. 3, 5, 7, and 8 is configured as described in FIG. , two index-vector conversion circuits 30. , 302
and one vector-exponent conversion circuit 40 and m EOs.
Although it is configured by R circuits EXI to EX@, it can be configured by one subtraction circuit 50, one single-only memory 60, and one addition circuit 70 as shown in FIG.

The subtraction circuit 50 calculates the modulo (2m
-1) and outputs the subtracted value to the read-only memory 60, which outputs the Zech function value Z(9)=t for the input value. The output value of this read-only memory 60 and the above-mentioned subtraction circuit 50
Addition circuit 70 modulo (2m
-1), the added value is the CF (2
1) It becomes the exponent of the power expression of the added value by the above addition.

That is, the above Zech function Z (equity) is αz(k)=
It is a function defined by αk + 1. For example, the case where two coefficients α1 and αj are added on GF(2,”) and the exponent p of the added value αp is calculated is explained using the following formula. α2=α1+α”=(αl-J+l)α”=αZ(1-
J) S, °, p=Z(i-j)+j, and the exponent of the added value of the two coefficients is the value of the above Zech function corresponding to the subtracted value of each exponent of the two coefficients, and the value of each of the above exponents. It can be determined by adding the subtraction number to obtain the subtraction value.

Therefore, although the adder shown in FIG. 4(C) requires three conversion tables, the adder shown in FIG. 9 can be realized with only one read-only memory 60, that is, one conversion table.

〔effect〕

According to the present invention, polynomials f (x) and g (X) whose coefficients and variables are numbers on the extended Galois field GF (2''')
, the quotient polynomial Q (X) and the remainder polynomial R (X) can be obtained at high speed by calculating f (X) / g (X), and the coefficients of the divisor polynomial g (x) can be made variable. A division circuit can be obtained.

Further, since the coefficients of the divisor polynomial g (x) are made variable as described above, it is possible to obtain a polynomial division circuit in which the degree of the divisor polynomial is also variable, as shown in the embodiment.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention that performs calculations using vectors, Fig. 2 is a diagram showing an example of a multiplication coefficient unit and a division coefficient unit of a circuit that performs calculations using vectors, and Fig. 3 is a diagram illustrating calculations using exponents. FIG. 4 is a diagram showing a division coefficient unit, multiplication coefficient unit, and adder of a circuit that performs an operation using an exponent, and FIG. Figure 6 is a diagram showing an embodiment of the present invention in which the degree of the divisor polynomial is varied by performing calculations using vectors, and Figure 7 is a diagram showing an example of the present invention in which the degree of the divisor polynomial is varied by performing calculations using exponents. FIG. 8 shows an embodiment of the present invention in which the
The figure shows an embodiment of the present invention in which the order of the divisor polynomial is made variable by performing operations using exponents by time-divisionally selecting registers. FIG. 9 shows another embodiment of an adder for a circuit that performs operations using exponents. FIG. 10 is a diagram showing a conventional division circuit. u and u' are multiplication processing units, Kv I Kv' is a division coefficient unit, R is a register, Cv is a vector-exponent converter, and Cs is an exponent-vector converter.

Claims (6)

[Claims] (1) A set and setting consisting of an exclusive OR circuit (E) and a delay latch (R_a) corresponding to the input of the number of parallel bits of the vector representation of the elements of the extended Galois field where the number of elements is 2^m a plurality of multiplication processing units (U_0, U_1...
・A division coefficient unit (U_e_-_1) which connects U_e_-_1) in a number that is one less than the number of terms of the divisor polynomial in series, and divides the output of the final stage multiplication processing unit by a set coefficient and sequentially outputs the result as a coefficient of the quotient polynomial. K_V), a register (R_e) that outputs the coefficient of the highest order term of the divisor polynomial to this division coefficient unit, and a register (R_e) that outputs the coefficient of each term corresponding to a lower order than the highest order of the division polynomial to each of the above multiplication coefficient units. register (R_0
, R_1, . . . R_e_-_1). (2) A polynomial division circuit on an extended Galois field according to claim 1, wherein the division is performed by switching and selecting the first-stage multiplication processing unit that inputs the coefficients of the polynomial to be divided. (3) A vector-exponent converter (C_v) that receives the input of the number of parallel bits of the vector representation of an extended Galois field element with 2^m elements and outputs the exponent of the exponent representation corresponding to that vector representation. is set to a set consisting of an adder (E') that adds two input exponents modulo (2^m-1) and a register (D), and a coefficient corresponding to the input exponent. a multiplication coefficient unit (K_A'
) and a plurality of multiplication processing units (U0′, U_1
'...U_e_-_1') are connected in cascade by one term less than the number of terms of the divisor polynomial, and the output of the vector-exponent converter is input to the first-stage multiplication processing unit, and the multiplication processing unit of the first stage is a division coefficient unit (K_v′) that outputs the exponent of the coefficient obtained by dividing the coefficient corresponding to the exponent inputted from the register of the processing unit by the coefficient corresponding to the set exponent to each of the above-mentioned multiplication coefficient units; and an exponent-vector converter (C_s) that converts the exponent output from the division coefficient unit into a corresponding vector representation and outputs the coefficient of the highest order term of the divisor polynomial set in the division coefficient unit. and a register (Re') that outputs the exponent of each term of the corresponding term lower than the highest degree of the divisor polynomial set in each multiplication coefficient unit (R_0', R_1', . . . ).
. . R_e_−_1'). (4) Select the output of each register of the multiplication processing unit in a time division manner and input it to one adder (E'), and select the output of this adder to each register of the multiplication processing unit in a time division manner. One multiplication coefficient unit (K_A′) multiplies the coefficient corresponding to the exponent output from the division coefficient unit by the coefficient corresponding to the set exponent, and outputs the exponent obtained to the adder. , an extension according to claim 3, characterized in that polynomial division is performed in time-division processing by outputting exponents written in a readable/writable memory to the multiplication coefficient unit in a time-division manner. Polynomial division circuit on Galois field. (5) The adder calculates the modulo (2^
m-1), a non-volatile memory (60) that outputs the value of the Zech function corresponding to the subtracted value output by this subtractor circuit, and a non-volatile memory (60) that outputs the subtracted value of An addition circuit (
70) A polynomial division circuit on an extended Galois field according to claim 3 or 4, characterized in that the circuit is configured by: (6) A polynomial over an extended Galois field according to claims 3 to 5, characterized in that the division is performed by switching and selecting the first-stage multiplication processing unit that inputs the exponent of the coefficient of the dividend polynomial. Division circuit.