JPS60212034A - Sigma arithmetic circuit of reed solomon coding and decoding system - Google Patents

Abstract

PURPOSE:To obtain coefficients sigma1, sigma2 of an error position polynomial with simple circuit constitution by inputting properly syndromes S0-S3 from a common bus in matching with each operating processing, storing the product sum of the syndromes to a latch section, applying the operation of the coefficients sigma1, sigma2 of the error position polynomial again via the common bus and outputting the result as a vector. CONSTITUTION:Each syndrome is inputted to a vector/exponential converting section 2 from the common bus 1 and multiplication/division of the syndromes is applied by adding/subtracting a power exponent at an MOD operating section 6. The output of the MOD arithmetic section 6 is converted into a vector by at an exponent/vector converting section 11 again, the product sum of the syndromes corresponding to each term of the numerator/denominator of the coefficients sigma1, sigma2 is applied at a vector adder section of the next stage and the result is stored in a product sum latch section 20. The result S1<2>+S0S2, S0S3+S1S2, S2<2>+S1S3 are stored respectively in latch circuits 17, 18, 19, the result is inputted again the vector/exponent converting section 2 and outputted to latch circuits 12, 13 as a vector.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a Reed-Solomon code decoding system capable of two-symbol error correction used in digital audio equipment, and more particularly to a coefficient calculation circuit for an error locator polynomial as one term of the decoding system. Regarding.

In conventional digital audio equipment, when reproducing information from a recording medium, code errors occur for six reasons. Therefore, as a countermeasure against random errors, information is encoded into a code that can be corrected. As an error correction code, BC
H code.

Reed-Solomon codes are well known. The Reed-Solomon code is a type of non-binary BCH code, and is a so-called CI (32, 28) Reed-Solomon code in which an 8-bit element is treated as one symbol in digital audio tape recorders.

A C2 (28, 24) Reed-Solomon code is used.

This shows that the C1 code has a code block length of 32 symbols and four information symbols. C
The same is true for 2 codes. Furthermore, two series of false 9 correction codes, C1 code and C2 code, are combined via interleap.

Reed-Solomon code can be encoded relatively easily using a shift register or the like. However, decoding is complicated. The decoding method known as Peterson's method involves calculating the syndrome, calculating the coefficients of the erroneous position polynomial, and determining the erroneous position.

The calculations are performed in the order of error pattern calculations. The present invention is directed to a circuit for calculating coefficients of an error locator polynomial.

In this invention, Reed-Solomon codes having a two-symbol error correction ability, such as C-codes and C2 codes, are handled. For example, in the C1 code, the code block length is 32, the number of check symbols is 4, the minimum interval is 5 symbols, and error correction of 2 symbols is possible.

The incorrect position polynomial is 1+σ1x10σ, which is a quadratic expression of x2, σ1. σ2 is the syndrome So, St, Ss,
Ss, but this calculation formula is complicated and there has never been a case where it has been achieved completely by hardware means.

DISCLOSURE OF THE INVENTION It is an object of the present invention to correct the coefficients σ1 . The object of the present invention is to provide a circuit that can claim σ snow as syndrome 5o-8s.

(Description of Erroneous Position Polynomial) Before describing the configuration of the present invention, the derivation of the Erroneous Position Polynomial will be explained. In C1 code and C2 code, each symbol is a 1-byte code, and 2'=1 out of 256 elements.
It is one. Since it belongs to a cyclic code, it can be expressed as a vector in polynomial representation. Furthermore, it can be expressed as a power of α of the primitive element, which is the root of the primitive polynomial. In other words, there is a one-to-one correspondence between the vector representation and the exponent. Note that in the present invention, each symbol is not limited to one byte.

Now about the CI(32,28) Reed-Solomon code,
A code block is a set of symbols (Ao, A,...ASS
), the syndromes So to S3 are calculated by the following formula.

In the double error correction code, the minimum code amount distance is 5, and the syndrome is set from So to S3, and the error position is determined by the following polynomial, that is, the error position polynomial σ (phantom).

Let us assume that the two incorrect positions are the n1th and n2th digits, which can be calculated from the 0th digit of Ao on the head, and σ(x) = (1-rnl-"x) (1-γn2-"
x) (2). Here, γ·=α−1. X
Since σ(x)=O with α−nl and α−n2, the erroneous position 311°n2 can be determined by index display.

σ(XI is related to syndrome 5o-8s as follows.

Expanding equation (2) as nl = Vi * rnj = V2, '(x) = (IVIX) (1-VzX
) (3)=1 (Vt+Vg)X+VIV1x”
=1+aIX102x2 On the other hand, polynomial S whose coefficient is the syndrome. (a, JX considering Xl) = So +S1x + SzX” +S
ax” 10-(32, 28) Reed-Solomon code
The coefficients up to X3 are given by syndrome calculation. The coefficients of fourth order or higher are unknown, but for Svez i(・te, V
1=γ. , −1=α”, v2=rn, □1=αn2
Therefore, from equation (1), St = en, Vl + en2V2 hold true. Here, enl l en2 is an error pattern.

Tsuma#)s So=en□+en.

51=enIV1+en2v2 S2=en,Vl +52x2+Sl=e,V, 10en2Vz. Therefore, 5oo(x) is expressed as follows.

””′XJ= (ent 10ng) + (eHIV1
+en, V, )x-)-, so the above equation is simplified. σ(increase) in equation (3) and S.o(X) in equation (4)
Taking the product of σ(x)S, (Xl=en□(1-v2X)+en!
<1-V, ri (53 This equation is a linear equation.

In the following, for a polynomial F(X) in X,
If the sum up to the xj term is expressed as [F(yrJ)i, the sum up to the cubic term of S-(trans) is 5(x) =
Sg+ S1x + S2x' + s, X3=[5o
o(xl).

It is expressed as

5oo(Since the fourth-order or higher-order terms of Xl affect only the fourth-order or higher-order terms in σ(X)S-(transition), [σfX) 5(X) ). = (σ(x)S−(X
) ).

holds true. However, σ(X)S, , (X) is (5)
As shown in equation 5, it is a linear equation, so it must be [σ(xis(Xi) = 0 (6). By the way ~ σ(X)= 1 + ff□x−112x”5(x)=
Since So+S1x +52x2+53x3, σ
(XI S (X) is calculated as σ(x)S(x)=
So+ (S1+a, So) x + (S2+ a□
S1+ a, 5o)X2+(S3+σ1S2+σ2S1
)X3+(σ□S3+σ2S2)X4+σ2σ3x5(
6) From the condition of formula, S2+σISI+σ2So=O,S3
+σIS2+σ2S□=0 is σ(xl=1+σ, X (8) From the same consideration, the following relational expression can be obtained.

S1+(71S,=O, S2+σ1S□=0.S3+σ
l52 = 0 therefore σ1 = s, /Sg -82/S1
=83/32X by substituting (Sl/So)”, we get σ(X
)=0. α-n1 corresponding to incorrect position n1
Since σ<x>=o holds when substituted, S, /S0
is equal to αn1, and the error position n can be immediately obtained from the exponent of S1/So.

Although the present invention provides a circuit that calculates σl and σ2 using equation (7), it is necessary to input the syndrome So-8m and repeatedly perform various calculations. The syndrome So"Sa is given as a vector, but it is difficult to directly multiply and divide them. However, as mentioned above, in a Reed-Solomon code, each symbol is a vector of polynomial representation and a primitive element of the root of a primitive polynomial. Since there is a one-to-one correspondence with the power exponent value, the above multiplication and division can be performed by converting the vector into an exponent and adding and subtracting it using the operation of ]V10D255.In this way, α255=α0=1
Therefore, it becomes a calculation of MOD 255. Also 86~S
Algebraic expressions containing 3, such as Sl" + S, 082, are also vectors and can be expressed as exponents, so σ
! , the numerator/denominator ratio of σ2 can also be calculated by MOD255.

(Structure of the Invention) As described above, the arithmetic circuit of the present invention has a syndrome So+ to Ss, t that is connected to a common path and input as a vector.
t) a vector/exponent conversion unit that converts the sum of products of syndromes into a power exponent value of a primitive element of a Reed-Solomon code; and a 5M0D calculation unit that performs a MOD operation of the sum and difference of two terms of the power exponent values. , an exponent/vector conversion unit that converts the MOD operation value into a vector, a vector addition unit that performs logical summation of the output vectors of the exponent/vector conversion unit, and a vector addition unit that inputs and latches the addition vector, and has a common output side. and a syndrome sum-of-products latch unit connected to the bus, and the syndrome 5o-8s is inputted from the common bus as appropriate in accordance with each calculation process and calculated.
5oSz, 5oSs+ StSg, Ss 10S
After storing σ1. σ2
It is characterized in that it performs the calculation and outputs it as a vector from the exponent/vector conversion section.

(Effects of the invention) -01 of the present invention. The σ2 arithmetic circuit utilizes the correspondence between the vector representation of Reed-Solomon code symbols and the exponent representation to perform necessary operations such as the product or sum of products of the syndrome 5o=Ss using the MO of the corresponding exponent.
By replacing it with D addition, it becomes an extremely simple configuration.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a circuit block diagram, and FIG. 2 is a time chart showing the operation.

In this embodiment, when one byte error is 9, the error position is set to n.
Since the error position ni can be found as σ*=St/so=αn1 if l, a circuit for calculating 51ZSo as a power exponent and immediately outputting nl is added to the circuit of the present invention.

In Figure 1, the common bus 1 is connected to the syndrome calculation circuit 2.
1, 22, 23, and 24 are connected and output the syndromes So, Sl, Sl, and Ss as vectors, respectively. From the common bus 1, each syndrome is transferred to the vector/exponent converter 2 in the time order shown in the operation explanation described later and in FIG.
The next latch circuit 3, EX-NOR circuit 4゜MOD255 adder circuit 5, and MOD operation section 6 add and subtract the exponents to obtain the syndrome. Performs multiplication and division. EX-NO
The R circuit 4 operates as an inversion circuit or a buffer.

The latch circuits 7 and 28 contain 8 bits when there is a 1-byte error.
Latch 1/So. The output of the MOD calculation unit 6 is again sent to the latch circuit 9. It is converted into a vector by an index/vector converter 11 consisting of an index/vector conversion circuit 10, and then converted into a vector by a vector adder 16 consisting of a latch circuit 14 and an EX-OR circuit 15 at the next stage. The sum of products of syndromes corresponding to each term of the numerator and denominator of σ2 is calculated and stored in the syndrome sum of products latch section. Here is the latch circuit 17,
18 and 19 respectively Sx”+5oSx r 5oS
s+5tSz, S2''+5ISll are stored.

Each of the latch circuits 17 to 19 is connected to the common bus IK, and inputs the σ1. Division by σ2 is performed, and the result is output to latch circuits 12 and 13 as a vector. Note that the vector/exponent conversion unit 2. The exponent/vector conversion circuit 10 is a read-only memory in which vectors and exponents are stored in correspondence.

The above circuit operation of FIG. 1 will be explained in detail with reference to the time chart of FIG. 2. The time chart is PiePzy
I will divide the time into . . . and explain the steps for each time. The signals below El in the top row of FIG. 2 represent signals that control the respective temporal operations of the constituent circuits.

Pl: Syndrome performance % Syndrome 81 data of circuit n is inputted to vector/exponent converter 2 via common bus 1. An exponent value to be input to vector/exponent converter 2 is stored in latch circuit 3.

P2: Syndrome 81 data from the syndrome arithmetic circuit 21 is input to the vector/exponent converter 2, the exponent value is inverted by the EX-NOR circuit 4, and the MOD 255 is added to the data stored in the latch circuit 3. Store in. In other words, σ5=s1/So for the −th error is calculated.

P3: 81 data of the syndrome calculation circuit n is subjected to vector/exponent conversion and stored in the latch circuit 3.

P4: Vector/exponential conversion is performed on the SL data of the syndrome calculation circuit n again, and the data of the latch circuit 3 and MOD2 are
55 is added and stored in the latch circuit 9. (Calculation of Sl'') P5: The data in the latch circuit 9 is converted into an index/vector and stored in the latch circuit 14.

P6: The syndrome S0 data of the syndrome arithmetic circuit 21 is subjected to vector/exponential conversion and stored in the latch circuit 3.

P7: The syndrome arithmetic circuit performs vector/exponential conversion on the syndrome S2 data, performs MOD255 arithmetic operation on the data in the latch circuit 3, and latches it in the latch circuit 9. (
5oS2 calculation) P8: Data of latch circuit 9 is indexed/
After vector conversion, the data of latch circuit 14 and EX-O
The R circuit 15 adds the result and stores it in the latch circuit 17. (
Pg: The syndrome S0 data of the syndrome calculation circuit 21 is subjected to vector/exponential conversion and stored in the latch circuit 3.

plO: Syndrome S3 of syndrome arithmetic circuit array
The data is vector/exponential converted, added to the data in the latch circuit 3 by the MOD 255, and stored in the latch circuit 9. (
Calculation of Sodm) Pll: Data in the launch circuit 9 is subjected to index/vector conversion and stored in the latch circuit 14.

PI3: Syndrome S1 of syndrome calculation circuit n
The data is vector/exponential converted and stored in the latch circuit 3.

PI3: Syndrome performance x circuit prisoner syndrome S
2 data is subjected to vector/exponential conversion, added to the data in the latch circuit 3 by the MOD 255, and stored in the latch circuit 9.

(Operation of 8182) P14: The data in the launch circuit 9 is converted into an index/vector, and the data in the latch circuit 14 is EX-ORed and stored in the latch circuit 18. (5oSa + SI S2 calculation) Plsi syndrome calculation circuit syndrome S2
The data is vector/exponential converted and stored in the latch circuit 3.

Pg6: Syndrome S of syndrome calculation circuit
2 data is subjected to vector/exponential conversion, added to the data of latch circuit 3 by MOD255, and stored in latch circuit 9.

(Calculation in S22) PI3: Data in the launch circuit 9 is subjected to index/vector conversion and stored in the latch circuit 14.

PI3: Syndrome S of syndrome performance x circuit z
1 data is subjected to vector/exponential conversion and stored in the latch circuit 3.

P2O: Syndrome S3 of syndrome arithmetic circuit array
The data is vector/exponential converted and added to the data of latch circuit 3 by MOD255 to be latched.

Store in path 9 (operation of 5ISa).

pro: The data in the latch circuit 9 is subjected to index/vector conversion, and the EX-OR with the data in the latch circuit 14 is stored in the shiratch circuit 19 (operation of Ss" + 5tSs).

P21: 5oSa+S stored in latch circuit 18
*Sz data is manually sent to the vector/exponent converter 2 via the common bus 1, converted into an index, and stored in the latch circuit 3.

P22: Sl + S stored in latch circuit 17
ong data is vector/exponentially converted again via the common bus 1, the polarity is inverted, and the data of the latch circuit 3 and M
OD255 is added and stored in the latch circuit 9. (σs
=SoSa +5xSz/Sx”+5oSz calculation)
P23: The data in the latch circuit 9 is converted into an index/vector and stored in the latch circuit 12.

P242 St + S stored in launch circuit 19
The tem data is again subjected to vector/exponential conversion via the common bus 1 and stored in the latch circuit 3.

P25: Ss+SoS stored in launch circuit 17
The z data is vector/exponentially converted again via the common bus l, the polarity is inverted, and the data of the latch circuit 3 and MOD
255 is added and stored in the latch circuit 9 (σ2=S2
"+5IS3/S1"+5oS2 calculation).

P26: Data in the latch circuit 9 is subjected to index/vector conversion and stored in the latch circuit 13.

P27: When the decoder is a Cl decoder, the data in the latch circuit 7 is stored in the latch circuit 8. When the decoder is a C2 decoder, the data in the latch circuit 7 is stored in the latch circuit 8 after the C1 correction operation is completed.

The final R27 step is for transferring data so that the data will not be lost when the C1 code and C2 code are continuously performed in the same circuit.

In the above explanation, the operation seems extremely complicated, but it is actually a combination of MOD addition of power exponents and vector addition, and the calculation is performed for each term by a clock. It can be done in an orderly manner. In addition, MOD255
This is because addition deals with 1 byte of data in this embodiment. If the number of bits of the data to be handled differs, you can change it accordingly.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, with FIG. 1 being a circuit block diagram and FIG. 2 being a time chart. 1...Common bus, 2...Vector/exponential conversion unit, 3
, 7 , 8 , 9.12, 13, 14, 17, 18.
19...Latch circuit, 4...EX-NOR circuit, 5
...11i'LOD255 addition circuit, 6...MOD
Arithmetic unit, 10... Exponent/vector conversion circuit, 11...
・Exponent/vector conversion unit, 15...EX-OR circuit,
16...Vector addition section, addition...Syndrome product-sum latch section, 21-24...Syndrome calculation circuit. Patent Applicant NEC Home Electronics Co., Ltd. Agent Patent Attorney Akihiro Sato LL, IILILL, LL, 1100 yen
-j Ln ■ Sa ω ■■1) Here) 11LILL
luO

Claims (1)

[Claims] When decoding a Reed-Solomon code having a two-symbol error correction capability, coefficients σ1 . σ2 is the syndrome So, S1. In a circuit that operates from St and Ss, a vector/exponent conversion unit connected to a common bus and converting the syndrome 5o-8sp or the sum of products of syndromes manually input as a vector into an exponent value of a primitive element of a Reed-Solomon code. MO that performs MOD calculation of the sum or difference of the power exponent values
a D calculation unit, an exponent/vector conversion unit that converts the MOD calculation value into a vector, a vector addition unit that adds the output vectors of the exponent/vector conversion unit, and inputs and latches the addition vector; It is equipped with a syndrome product-sum latch unit whose output side is connected to a common node ζ, and inputs the syndrome So=Sg from the common node as appropriate in accordance with each calculation process, and calculates the syndrome Sl'' +
5oSz s 508m+ 8182, Sz”+5
After storing the syndrome product sum tSs in the syndrome product sum latch unit, the stored vector is again input to the vector/exponent conversion unit via the common bus to calculate al and σ2, A σ arithmetic circuit using a Reed Solo encoding/decoding system, characterized in that the exponent/vector converter outputs a vector as a vector.