RU1817107C - Device for modelling dynamic processes - Google Patents

Abstract

The invention relates to computer technology and can be used in the design of automated control systems, in debugging software, and, in particular, in modeling the operating time of a system taking into account failures and restoration of operability. An object of the invention is to increase the accuracy of a simulation result. The goal is achieved in that the device for simulating dynamic processes contains the first and second random number sensors 1 and 2, the comparison node 10, the adder 8, accumulating the adder 9, the block of elements 2 AND-OR 11, the group of elements OR 14, from the first sixth delay elements 5, 6, 7.18, 19, 22, first and second blocks of random number sensors 3, 13, decoder 12, element OR 4, pulse distributor 20, maximum selection block 21, multiplier 17, first and second register - Ry 15 and 16. 1 z.p. f-ly, 2 ill. ate with

Description

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The device relates to the field of computer technology and can be used in the design of automated control systems, in debugging software, and, in particular, in simulating the operating time of systems taking into account failures and restoration of operability.

The purpose of the invention is to increase the accuracy of the simulation result by taking into account the possibility of parallel execution of individual sections of the program and the use of various recovery algorithms.

The introduction of these elements and the corresponding relationships allows us to take into account the parallel execution of individual sections of the program and the application of various recovery algorithms in the simulation of dynamic processes.

The first DSP, generating an integer defining a reconstruction algorithm, which is converted by the decoder into a signal that triggers the corresponding DSP, which produces a number proportional to the recovery time. The pulse distributor, the second block of the frequency converter and the maximum selection block are used to sequentially generate a number proportional to the execution time of parallel processes and select the maximum of them. The multiplier is used to obtain a more accurate recovery time by taking into account the complexity of the process being performed.

The device diagram is shown in Fig. 1. The device contains random number sensors 1, 2, a random number sensors block 3, an OR element 4, delay elements 5, 7, an adder 8, an accumulating adder 9, a comparison unit 10, a block of elements 2I-ILI 11 , decoder 12, block of random number sensors 13, block of OR elements 14, registers 15, 16, multiplier 17, delay elements 18.19, pulse distributor 20, maximum selection block 21, delay element 22.

In FIG. Figure 2 shows an example of a block for selecting a maximum of two numbers, which contains registers 23.24, a comparison node 25, a 2-OR-26 element node, register 27.

The device operates as follows. Two random numbers tM and tce are generated by the sensors: the first determines the execution time of the longest program process, and the second determines the time before the computer malfunctions. It is believed that in the event that a failure occurred before the program execution completed, after a period of time tv | necessary for recovery, program execution resumes. The simulation ends if tM is less than tce, i.e. at the next implementation, there were no failures during the execution of the program. The result of the simulation is a number proportional to the execution time of the program, which is calculated by the formula:

n-1

tflbm 2 (C6 | + tB |) + 1mp. I 0

0

0

5

5

0

where V i 0, n-1; tc6: tM: tC6

5

.

Calculation of 1sp is carried out as follows. At the moment the signal arrives at the input of the device, the accumulating adder 9 is reset and the signal through the element И И 4 is supplied to the ДСЧ 2, which generates a number corresponding to tC6.

At the same time, the signal from the OR element 4 is fed to the input of the pulse distributor 20, which starts sequentially the 5 frequency dividers in the frequency converter block 3, which generate IM numbers;,; proportional to the execution time of each of the parallel processes. Then, in the maximum selection block 21, tM | ,

, m

corresponding to the time of the longest process. When a signal arrives from delay element 6, tMi and -tcei are compared. From the output of comparator 10 at tMi tc6i. those. there was a failure, a signal is sent to the MAS 1 to generate a number corresponding to time t. In DRC 1, a number is generated corresponding to the reconstruction algorithm. It goes to

Q is a decoder 12. which starts the corresponding DSP from the DSP block 13. The DSP produces a number proportional to the recovery time tei. which through the block of OR elements 14 enters the input D of the register 15 at the time of the signal from the delay element 19 to the input C. At the same time, when the signal from the delay element 19 arrives at the input C of the register 16, the signal from the maximum selection block 21 to its input D. In the multiplication block 17, tmt and tei are multiplied, and the result on the adder 8 is added to tcei. The amount goes to the block of elements 2I-OR. At the moment of arrival of the signal from the delay element 7, the sum (tC6i + tei) is issued from it to the accumulating adder 9, where formir -1 is 2 (tcei + tui) - after the node is triggered

comparing the process described above by

echoed until tMi tC6i. At tni tc6i 0 p) the signal from the maximum selection block is sent to the block of 2-OR elements and at the time of arrival of the signal from the comparison node 10, tni is output to the accumulating adder 9, where the forp -1 is generated by Г (tC6i + тВ |) + 1mp which

steps to the first information outputs of the device. In this case, the signal from the comparison unit 10 also enters the second control output of the device and

; P - 1

sum 2 (sat | + tB |) + tMn. removed from the per-

i o

new information output of the device at the end of transients on the accumulating adder 9,

Technical implementation. The pulse input signal is supplied to the second input (Ust, О) of the accumulating adder 9 and to the second input of the OR element 4. The pulse signal from the output of the OR element 4 is fed to the input of the frequency converter 2, delay elements 6, 19, and the pulse distributor 20. By pulse the binary signal tcfv is removed from the potential outputs of the signal from the potential output 2 of the signal. At the same time, the pulse distributor 20 is triggered by the pulse signal, and each of the differential signals from the frequency converter 3 is sequentially triggered by the pulse signals from the potential outputs of which the signals are fed to the information inputs of the maximum selection block 21 at the time of the signal from the delay element 22 to its control input. From the potential output of the maximum selection block 21, the signal enters the third input of the block of 2-OR elements, the information input D of register 16 and the second input of the comparison unit. According to the pulse signal from the delay element 6, which is supplied to the third input of the comparison node 10, pulse signals are generated at the first and second output of the comparison node 10. If a single pulse signal is generated at the first output of the comparison node, it is supplied to the delay element 18 and the frequency converter 1. from the output of which a potential signal is received, which is input to the decoder 12. A potential signal is taken from the decoder 12, on the leading edge of which the corresponding DSP is triggered in the DSP block 13, and the potential signal from it through the And block AND 14 is supplied to the data input D of register 15. Writing information on registers 15,16 occurs when the pulse signals .On receipt of their clock inputs C from the elements

0

5

Q

g

0

delays 18 and 19, respectively. The potential signals from the outputs of the registers 15, 16 are fed to the multiplier 17. The potential signal IB is fed to the first input of the adder 8, the second input of which receives the potential signal tC6. From the output of adder 8, a signal corresponding to the sum of tC6 + tee is output to the first potential input of the block of 2-OR elements. The pulse signal from the first output of the comparison unit, delayed by the delay element 7, is fed to the second pulse input of the block of 2-OR elements. By this signal, a binary code gsb + Tween the first information input of the accumulating adder 9 is output from its potential output. The pulse signal from the pulse output of the comparison unit 10, delayed by the delay element 5, is output to the first input of the OR element 4, and the above process is repeated until until a single pulse signal appears at the second pulse input of the comparison unit.

From the potential output of the maximum selection block, the binary code tM is supplied to the third potential input of the block of 2-OR elements and, by the pulse signal from the second output of the comparison node, which is fed to the fourth pulse input of the block of 2-OR elements, is output to the first potential input of the accumulating adder 9.

The pulse signal from the second input of the comparison unit 10 is supplied to the second output of the device. After the end of the transient processes on the accumulating adder 9, the signals from its output go to the first potential output of the device.

The proposed device can be used to design complex systems, in particular, the study of the reliability of the complexes of control algorithms and programs, taking into account equipment failures and restorations. As a result of using the proposed device, a more accurate estimate of the program execution time can be achieved.

Claims (1)

1. A device for simulating dynamic processes, containing the first and second random number sensors, a comparison unit, the first to third delay elements, an adder accumulating an adder, a block of 2-OR elements and a group of OR elements, characterized in that, for the purpose of modeling accuracy , it contains the fourth, fifth and sixth delay elements, the first and second blocks of random number sensors, a decoder, an OR element, a pulse distributor, a maximum selection unit, a multiplier and first and second registers, while the trigger input is The device is connected to the first input of the OR element and to the installation input in О of the accumulating adder, the information outputs of which are connected respectively to the outputs of the simulation result of the device, the output of the OR element is connected to the input of the first random number sensor, to the synchronization input of the pulse distributor, and to the inputs of the first, the second and third delay elements, the outputs of which are connected respectively to the synchronization inputs of the comparison node, the first register and the maximum selection block, the outputs of which are connected to the input the first group of the block of AND-OR elements, to the information inputs of the first group of the comparison node and to the information inputs of the first register, the outputs of which are connected to the information inputs of the first group of the multiplier, the information outputs of which are connected to the information inputs of the first group of the adder, the information outputs of which are connected to the inputs of the second group of the block of elements AND-OR, the outputs of which are connected respectively to the information inputs of the accumulating adder, the output of the Less node comparison is connected to the first input to the block of 2I-OR elements and to the output of the sign of readiness of the result of the device, the output is equal to more than the comparison node is connected to the inputs of the fourth, fifth and sixth delay elements and to the input of the second random number sensor, the outputs of which are connected to the inputs of the decoder, the outputs of which are connected respectively to the inputs of the first block of random number sensors, the outputs of the groups of which are connected respectively to the inputs of the elements OR groups, the outputs of which are connected respectively to the information inputs of the second register, the outputs of which are connected respectively to the information inputs of the second group of the multiplier, the outputs of the first random number sensor are connected to the information inputs of the second group of the comparison node and the information inputs of the second group of the adder, the outputs of the fourth, fifth and sixth delay elements are connected respectively to the second input of the block of elements 2I- OR, to the second input of the OR element and to the synchronization input of the second register, the outputs of the pulse distributor are connected respectively to the inputs of the second block of sensors of the case numbers, the outputs of the first and second groups of which are connected respectively to the information inputs of the first and second groups of the maximum selection block. 2, The device according to claim 1, characterized in that the maximum selection block contains three registers, a comparison node and a 2-OR element node, while in the maximum selection block, the information inputs of the first and second groups of the block are connected respectively to the information inputs of the first and of the second register, the outputs of the first register are connected to the inputs of the first group of the node of the 2 AND-OR elements and to the information inputs of the first group of the node of comparison, the first output of which is connected to the first input of the node of the 2 AND-OR elements, the outputs of which are connected respectively to and the information inputs of the third register, the outputs of which are connected respectively to the outputs of the block, the outputs of the second register are connected to the inputs of the second group of the node of the II-OR element and to the information inputs of the second group of the node of the comparison, the second output of which is connected to the second input of the node of the II-OR elements, the block synchronization input is connected to the synchronization inputs of the first, second and third registers and the comparison node.