RU1798743C - Device for functional control of large scale circuits - Google Patents

Description

The invention relates to measurement technology, in particular to measuring equipment for semiconductor devices, with a high degree of integration, and is intended for use in automatic control systems for the dynamic functioning of large integrated circuits (LSI) with up to 256 conclusions and classification of their results / control into groups. ..: ..

The aim of the invention is to eliminate the noted drawback, namely, increasing the performance of the device for functional control of LSI by increasing the efficiency of using hardware according to the group principle, which consists in distributing the measurement resources of N channels in l groups of m channels in each group and simultaneously controlling time parameters in each group for each controlled output of the circuit.

In FIG. 1 shows a functional diagram of a device for functional control of LSIs using one group of terminals, combining m channels of influence-measurement; Figures 2-4 are examples of specific embodiments of the individual nodes and blocks of the device; figure 5 - timing diagrams illustrating the operation of the device ..

The device contains blocks 1-1 ... 1 t of analog comparators, shapers 2-1 ... 2 t pulses, 3 signal distributor, blocks 4-1 ... 4 t delay, blocks 5-1 ... 5-PP switching, D-flip-flops 6-1 ... 6-t, 7-1. „7-t, 8-1, .. 8-t, memory block 9, test block 10, synchronization block 11 , contact block 12, computing unit 13, and output bus 14. Blocks 1-1., .1 of analog comparators consist of analog comparators 15-1 ... 15 of the upper level and analog comparators 16-1 ,. lower level, and the computing unit 13 - from block 17 matching

and computer 18; :. , ..:. .

The inputs of blocks 1-1..L-m of analog comparators formed by the first combined inputs of the comparators 15-1 ... 15-t, 16-1 ... 16-t of the upper and lower levels, respectively, and the outputs of the shapers 2- 1 .., 2 t pulses connected to. contact block 12.

. The outputs of the comparators 15-1. “15-top, its level is separately connected to the inputs of the first group of inputs of the distributor 3 signals, and the outputs of the comparators 16-1 ... 16- m lower at exactly the inputs of the second group of inputs of the distributor 3, outputs of the first and second groups of outputs of which

Separately connect the first and second inputs of blocks 4-1 ... 4-t delay. The first inputs of the shapers 2-1 ... 2-t are separately connected with the outputs of the first group of outputs of the TO unit of test sequences, and the second inputs are with the outputs of the second group of outputs of the block 10, the outputs of the third group of outputs of which are separately connected with the information inputs of triggers 6-1 ... 6-t, and the outputs of the fourth group of outputs - with information inputs of triggers 7-1 ... 7-t, Synchronizing inputs of triggers 6-1 .., 6-t, 7-1 ... 7-t combined and connected to the first output of the block

And synchronization. The outputs of triggers 6-1 ... 6-t are separately connected to the first inputs of the corresponding blocks 5-1 ... 5-t switching, and the outputs of the triggers 7-1 ... 7-t are with the second inputs of the corresponding blocks 5-1 ... 5 tons of switching, the third and fourth inputs of which are separately connected to the first and second outputs of the corresponding blocks 4-1 ... 4-t delay. The outputs of the 5-1 ... 5-t switching units are separately connected to the information inputs of the 8-1 ... 8-t triggers, the synchronizing inputs of which are separately connected to the outputs of the second group of outputs of the synchronization unit 11, and the outputs are connected to the output bus 14.

The group of third inputs of the signal distributor 3 is connected to the group of first outputs of the memory unit 9, the group of second outputs of which is connected to the groups of third inputs of the delay 4-1 ... 4-t blocks, and the inputs to

the outputs of the computing unit 13 connected to the interconnected unit

10 test sequences and block

11 synchronization.

Blocks 1-1. “1-t analog comparators are designed to compare the signals coming from the controlled LSI located in the contact block 12, with the reference voltages of the upper and lower levels (levels 1 and O, respectively), supplied to the second inputs of the analog comparators 15-1., .15-t, 16- 1 ... 16-t FROM programmable sources Don 1-1 ... Uon1-m, Uon2-1 ... U0n2-m reference voltages. Analog comparators are made on operational amplifiers x (597CA1 microcircuit).

Shapers 2-1 ... 2-t pulses are used to generate pulse signals with output voltage levels,

corresponding to given reference voltage levels Un-i.,. UH-m, UB-i .... ye-m. These signals are signals of actions, which are set via the contact block 12 to the terminals of the controlled LSI. Formovagels of 2-1 ... 2 t pulses are implemented by

Three state type driver circuitry (driver).

The signal distributor 3 is intended for pairwise connection and transmission of signals from the outputs of any of the blocks .1-1 ... 1-t analog comparators to the inputs of any blocks 4-1, ..4-t delays depending on the control signals coming from a memory unit 9 to the group of inputs of the signal distributor 3.

Figure 2 shows a functional diagram of a signal distributor 3 for a group of four channels (), made on four dual multiplexers 19 ... 22. K1500KP171 microcircuits are used as dual multiplexers.

Blocks 4-1 ... 4-t delays are designed to equalize in time the signals in the channels of the measurement effect of each of the n groups coming from the outputs of blocks 1-1 ... 1-t analog comparators through the distributor of 3 signals and transmitting calibrated signals to the inputs of the corresponding blocks 5-1 ... 5-t switching. Each of the 4-1 ... 4-t delay units consists of two independent delay lines controlled by signals from the memory unit 9. A functional block diagram of the delay unit is shown in FIG. Each of the delay units is implemented on buffer elements 23 ... 28, multiplexers 29, 30, delay elements 31 ... 34 with mode-based security means - resistors connected to constant voltage sources - 4.5 V, and multiplexers 35, 36. The buffer elements 23 ... 25 are connected in series and are made on K1500LM122 microcircuits used as delay elements, the delay of each element being 0.7-1.0 ns. The input of the element 23 and the outputs of the elements 23 ... 25 are connected to the data inputs of the multiplexer 29 (chip K1500KP171), the output of which is connected to the combined inputs of the delay elements 31, 32 with a resolution of 0.4 n provided by the selection of the corresponding loads - resistors connected to the sources constant voltage. The outputs of the delay elements 31, 32 are connected to the data inputs of the multiplexer 35, made on the chip K1500KP171. The listed nodes form the first independent block delay line. The second delay line is formed by similar connections of the buffer elements 26 ... 28, the multiplexer 30, the delay elements 33, 34 and the multiplexer 36. The element base of the second delay line is also similar to the first (1500 series chips). The control inputs of the multiplexers 29, 30, 35, 36 are separately connected to the outputs of the memory unit 9 and are used to set the corresponding signal delay codes with a resolution of 0.4 non in the range from 0 to 3.5 non.

Blocks 5-1 ... 5-t switching are designed to transmit signals coming from the outputs of the corresponding blocks 4-1 ... 4-t delay, depending on the control signals coming from D-flip-flops 6-1. ..6-t, 7-1 ... 7-t to the control inputs of blocks 5-1 ... 5-t, to the inputs of the corresponding D-triggers 8-1 ... 8-t. Figure 4 shows a functional diagram of one of

5 switching blocks. Each of the blocks 5-1 ... 5-t switching is implemented on the elements OR 37 ... 40, and the input element OR .37 is the first control input of the switching, the first inputs of the three-input

0 OR elements 38, 39 form information inputs, and the second combined inputs of OR elements 38, 39 form the second control input of the switching unit. Direct and inverse outputs of an element OR

5 37 are separately connected to the third inputs of the OR elements 38, 39, respectively, the outputs of which are separately connected to the inputs of the two-input element OR 40, the output of which forms the output of the switching unit. As an element base for the implementation of the switching unit, K1500LM101 microcircuits were used.

Triggers 6-1 ... 6-t, 7-1 ... 7-t are designed for temporary storage of the reference

5 information of masking signals, respectively, and transmitting these signals to the corresponding block 5-1 ... 5-t switching of each of the m channels of influence-measurement. Triggers 8-1 ... 8-t are used to generate output information about the results of the control for each output of the studied group of m conclusions of the controlled LSI. Triggers 6-1 ... 6-t, 7-1 ... 7-t, 8-1 ... 8-t are made on K1500TM131 microcircuits.

5 The memory unit 9 is designed to store address information for the distributor of 3 signals about pairwise connecting the outputs of blocks 1-1 ... 1 of analog comparators to the inputs of the corresponding lines

0 block delays 4-1 ... 4 t delays, as well as

for storing codes of all delay lines

with various switching combinations

 signals of analog switches. Block 9

memory implemented on chips

5 K1500RU073.

Block 10 of test sequences is designed to generate input actions for controlled LSI from signals coming from the outputs of block 11 of synchronization — clock pulses and phase signals, from which control sequences are formed that are fed to the inputs of 2-1 ... 24-t pulse shapers, settings the latter in the third state, the formation of reference information signals and masking signals received through D-triggers 6-1 ... 6-t, 7-1 ... 7-GL to the inputs of the corresponding blocks 5-1 ... 5- t switching. At the beginning of block 10 test sequences, a well-known technical solution was used.

The synchronization unit 11 is designed to generate pulses with programmable time parameters: period, delays and durations, providing clocking and construction of a time diagram of the device operation when monitoring dynamic LSI parameters. As the synchronization unit 11, a known synchronization generator circuit,.

Contact block 12 is used to connect the terminals of the controlled LSI (in our case, m conclusions to m inputs of blocks 1-1 ... 1 t of analog comparators and m outputs of shapers 2-1 ... 2 t pulses). As the contact block 12, a standard connecting device of the UK type is used.

Computing unit 13 is intended for long-term storage of information - a monitoring program in computer memory 18, for transmitting this information through matching unit 17 to test sequence unit 10, synchronization unit 11, and memory unit 9. As the computing unit 13, the computing complex Electronics IMSOY2 was used. An output bus 14 is used to connect information recording and storage means (not shown in the drawing).

The operation of the device for monitoring the LSI for a group of conclusions is as follows.

A monitored BI C is placed in the contact block 12. Before starting work from the computing block 13, information is recorded in the memory block 9, the test sequence block 10 and the synchronization block 11, and the reference voltage levels U0ni, Uon2 of blocks 1-1 are set. ..1-m analog comparators and logic signal levels of the shakers 2-1 ... 2-t pulses, triggers 8-1 ... 8-t are set to the initial state by supplying a signal from the computing unit to the collection inputs (in the drawing not shown). Information is recorded in the memory unit 9 from the computing unit 13

connecting the output of blocks 1-1 ... 1 t of analog comparators through a 3-signal distributor to the inputs of the adjustable delay lines of blocks 4-1 ... 4-m delays, as well as

delay codes for each 4-1 ... 4-t delay block. Moreover, if all m channels of influence-measurement are involved in the group, then each of the blocks 1-1 ... 1 t of analog comparators is connected via a signal distributor 3 and the corresponding delay lines of blocks 4-1 ... 4-t delay - Corresponding blocks of 5-1 ... 5-t switching. If one or more channels in a group remain free,

then the blocks of analog comparators of the working channels can be connected through the signal distributor 3 to the delay blocks and switching blocks of unused channels of influence-measurement. Wherein

the reference information and masking signals for these channels are recorded the same as in the working channel, and the strobe delay in these channels is set in accordance with the groups

classification.

To illustrate the above, we give the following example.

Suppose that in a group consisting, for example, of four channels of influence-measurement, the third and fourth channels are not involved in the control process. Through the signal distributor 3, the blocks 4-3 and 4-4 of the delay of idle channels are connected to the block 1-1 of the analog comparators of the first channel of influence-measurement. At the same time, the delay of the strobe pulses g3 is set in the first channel, which corresponds to the first classification group, in the third channel - g32,

which corresponds to the second group of classification, and in the fourth channel - G3z. which corresponds to the third group of classification.

In block 10 of test sequences is written control program

LSI (input actions for shapers of 2-1 ... 2-t pulses, reference information received in 6-1 ... 6-t triggers, and masking signals received in 7-1 ... 7-gp triggers) . Information on the temporal parameters of the generated pulses (period, delay, and duration values) arriving at the synchronizing inputs of 6-1 ... 6-t triggers is entered into synchronization unit 1. 7-1 ... 7t, .8-1 ... 8-t and in block 10 test sequences.

Then the device is started (the Start button is not shown in the drawing). In this case, the synchronization unit 11 generates

clock pulses entering the block 10 test sequences. According to these clock pulses, information from block 10 of test sequences is fed to the inputs of shapers 2-1 ... 2 t pulses, and control signals are supplied to the first inputs of the shapers and control signals of the third state are supplied to the second inputs. Formers 2-1 ... 2 t pulses from signals from block 10 of the test sequences generate pulses with levels of UH. UBs that are fed to the inputs of a controlled LSI. Information taken from its outputs enters the blocks 1-1 ... 1 of analog comparators, is compared with the reference voltages Uoni, Uon2. On figa shows the output signal of the controlled LSI. When the reference voltage signal 00n1 is exceeded, the analog comparators 15-1 ... 15-hp of the upper level generate signals of the logic zero (O) level at their outputs, and when the reference voltage signal U0n2 is exceeded, the analog comparators 16-1 ... 16- The lower level generates logic level signals of the logical unit (1). The output signals of the analog comparators of the upper and lower levels of one of the channels of influence-measurement, for example the first channel, are presented in Fig. 56, respectively. The information inputs of triggers 6-1 ... bt receive reference information generated by block 10 of test sequences (Fig.2d), and the information inputs of triggers 7-1 ... 7-ts of outputs of block 10 receive masking signals (Fig.5d). On the leading edge of the clock pulses generated by the synchronization unit 11 with a period To (Fig.5e) and supplied to the synchronizing inputs of the triggers 6-1.,. 6-gp, 7-1 ... 7t. in the latter, overhead information is recorded — reference and masking signals, respectively. The signals at the outputs of the triggers 6-1, .. 7-1 of the first channel are presented in Fig. The signals from the outputs of the comparators 1.5-1, 16-1 of the upper and lower levels of the first channel through the distributor 3 signals are fed to the inputs of the delay line of blocks 4-1, 4-3, 4-4 of the delay of the first, third and fourth channels. Moreover, in accordance with the codes obtained from the memory unit 9 for this combination of switching in the channels, the delayed signals from the outputs of the delay units 4-1, 4-3, 4-4 are supplied to the inputs of the corresponding blocks 5-1, 5-3, 5-4 switching. In Fig. Bq, l shows the signals at the outputs of the delay lines of blocks 4-1, 4-3, 4-4 delay. The signals at the outputs of blocks 5-1, 53. 5-4 switching are identical, since the reference information and the masking signals in the indicated channels are the same. The shape of these signals is shown in Fig. 5m. From the outputs of switching blocks 5-1, 5-3, 5-4, the delayed signals are fed to the information inputs of the corresponding triggers 8-1, 8-3, 8: 4, to the synchronizing inputs of which strobe pulses from the outputs of the 1G synchronization block are supplied, the position of the strobe pulses (delay relative to clock pulses) is determined by classification groups. In this example of implementation, the delay time of the strobe pulse relative to the clock pulses in the first channel is r3i (Fig. 5n). in the third channel Tz2 (Fig.5p), and in the fourth - the TEZ (Fig.5p).

Information is recorded on the leading edge of the strobe pulses in triggers 8-1.8-3, 8-4, at the outputs of which the signals shown in Figs. 5c, t, y, respectively, are set. These signals carry information about the affiliation of the controlled LSI to a particular classification group. If, for example, during monitoring in the trigger 8-1 of the first channel and in trigger 8-4 of the fourth channel, 1 is fixed, this means that the monitored LSI belongs to the Nth classification group. Through the output bus 14, this information enters the means of recording, storing and processing information (not shown in FIG.).

Thus, in one run, for each controlled output, several measurements are made to determine the classification group of the LSI being tested, which results in a reduction in the monitoring time, i.e., an increase in the productivity of the device. In addition, the device has advanced diagnostic capabilities, expressed in the fact that it allows you to quickly localize the fault in each channel by ensuring that the output of any analog comparator is connected to the delay lines of any channel

exposure to measurements in the appropriate group.

8 case of a failure in the channel, in the presence of free (unused during the monitoring) channels

Under the influence of measurement, the faulty channel is automatically turned off and the free channel is connected, which helps to increase the reliability of the device, increase the efficiency of use of hardware and increase the utilization rate of its nodes.

The technical advantage of the proposed device for functional LSI control over the prototype lies in the possibility of distributing the measurement resources of N channels into n groups of no m channels s in each group and simultaneously monitoring the time parameters in each group for each monitored output.

Socially beneficial advantages derived from the technical are to increase the productivity of the device, increase the efficiency of use of hardware and expand the diagnostic capabilities of the device.

The proposed device for functional control of the LSI is planned to be used in the complex of control of static parameters and dynamic functioning of super-large integrated circuits with the number of outputs up to 256 and the operating frequency up to 50 MHz.

Claims (1)

The claims A device for the functional control of large integrated circuits, containing N channels of influence-measurement according to the number of outputs of the controlled circuit, each of which consists of a block of analog comparators, a pulse shaper, a delay unit, a switching unit and three triggers, a test sequence block common to all channels, a block synchronization, computing unit, contact block and output bus, and the input of the block of analog comparators and the output of the pulse shaper of each of the N channels of influence-measurement with dineny with the contact block, the first and second inputs of each of the pulse generators separately connected to outputs of the first and second groups of outputs b.loka test sequences, and outputs a third the fourth group of outputs of which are separately connected to the information inputs of the first and second triggers of each channel, the synchronizing inputs of which are connected to the first output of the synchronization unit, and the outputs are connected to the first and second inputs of the switching unit, the output of which is connected to the information input of the third trigger connected with its output with the output bus, the test sequence unit and the synchronization unit are interconnected with a computing unit, characterized in that, in order to increase the productivity-operation of the device by increasing the efficiency of using hardware according to the group principle, which consists in in the distribution of resources for measuring N channels in n groups of t channels in each group and simultaneous control of time parameters in each group for each controlled output of the circuit, p signal distributors and m memory blocks by the number are entered into the device groups, each of which contains m channels of influence -measurement, while the inputs of the first and second groups of inputs of the signal distributor in each group are separately connected to the corresponding outputs of m blocks of analog comparators, a group of third inputs with a group of first outputs of the corresponding memory block, outputs of the first and second groups of outputs of the signal distributor separately connected to the corresponding inputs of m delay units / the first and second outputs of each of which are separately connected to the third and fourth inputs of the corresponding switching unit, a group of third inputs - with a group of second outputs of the memory unit, the inputs of which are connected to the outputs of the computing unit, and the outputs of the second group of outputs of the synchronization unit are separately connected to the synchronizing inputs of the third triggers. From the memory unit 9 of FIG. 2 Rtbsha fe.3 OnrSiDKQ /. delays From trigger 6- From trigger 7-7 No. 2 $