RU1793448C - Dividing device - Google Patents

Description

Fig. /

The invention relates to computer technology and can be used in analog computers.

The purpose of the invention is to improve the accuracy of the device.

In FIG. 1 shows a structural diagram of the proposed device; in FIG. 2 are timing diagrams illustrating its operation.

The dividing device comprises a clock pulse generator 1, a switch 2, a signal processor 3, an algebraic accumulation memory unit 4, an adder 5, a key 6, input 7 and 8, and output 9 and 10 buses. The first output of the generator 1 is connected to the first control inputs of the switch 2 and block 4, the second output is connected to the second control inputs of the switch 2 and block 4, and the third output is connected to the third control input of the switch 2 and the control input of key 6, information input which is connected to the output of the adder 5 and the bus 10, and the output to the second summing input of the adder 5. The first, second and third information inputs of the switch 2 are connected to the buses 7, 8 and 10, respectively; but, the output is with the input of the logarithm 3, the output of which is connected to the information input of block 4 and the subtracting input of the adder 5, connected by the first summing input with the output of block 4 and bus 9.

The device operates as follows.

The generator generates at its first (Fig. 2a), second (Fig. 26) and third (Fig. 2c) outputs rectangular pulses shifted in time relative to each other, the levels of which are sufficient to close the channels of switch 1 and key b and to ensure recording signals from the output of the logarithm 3 to block 4. The signal from the first output of generator 1 goes to the first control inputs of switch 2 and block 4, the signal from its second output goes to the second control inputs of switch 2 and block 4, and the signal from its third output - to the third control input switch 2 and the control input of switch 6.

Under the action of a signal from the first output of generator 1, switch 2 connects to

the input of the logarithm 3 signal level A from the bus 7 and the output of the logarithm 3 is the signal Ui log A

which is stored by block 4.

Under the action of the signal from the second output of the generator 1, the switch 2 connects a level B signal from the bus 8 to the input of the logarithm 3, the signal U2 log B is generated at the output of the logarithm 3.

which in block 4 is subtracted from the signal Ui, the result of the subtraction is stored in block 4. At the end of the action of the signal from the second

the output of the generator 1 in block 4 turns out to be a stored signal

U4 - Ui - U2 - log -g,

ABOUT)

which goes to bus 9 and to the first summing input of adder 5.

Under the action of the signal from the third output of the generator 1, the key b connects the output of the adder 5 to its second summing input, and the switch 2 connects the output of the adder 5 to the input of the logarithm 3. At the output of the adder 5 and on bus 10, a signal Us is generated, which is fed to the second input of the adder 5 and to the input of the logarithm 3.

A signal is generated at the output of the logarithm 3

Uz log us, (2) which goes to the subtracting input of adder 5.

Given that the signal Us at the output of adder 5 is equal to the algebraic sum of the signals U4, Us and Ua at its inputs, we can write

 + U5-U3 or

U of.

Taking into account equations (1) and (2), we obtain

log - | log Us or

- $

Thus, at the output of block 4 and bus 9, a signal is formed equal to the Logarithm of the ratio of signals on buses 7 and 8, and at the output of the adder 5 and bus 10, a signal equal to this ratio itself.

Claims (1)

SUMMARY OF THE INVENTION A dividing device comprising a switch, the first and second information inputs of which are respectively the inputs of the dividend and divider devices, the output of the switch through the logarithm is connected to the information input of the algebraic summation storage unit, the control inputs of which and the control inputs of the switch are connected to corresponding outputs of the clock generator, characterized in that, in order to increase accuracy, a key and an adder connected to it are inserted the subtracting input to the output of the logarithm, the first summing input to the output of the memory block of the algebraic summation, and the output to the third information input of the switch and through the key to its second summing input, the outputs of the adder and the output of the memory block of algebraic summation are respectively the main and additional outputs of the device, the control input of the key is connected to the additional output of the clock generator and the corresponding control input of the switch.  B t n 8 t t t FIG. 2