RU1780033C - Active power-to-digital code converter - Google Patents

Abstract

Usage: control of electric power parameters of an industrial network as part of information-measuring systems. The inventive device contains two calibrated resistors 1 and 28, a level 2 latch, a reference voltage source 3, two analog switches 4 and 29, a voltage converter code 5, six registers 6-11, an adder 12, a multiplier 13, two constant of memory units 14 and 15, pulse generator 16, clock generator 17, two counters 18 and 19, delay element 20. Element 21, control unit 22, two switches 23 and 24, OR element 25, multiplexer 26, divider 27 the wife. 2 il.flee vzhpzu Humvi / H lmiOS ^ gCOСVI00о оСО) CA > &

Description

The invention relates to electrical engineering and is intended for use in combination

information-measuring system for monitoring the parameters of electricity in an industrial network.

A known converter of active power into a digital code containing a calibrated resistor, a level lock, a reference voltage source, an analog switch, a voltage to code converter, six registers, an adder, a multiplier, two read-only memory devices, a pulse shaper, a reference frequency generator, two counter, delay element, AND element, and control signal generator 1.

Not, the disadvantage of the known device is the low conversion accuracy.

The closest in technical essence to the present invention is an active power to digital code converter comprising a calibrated resistor, level lock, reference voltage source, first and second analog switches, first and second voltage to code converters, registers, adder, multiplier, read-only memory devices, pulse generator, reference frequency generator, counters, delay element, AND element, control signal generator, voltage divider, multiplexer, many ovhodovy OR-NO element, first and second AND gates 2.

In a real industrial network, for reasons of all kinds of switching switching, triggering of automation equipment, non-linear nature and sudden fluctuations in the load of an electricity consumer, etc., there are pulsed noise distorting the sinusoidal shape of the electric signal with multiple excesses of its amplitude and a wide range of variation in the duration of impulse distortions .

In addition, due to the switching phenomena listed above, the nonlinear and complex nature of the load P (1I) p (lii) {TGH otherwise O, - Mi-iaui where Jii and Г | 2 are the mathematical expectations of ii and Ii2. With equal uniform distributions of the absolute random components of the errors of the level lock and the power consumer, as well as due to the pronounced parasitic frequency properties of the power network (inductance, mutual inductance and capacitance of phase and linear connections, etc.), a wide range of harmonics is observed, from the first ( 50 Hz) to the hundredth, on the network, which leads to distortion of the waveform (triangular, bell-shaped), especially in the case of transients, for example, the mode of inrush currents.

In this case, within a few seconds, the voltage or current level in the network can be several times higher than the corresponding level in the normal steady state, to which the voltage or current returns at the end of the transient process.

To work with this measured signal, the prototype comprises two voltage to voltage converters.

The first of them processes the input signal at a scale not exceeding the amplitude of the nominal value of the sinusoidal or non-sinusoidal shape, and the second when this amplitude is exceeded.

Based on these considerations, the prototype circuit contains two approximately identical channels for measuring the input signal: analog switches, voltage to code converters, voltage divider.

The accuracy of converting active power to code in the prototype circuit is determined mainly by the metrological parameters of the level lock, as well as voltage converters to code, i.e. their speed and accuracy, since according to Kotelnikov’s theorem, the higher the sampling frequency, the more accurately the input signal can be converted with significant distortions using the digital processing of instantaneous values to measure active power.

With a uniform distribution of the absolute random error of the transducers within ± Ai2i and ± Ai22, the codes NI-II and Ni2i correspond to the values of the input current (1i ± Ai2i) and (Ii2 ± D122) with the probability distribution densities if 111 if III i2i iii Ih - Г Д121, (1) | 21 iii 1i + AI21, (2) at the corresponding input voltage levels within ± Au2i and ± Di22, the composition of these distributions in both cases is the Simpeon distribution within ± 2 Di21 and ± 2 And U22, respectively. Thus, the Null codes correspond to the values of the input2 Au2l-Uii + uii 4 Au2i ц +2 Au2i - UH P (uii) 4 AlJ21 otherwise 0, 2 Au22 Ui2 + ui2 4 A U22 U | 2 + 2AU22-U, 2 p ( ui2). 4 Au22 otherwise 0, where Uii and Ui2 are the mathematical expectations of uii and ui2, respectively. The mathematical expectation of the product of the instantaneous values of the current and voltage UI1 ill at the Nth point of their sampling and its dispersion with the independence of their transformations using a converter, i.e. when the input signal does not exceed the scale of the latter:, Uii + 2Au21 III + 2Al21 M UMili //.XU|i-2Au21 tli-2Al21 xuii IH P (uii) p (til) d uii d iii Uii 111 1 (5) U | i + 2Au21 Ili + 2Al21 D uiilii .X Uli-2Au21 Iii-2Ai21 X (UH 111 - M UH IH) 2 p (UH) p (ili) XX d UH d IH I (UiH A I2i H IH A U21 + + | AI21 AU21). If the input signal exceeds the scale of the first converter, the second converter operates. In this case, similarly to reasoning, we obtain the mathematical expectation and variance. M ut2 Ii21 Ui2 Ii2; (7) (XAU22 + | AJ22 AU22 J The total dispersion of the result of the conversion of the input current and voltage, in order to calculate the active power for the period Tx Dr Tx2 {Е D {uii 2 .. (9) Н 112 1 where Tx-Cn + t) ATx. Consequently, the total root-mean-square value of atz of random ω, if if, if the NECS of the voltage are (Uc ± 2Au22) and (Ui2 ± 2 Au22) with the probability distribution densities: Uii -2 Au2i Uii, ii uii: UH -t- 2 Au2i Ul2 - 2 AU22,,, y, -b 2 AU22, which represent the prototype errors, is defined by the expression a. / | ATx / u (t) l (t) dt Е (Л1 Дl2t -t „А 1) + f; (Tg and 1h I /u(.)P(Od, neglecting the effect of the products Au2ix Ai2i and Au22 Al22 in view of The random component of the error characterizing that the probability of coincidence of Au2i Au22 and Ai2i Al22 for two converters of the same type is very low is practically impossible.This difference is determined by the technological spread, aging of the elements, etc., which is explained the complex internal structure of the ADCs used as converters, these differences cause random errors of the converters to vary Thus, a disadvantage of the prototype is that in transient conditions and during switching events in an industrial network, the total error of converting active power to code increases due to different intervals of random errors of the converters, which is expressed in the difference between the limits AU21 and AU22, Al21 And Ai22. In addition, the presence of a scatter in the parameters of the transducers causes an additive component of the conversion error: ДТхЕ () (uj + Au2) -u} lj. rJ 1 5dd2 ijTjTf; - / u (t) l (t) dt

where A12 and Au2 are the difference between the additive errors of the converters, and the additive error of zero is accepted for the first of them.

After simple converters (11) we get:

d Urm Ai2 + Irm A U2 / .o

D U ™ Ucos o

assuming that the deviation of the input signal from the scale of the transducer 5 contains m sampling points per period, appears in only one half-wave of the period Tx, and the average values of the voltage and current during this time are Urm and Irm, and about the phase shift between them,

Thus, the disadvantage of the prototype is the low accuracy of the conversion of the active power of transient signals and impulse deviations in an industrial power grid.

The purpose of the invention is to improve the accuracy of conversion.

This goal is achieved in that the active power into a digital code converter containing a first calibrated resistor, a level lock, a reference voltage source, first and second analog switches, a voltage to code converter, six registers, an adder, a multiplier, a first and second constant data storage units, a pulse shaper, a reference frequency generator, first and second counters, a delay element, an I element, a control signal shaper, a multiplexer and a voltage divider, the fix input being the level switch is connected to the input voltage bus, the first output of the first calibrated resistor is connected to the current bus, the input of the pulse former and the first inputs of the analog switches, the output of the first analog switch is connected to the information input of the voltage converter to the code, the first output of the reference voltage source is connected to the second input of the first analog switch, the output of the level lock is connected to the third input of the first and second input of the second analog switch, the output is multip the lexor is connected to the input of the first register, the first output of the first register through the And element is connected to the inputs of the selection and transfer of the first adder channel, and the second outputs to the second inputs of the first adder channel, the first input of the first adder channel is connected to the ground bus, and the outputs are with the inputs of the third register, the outputs of the higher bits of the adder are also connected to the inputs of the second register and the inputs of the second channel of the multiplier, also connected to the outputs of the fourth register, the inputs of the first channel of the multiplier are connected to the second register and constant memory blocks, and the outputs - with the inputs of the fourth, fifth registers and inputs of the third channel of the adder, the inputs of the second channel of which are connected to the outputs of the third register, the output of the reference frequency generator is connected to the synchronization input of the pulse generator, the recording input of the first register and the input of the first counter, the outputs

bits of which are connected to the inputs

sixth register, and the reset input to zero to the input of the second counter and through the element

delays to the input of the sixth register entry

and the output of the pulse shaper, inputs

the first and second permanent memory blocks are connected, respectively, to the outputs of the fifth and sixth registers, the first input of the driver of the control signals is connected to the output of the generator

reference frequency, the outputs of the first and second counters are connected to the first and second groups of inputs of the driver of the control signals, the output control bus of which is connected to the control input

the first analog switch, the control input of the second analog switch, the control input of the level lock, the clock input of the voltage to code converter, the first input of AND element, write inputs of the second, third, fourth, fifth registers and multiplier, read permission inputs of the second and fourth register, control inputs of the adder and read-only memory blocks, inputs

resetting the third and fifth registers, inputs of the selection of adder channels, as well as inputs of managing the product multiplier register, in addition, all the inputs of the multiplexer are connected to the inputs of the first register,

the first and second comparators, the OR element, and the second calibrated resistor are introduced, the first inputs of the comparators connected to the output of the second analog switch, and their second inputs to the corresponding outputs of the reference voltage source, the outputs of the comparators connected to the inputs of the OR element, the output of which is connected to the address zhor, oh multiplexer and second manager

the input of the first analog switch, the third and fourth control inputs of which are connected to the corresponding terminals of the output bus of the driver of the control signals, in addition, the control inputs of the comparators are connected to

the control input of the voltage converter to the code, and the second output of the first calibrated resistor is connected through the second calibrated resistor to the ground bus and to the fourth input of the first analog switch, the fifth input of which is connected to the output of the voltage divider, the output of the level lock is connected to the input of the divider voltage, the output of the voltage converter into the code is connected to the high-order bits of the first inputs and the low-order bits of the second inputs of the multiplexer, and its low-order bits of the first inputs and the high-order bits of the second connected to earth bus.

The new elements revealed in comparison with the prototype are known from various sources of information. So, in the particular case of implementation, the first and second comparators are built on 597CA2 (bKo. 347.190 TU).

As an OR element, the K555LL1 chip (B.Ko.348.289 TU5) was used.

No solutions with a similar combination of known elements were found.

The significance of the differences in the solution lies in the fact that the obtained new interconnection of the known elements of the claimed converter made it possible to increase the conversion accuracy by a factor of 2. This, in turn, leads to energy savings due to a more accurate accounting of the consumed electricity when using the proposed converter of active power into a digital code. Thus, the solution is novel and meets the criterion of significant differences.

On Fig, 1 presents a functional diagram of the proposed Converter of active power into a digital code; Fig. 2 is a timing chart of its operation.

The converter of active power into a digital code contains the first 1 and second 28 calibrated resistors, a level 2 latch, a voltage reference source 3, the first 4 and second 29 analog switches, voltage to code converter 5, registers 6-11, adder 12, a multiplier 13, read-only memory blocks 14 and 15, pulse shaper 16, reference frequency generator 17, counters 18 and 19, delay element 20, AND element 21, control signal generator 22, first 23 and second 24 comparators, OR element 25, multiplexer 26 and voltage 27.

The input of the fixed level 2 is connected to the input voltage bus. The first output of the first calibrated resistor 1 is connected to the current input bus, the input of the pulse generator 16 and the first inputs of the analog switches 4 and 29. The output of the first analog switch 4 is connected to the information input of the voltage converter 5 5 to the code. The first output of the reference voltage source 3 is connected to the second input of the first analog switch 4. The output of the level 2 latch is connected to the third input of the first 4 and the second input of the second 29 analog switches. The output of the multiplexer 26 is connected to the input of the first register 6. The first output of the first register 6 through the element And 21 is connected to the inputs of the mode selection and transfer of the first channel of the adder 12, and the second outputs to the second inputs of the first channel of the adder 12. The first input of the first channel of the adder 12 is connected to a ground bus. Adder Outputs 12

0 are connected to the inputs of the third register 8. The outputs of the higher bits of the adder 12 are also connected to the inputs of the second register 7 and the inputs of the second channel of the multiplier 13, also connected to the outputs

5 of the fourth register 9. The inputs of the first channel of the multiplier 13 are connected to the outputs of the second register 7 and read-only memory blocks 14, 15, and the outputs are connected to the inputs of the fourth 9, fifth of 10 registers and inputs

0 of the third channel of the adder 12. The inputs of the second channel of the last are connected to the outputs of the third register 8. The output of the reference frequency generator 17 is connected to the synchronization input of the pulse generator 16, the recording input of the first register 6 and the input of the first counter 18. The outputs of the bits of the counter 18 are connected to the inputs of the sixth register 11, and the reset input is zero to the input of the second counter 19 and through the delay element 20 to the recording input of the sixth register 11 and the output of the pulse shaper 16. The inputs of the first 14 and second 15 read-only memory blocks are connected, respectively, to the outputs of the fifth 10 and sixth registers. The first input of the driver 22 of the control signals is connected to the output of the generator 17 of the reference frequency. The outputs of the first 18 and second 19 counters are connected to the first and second

0 groups of inputs of the shaper 22 control signals. The output bus of the latter is connected to the control input of the first analog switch 4, the control input of the second analog switch 29.

5 to the control input of the level 2 latch, the clock input of the voltage converter 5 to the code, the first input of the And 21 element, the write inputs of the registers 7-11 and the multiplier 13, the read enable inputs of the second 7 and the fourth 9 registers, inputs

the control of the adder 12 and the read-only memory blocks 14, 15, the reset inputs of the third 8 and fifth of 10 registers, the channel selection inputs of the adder 12, as well as the multiplier output register control inputs 13.

The first inputs of the comparators 23 and 24 are connected to the output of the second analog switch 29, and their second inputs are connected to the corresponding outputs of the reference voltage source 3. The outputs of the comparators 23 and 24 are connected to the inputs of the OR element 25, the output of which is connected to the address input of the multiplexer 26 and the second control input of the first analog switch 4. The third and fourth control inputs of the latter are connected to the corresponding terminals of the output bus of the control signal generator 22. The control inputs of the comparators 23, 24 are connected to the control input of the voltage converter 5 to the code.

The second output of the first calibrated resistor 1 is connected through the second calibrated resistor 28 to the ground bus and to the fourth input of the first analog switch 4, the fifth input of which is connected to the output of the voltage divider 27. The output of the level 2 latch is connected to the input of the voltage divider 27. The output of the voltage converter 5 to the code is connected to the high order bits of the first inputs and the low order bits of the second inputs of multiplexer 26, and its low order bits of the first inputs and high order bits of the second inputs are connected to the ground bus.

In a particular converter implemented, a level 2 latch is constructed according to the circuit shown in the book Vorobev N.V., Werner V.D. The elemental base and circuitry of the interface means. - M .: Higher school, 1984, p. 22, fig. 1.18. The reference voltage source 3 is constructed according to the scheme from the same book (c, 58, Fig. 2.47) with the addition of two resistor dividers at its output to provide three reference voltage values at the three outputs of source 3.

The analogue switches 4.29 and the voltage converter 5 to the code are constructed according to the schemes, respectively (see the book by N.V. Vorobyev and V.D. Werner, p.19, Fig.1.14 and the article by Klimashauskas K.Yu., Marcink Vichusa A, I.K., Stashisa I.V. High-speed eight-bit ADC K1107PV2, Electronic industry, Mg 7, 1985, Fig. 1, p.31).

Registers 6–11 are memory registers with buffer devices at the outputs that allow disconnecting the register outputs from external circuits (see the book by V.L. Gorbunov, D.I. Panfilova, D.L. Presiukhina, Fundamentals of Microcomputer Construction. M .: High school, 1984, p. 110, fig. 3.5). The adder 12 and the multiplier 13 are built, similarly to the prototype, respectively, on the chips KR 1802IM1 (6K0.348.629-11TU) and KR1802VRZ (6K0.348.629-07TU).

Read only memory

14 and 15 are constructed according to the scheme described in the book by Alekseenko A.G., Shagurina I.I. Microcircuitry. - M .: Radio and communications, 1982, Fig. 7.17, P.269.

The pulse generator 16 is built, like the prototype, on a Schmitt trigger with an output connected to the trigger D-input, the R and C inputs of which are connected to the driver synchronization input, and the direct output is the output of the latter.

The counters 18, 19 and the element And 21 are built on E555IE7 chips (b.Ko.348.289. TUZ) and K555LI1 (bKo.348.289 TU1).

The driver 22 of the control signals along with the designations of its inputs and outputs is similar to that used in the prototype, where it is described in detail.

As multiplexer 26, the K555KP11 chip (bKo.348.28914TU) was used.

The proposed Converter of active power to code works as follows.

Shaper 16 extracts periods Tj

oscillations of the input current l (t), which determine the conversion intervals, and at the beginning of each current period (see Fig. 2,6) generates a pulse synchronized with the pulse of the reference sequence with

the output of the generator 17 (see Fig. 2, a), moving along its leading edge, the code is transferred from the counter 18 to the register 11, and after a time determined by the delay element 20, the counter 18 is reset to zero. During

of the next period Tj, the counter 18 counts the number of pulses by the reference repetition rate fo from the output of the generator 17

NTj fo-Tj, (13)

whose code at the beginning of the next period

Tj + 1 is transferred to register 11. The output code of register 11 is the address for read only memory 15, where the code number 1 is written to address NTJ. Junior period TT

counter 18 (see FIG. 2, c) determines the sampling step of the input signals and is divided into four clock cycles n, T2, tz and T4. In the first clock cycle T1 of the next sampling step tm (CP. Fig. 2, c), the voltage drop value is R- Im

on calibrated resistors 1 and 28, it is directly proportional to the value of im of the input current at the current point m of the period Tj, and the value of the input voltage Um at the same point is supplied through the analog switch 4 to the input of the converter, respectively

5i and to the input of the latch 2 installed by the driver 22 into the signal sampling mode (see Fig. 2, d, e), where they are fixed. In the second step G2 of step tm, the converter 5 is set by the former 22 to the storage mode (see Fig. 2, e) and converts the voltage R-im into a digital forward code Nim, transferred at the end of G2 by the leading edge of the signal from the output of the generator 17 (see 2, a) through multiplexer 26 to register 6:

N | Kl-lm,. (14)

where Ki is the coefficient of proportionality.

In the third clock cycle of step tm (see Fig. 2, c), the switch 4 controlled by the driver 22 (see Fig. 2, c) connects the voltage um from the output of the latch 2 to the input of the converter 5, and the adder 12 performs the conversion direct Nim code to optional. In this case, adder 12 is set to the state of sampling the first channel and read permission (see Fig. 2, g, h), and the input of the mode selection and transfer of this channel with an inverse value of Nim receives 1 sign of this number, which determines the inversion of the adder code and adding to the result of inverting unity. At the end of G3, the result of the conversion by the signal from the output of the adder (see Fig. 2, and) is transferred to register 7. With a positive value of Ni, its code remains unchanged, since the direct and additional codes of a positive number coincide.

In the fourth step t of step tm, the converter 5 converts the voltage Um into a digital direct code of the number Num (see figure 2, e):

Num KU- Um, (15)

where KU is the proportionality coefficient, which at the end of the conversion is transferred through the multiplexer 26 to the register

6 (see Fig. 2, a), and in the second clock cycle T2 of the next sampling step tm + i is converted by the adder 12 into an additional code (see Fig. 2, c, g, h). At the end, the codes of the numbers Num and Nim, respectively, from the outputs of the adder 12 and the register 7, which are in the state of read permission (see Fig. 2,3, g) are recorded by the signal from the output of the driver 22 (see Fig. 2, k) to the multiplier 13, where during the next clock cycle Gz (see Fig. 2, c) are multiplied, after which the result of the multiplication under the control of the former 22 (see Fig. 2, m, i) is entered in the product register. In the first step of the sampling step tm + 2, the product code Nim Num from the output of the multiplier

5 of the device 13 is fed to the inputs of the second channel of the adder 12 installed by the former 22 in the state of sampling the second and third channels (see Fig.2.p), where it is added to the sum of the results of multiplying the values of the input signals for (t-1) previous points their discretization in the current conversion interval Tj from the outputs of register 8, after which the result of summing the signals from the output.

5 of the shaper 22 (see FIG. 2, p) is entered in the register 8. The values of the input signals of all sampling points for the interval Tj are subjected to such processing, except that the result of the multiplication of codes

0 of the input signals for the last fine discretization beyond Tj are not written to the product register of the device 13, but directly in the fourth step of the sampling step ti of the conversion interval

5 is added by adder 12 with the output code of register 8 (see Fig. 2, b, c, m, n, n), after which the resulting code

p1

NZJ 2:, - (16)

0m g

transferred to the device 13 (see figure 2, h, l) simultaneously with the code of the coefficient of correction K | with the output of read-only memory 14 installed

5 by former 22 (see FIG. 2, t) in read enable mode. During the second clock cycle G2 of step t2 in the interval Tj-t-i, multiplication by the coefficient Kk is carried out, after which the result of multiplying from the output

0 device 13 (see figure 2, m, n), directly proportional to the active energy

/ l (t) .u

(t) dt, (17)

N.J KK-NJ: J KV

where KW is the proportionality coefficient, is recorded in register 9 (see Fig. 2, e).

At the beginning of the fourth clock, the former 22 is reset to O of register 8 (see Fig. 2, h). At the end of the same measure

NWJ codes from the output of register 9 and I / NTI from the output of read-only memory 15 (see Fig. 2, f) are entered into the device 13, where they are multiplied (see Fig. 2, l), after which the result of multiplication, etc. mo percentage of active power is transferred to register 9 (see Fig. 2, m, n, y);

At) and (

Npj NWJ / NTJ Cr / l (t) u (t) dt

(1B)

about

A correction factor Kk is introduced to correct the additional error caused by the change in the ambient temperature and the aging of the elements. The possible values of the correction coefficient in a predetermined temperature range of the inverter operation are stored in a constant storage device 14 in advance. The selection of the desired Qc value is carried out as follows. Periodically, after a certain number of periods 1 (t), the counter 19 is set to a state that determines the correction interval Tk and ensures that the reference voltage source 3 is connected to the analog input of the converter 5 (see Fig. 2, x). During the interval Tk, the reference voltage Uo undergoes the same transformations as the input variable signals R i (t) and u (t). At the beginning of the next interval Tk + 1 (see Fig. 2,6} register 10, output code which determines the address of access to the read-only memory device 14, is reset by the signal from the driver 22 (see FIG. 2, c) to the state that determines the code of the number 1 at the output of the device 14. The resulting conversion code Uo for Tk is multiplied by Kk- 1 and 1 / NTK, after which the result of the conversion is transferred to register 10 (see, Fig. 2, h), determining the address to device 14 until the next conversion interval Uo .. Comparators 23 and 24, operating synchronously with the voltage converter 5 to the code, control the value of the current input signal by comparing it with the values Uni and Un2 coming from the outputs of the reference voltage source 3: Uni Umax + AU I, .Q Un2 Umln-Au I where Umax and Umin are the maximum and minimum values of the input voltage, which determine the measurement scale of the voltage transducer 5 into a digital code: Di is the voltage deviation value, depending on the sensitivity of the transducer 5 and equal to its guise mladschego bit (taken from the reasons that the value of the random component of the error comparators converter 5 and no more than half the least significant bit converter 5). If the value of the input signal does not exceed the scale of the converter 5, then the value of the logic zero is set at the output of the OR element 25, and the analog switch 4 confirms the receipt of signals from the output of the level 2 latch and from the first output of the resistor 1 without changing, e. with a single transmission coefficient, When the input signal deviates from the scale Umax + D and; Umin - Au appears the level of a logical unit at the output of one of the comparators 23 or 24, controlling the signal level from the output of the second analog switch 29, which forces the first analog switch 4 to switch and change the transmission coefficient of that channel (voltage or current), where a deviation occurred, either in the signal from the output of the voltage divider 27, or from the point of connection of the resistors 1 and 28. The difference between the codes at the output of the voltage converter 5 to the code will be different in both cases, i.e. the value of its least significant bit, when the input signal is within and outside the scale, a different voltage value will correspond. Consider the case of quadrupling the scale of converter 5, then the transmission coefficient of the voltage divider 27 and the divider on resistors 1, 28. p 4, which corresponds to two binary bits (). In this case, the operation of the multiplexer 26 is organized in such a way that when the level of zero is at the output of the OR element 25 (the input signal does not exceed the scale Umax + Д and; Umin - Аи), a code of the form ICON is set at the output of the multiplexer 26, (20a ) where 1 is the sign code, N is the code from the output of the converter 5, When at the output of the OR element 25 there is a level (the input signal exceeds the scale of Umax + and; Umin- and), a code of the form INOO is set at the output of the multiplexer 26. (206) Thus, for example, in the case of using a converter 5 of type K1107PV2, we have at the output multiplexer 26 10-bit bus. After further calculations using the algorithm for finding the active power value, the extra bits can be removed by simply reducing the bit size of the result code. The total rms value C7fi of the random error components of the proposed device is determined by the expression 2 (ui2Di2 + 1i2 Aui2) / r-ATxVТх / u (t) - | (t) dt

taking into account the fact that when the measuring scale of the transducer 5 is changed, its values of the absolute random errors ± Ah and ± Aui are not named, and Uii and IH are the mathematical expectations uii and.

Comparing the expressions (10) and (21), accept the Ai2i Ali and

ma with that

A U22 AA

  Au2i aui as well that square

segments of the input signal when issuing codes of instantaneous values uii and iii by converters 5 and 25 (in the case of the prototype)

P

2 SUl2Ai22

2 A 121

those. SUii

equal, and 1

12 1

m

P

And Xi D21 D22. Get 2 liters ,,. 2

And 112 1

Qr.grr 2 2 Hz. /

In addition, based on the operating principle of the proposed device, it can be seen that in this case there is no component error due to the difference in additive systematic errors of the converters 5 and 25, which is typical for the prototype. Thus, the proposed converter of active power to code has at least 2 times higher accuracy of converting signals from an industrial power supply network in comparison with the prototype.

Claims (1)

SUMMARY OF THE INVENTION An active power to digital code converter comprising: a first calibrated resistor, a level lock, a voltage reference source, first and second analog switches, a voltage to code converter, six registers, an adder, a multiplier, first and second read-only memory blocks; a pulse former, a reference frequency generator, first and second counters, a delay element, an And element, a driver of control signals, a multiplexer and a voltage divider, the input of the level lock of the connection n with the input voltage bus, the first output of the first calibrated resistor is connected to the current input bus, the input of the pulse former and the first inputs of the analog switches, the output of the first analog switch is connected to the information input of the voltage converter into a code, the first output of the reference voltage source is connected to the second the input of the first analog switch, the output of the level lock is connected to the third input of the first and second input of the second analog switches, the output of the multiplexer is connected to the input at the first register, the first output of the first register through the AND element is connected to the inputs of mode selection and transfer of the first adder channel, and the second outputs to the second inputs of the first adder channel, the first input of the first adder channel is connected to the ground bus, and the outputs to the inputs of the third register, the high-order outputs of the adder are also connected to the inputs of the second register and the inputs of the second channel of the multiplier, also connected to the outputs of the fourth register, the inputs of the first channel of the multiplier are connected to the outputs of the second register and the post nnyh memory blocks and outputs of the fourth input c n of registers and the third adder input channel, the second channel inputs are connected to outputs of the third register, the output of reference frequency oscillator is coupled to an input of the synchronization pulse, recording of the first input 5 of the register and the input of the first counter, the bit outputs of which are connected to the inputs of the sixth register, and the reset input to zero - to the input of the second counter and through the delay element to the recording input of the sixth register and 0 to the output of the pulse former, the inputs of the first and second constant memory blocks are connected respectively to the outputs of the fifth and sixth registers, the first input of the driver of the control signals is connected to the output of the reference frequency generator, the outputs of the first and second counters are connected to the first and second groups of inputs of the driver of the control signals, the control output bus of which is connected to the control input of the first analog switch, the control input of the second analog switch, the control input latch level, the clock input of the voltage converter in 5 code, the first input of the And element, the recording entries of the second, third, fourth, fifth registers and the multiplier, the read resolution inputs of the second and fourth registers, the adder control inputs, and 0 constant memory blocks, reset inputs of the third and fifth registers, inputs of the selection of adder channels, as well as inputs for controlling the product multiplier register, characterized in that, for the purpose of 5 to increase the conversion accuracy of the device, the first and second comparators, the OR element, and the second calibrated resistor are introduced into it, the first inputs of the comparators connected to the output of the second analog switch, and their second the inputs are with the corresponding outputs of the reference voltage source, the outputs of the comparators are connected to the inputs of the OR element, the output of which is connected to the address input of the multiplexer and the second control input of the first analog switch, the third and fourth control inputs of which are connected to the corresponding outputs of the output bus of the control signals, in addition, the control inputs of the comparators are connected to the control input of the voltage to code converter, and the second output the first calibrated resistor is connected through the second calibrated resistor to the ground bus and the fourth input of the first analog switch, the fifth input of which is connected to the output of the voltage divider, the output of the level lock is connected to the input of the voltage divider, the output of the voltage converter to the code is connected to the older bits ladies first entrances 0 and the low order bits of the second inputs of the multiplexer, and its low order bits of the first inputs and the high order bits of the second are connected to the ground bus. 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