RU2018142C1 - Device for measuring electric parameters - Google Patents

Abstract

FIELD: digital measurement technology. SUBSTANCE: device for measuring electric parameters has serially-connected object 1 to be tested, units 2 for matching levels of input measured parameters of the object being tested, analogue switching unit 3, filter 4, sample-and-hold element 5, analogue-to-digital converter 6 infomation input of which is connected to information output of sample-and-hold element 5, computer unit 7, address bus 8, control bus 21 and information buses of data output 19 and input 20 of the computer unit through which information outputs of analogue-digital converter 6 and computer 7, are interconnected pulse frequency shaper 9, period-to-code converter 10, sampling interval shaper 11, reference frequency generator 12, frequency divider 13 by two, two decoders 14, 15, two AND gates 16, 17, delay element 18. EFFECT: enhanced accuracy. 4 dwg

Description

 The invention relates to digital electrical engineering and can be used in monitoring systems for power nodes, in particular in on-board power supply systems.

 Known devices for measuring electrical parameters (currents and voltages), based on the digital conversion of the measured analog value and subsequent processing of the obtained digital values in the microprocessor to obtain the value of the measured parameter.

 Depending on the software implementation in a digital computer, these devices allow the measurement of amplitude, average, and rms voltage and current values.

 Their main disadvantage is the low accuracy of the measurement when the frequency of the measured parameter deviates from the nominal and the significant time spent on the program due to the need to increase the number of discrete samples for the measurement period.

 The closest in technical essence to the proposed device is a device that contains a series-connected control object, coordinators of the levels of the input measured parameters of the control object, an analog switch (AK), a filter, a sampling-storage circuit, an analog-to-digital converter (ADC), the information input of which connected to the information output of the sampling-storage circuit, a computing device (VU), an address bus, a control bus, information buses for outputting and inputting data of a computing device va, which are connected via data outputs and ADC slave.

 This device also has a low accuracy when the frequency of the measured parameters deviates from the set values, as well as low speed due to the significant time spent on information processing.

 The purpose of the invention is to improve the accuracy and speed of measurement of electrical parameters.

 This goal is achieved by the fact that in the known device for measuring electrical parameters, containing a series-connected control object, matching devices of the levels of the input measured parameters of the control object, an analog switch AK, filter F, a sampling-storage circuit, an analog-to-digital converter of the ADC, the information input of which is connected to information output of the sampling-storage scheme, computing device VU, address bus, control bus and information bus output and input data of the computing device The means by which the information outputs of the ADC and the VU are connected, the pulse generator of the frequency converter frequency converter, the converter period-code PPK, the generator of the sampling intervals of the PID, the reference frequency generator, the frequency divider by 2, two decoders, two circuits, and a delay circuit so that the information output are introduced the analog switch AK is connected through a filter to the input of the frequency converter of the frequency converter and the information input of the sampling-storage circuit, the output of the frequency generator of the frequency converter is connected to the input of the period -code AUC, the first input of the first AND gate and to an input of frequency divider 2, whose output is connected to the second input of the second AND gate, whose output is connected to the input of "Start" shaper FID sampling interval; the information outputs of the period-code converter PPC are connected to the data input bus of the VU computing device, and the information inputs of the period-code converter are connected to the data output bus of the VU computing device, the output of the period-code converter PPC "Transformation end" ("KP") is connected to the first input "TPR1" (Interrupt requirement) of the computing device VU, and the input "Start" of the converter period-code PPK is connected to the output of the first AND circuit; to the data output bus of the computing device, the information inputs of the FID sampling interval generator are connected, and ADC control inputs (6), PID (11), PPC (10), the reference frequency input of the PPC period-code converter are connected to the VU I / O control bus and the PID sampling interval generator is connected to the output of the reference frequency generator; the control output of the PID sampling interval generator is connected to the “Start” input of the sample-storage circuit and to the input of the delay circuit, the output of which is connected to the “Start” input of the ADC analog-to-digital converter, the “Ready” output of which is connected to the second TPR2 input (requirement interruptions) of the WU computing device, whose information outputs are connected through the address bus to the inputs of both decoders, the outputs of the first decoder connected to the control input of the analog switch AK, the first output of the second decoder connected to the second input of the first circuit And, and the second output of the second decoder is connected to the first input of the second circuit I.

 In the known technical solutions, no signs have been found that distinguish the proposed solution from the prototype, therefore, we can conclude that this solution has "significant differences".

 Figure 1 presents a block diagram of a device for measuring electrical parameters; figure 1 is a timing diagram of the signals at the input and output of the frequency pulse former (FIC); figure 3 is a timing chart explaining the principle of synchronization of the number of samples with the period of the measured signal; in FIG. 4 is an illustration of the appearance of a lead error due to the approximate calculation of a sampling interval.

 The proposed device for measuring electrical parameters (Fig. 1) contains a control object 1, level coordinators 2 of the input measured parameters of the control object, an analog 3 switch (AK), a filter 4, a sampling-storage circuit 5, an analog-digital 6 ADC converter, the information input of which connected to the information output of the sample-storage circuit 5, sample-storage, analog-to-digital 6 ADC converter, the information input of which is connected to the information output of the sample-storage circuit 5, computing device 7 WU, address 8 th bus, control bus 21, output data lines 19 and data input 20 BV 7, which are connected via data outputs of analog-to-digital converter ADC 6 and 7 slave computing device. In addition, the proposed device comprises a driver of 9 pulses of the frequency of the frequency converter, a converter 10, a period-code of the control panel, a generator of 11 sampling intervals of the PHIL, a generator of 12 reference frequencies, a frequency divider 13 by 2, decoders 14 and 15, two circuits I 16 and 17, and a circuit delays 18. The information output of analog 3 of the AK switch is connected through a filter Ф 4 to the input of the generator of 9 pulses of the frequency of the PMF and the information input of the sampling-storage circuit 5. The output of FIC 9 is connected to the input of the converter 10 period-code of the control panel, the first input of the second circuit And 16 and the input of the frequency divider 13 by 2, the output of which is connected to the second input of the second circuit 17 I. The output of the second 17 circuit And is connected to the input "Start" shaper of 11 FID sampling intervals. The information outputs of the control panel 10 are connected to the data input bus 20 of the computing device 20. The output of the control panel 10 "KP" is connected to the first input "TPR1" of the computing device 7 VU, and the input "Start" of the control panel 10 is connected to the output of the first 16 circuit I. To the information the data output bus 19 is connected to the information inputs of the PID 11. The inputs of the "Reference frequency" PPK 10 and the PID 11 are connected to the output of the generator 12 of the reference frequency. The control output of the PID 11 is connected to the "Start" input of the sample-storage circuit 5 and to the input of the delay circuit 18, the output of which is connected to the "Start" input of the analog-to-digital 6 converter (ADC). The “Ready” output of the ADC 6 is connected to the second TPR2 input of the VU computing device 7, the information outputs of which via the address bus 8 are connected to the inputs of both decoders 14 and 15. The outputs of the first 14 decoder are connected to the control inputs of analog 3 of the AK switch, the first output of the second 15, the decoder is connected to the second input of the first 16 circuit And, and the second output of the second 15 decoder is connected to the first input of the second 17 circuit I.

 The proposed device operates as follows.

 The electrical parameters (alternating voltages and currents) of the control object 1 are supplied to the inputs of level 2 coordinators, which ensure that the input signal levels are brought to the level of permissible voltage of the AK 3 analog switch. As level coordinators, for example, resistive dividers for input voltages or shunts can be used and ballasts for currents using operational amplifiers. After the initial start-up, the computing device BU 7, in accordance with the functioning program laid down in it, is addressed to the first decoder 14 through the address bus 8, at the output of which a control code is generated, by which the analog switch AK 3 transfers the normalized voltage of one of the parameters to its information output. The control code AK 3 remains unchanged during the measurement cycle of the corresponding parameter.

 The low-pass filter f 4 suppresses the higher harmonics present in the input signals. Next, the filtered signal is fed to the pulse generator of frequency FIC 9, which generates unipolar rectangular pulses at the output with a frequency corresponding to the frequency of the input signal (see Fig. 2). The generator 9 pulses of the frequency of the FIC is made on an integral comparator of type 512CA3.

 The computing device VU 7 sets the address corresponding to the converter PPK 10 on the address bus 8, and generates a unit code via the information bus of the output 19, which is written to the control panel 10, thereby programming the control panel 10 to the measurement mode of one period. Then WU 7 is addressed to the second decryptor DSh2 15, setting the code on the address bus 8 that corresponds to the appearance of the signal at the first output of this decoder entering the input of the first circuit And 16. On the leading edge of the pulse from the output of circuit And, PPK 10 starts.

From this moment in the control panel 10, the pulses fill the reference frequency F _{et the} time interval corresponding to the period of the input signal and arriving in the form of a rectangular pulse from FIC 9.

 In the control panel 10, the information recorded in the control panel when it is programmed by the number of periods of the input signal is compared, and after the information matches the output of the control panel, a code is generated for the number of pulses of the reference frequency that fit on the period of the input signal, i.e. period code.

 After the conversion is completed and the information is ready for further processing, PPK 10 gives a signal about the end of the conversion "KP", received at the input TPR1 WU 7.

Upon receipt of the interrupt signal WU 7 in accordance with the processing routine of this interrupt is addressed to the decoder DSh2 15, resetting the signal at its first input; sets the address of the control panel on the address bus 8 and receives the input signal period code N _t on the data bus input 20 from the control panel

, где n - число отсчетов за период входного сигнала, хранится в памяти ВУ 7 в виде константы и выбирается в соответствии с теоремой Котельникова

>2f_max , где Т - период входного гармонического сигнала;
f_max - частота высшей гармоники в спектре этого сигнала.In WU 7 is the calculation of the sampling interval T _i , i.e. code of the number of pulses of the reference frequency falling within the sampling interval using the expression
T _i =

, where n is the number of samples for the period of the input signal, is stored in the memory of VU 7 as a constant and is selected in accordance with the Kotelnikov theorem

> 2f _max , where T is the period of the input harmonic signal;
f _max is the frequency of the highest harmonic in the spectrum of this signal.

 In this case, the error from the influence of higher harmonics when calculating the values of the measured parameters is zero. If the input signal contains a sufficiently wide range of harmonics, then the elimination of this error is provided by matching the frequency response of the filter Ф 4 with technically feasible n. Thus, when the frequency of the input signal changes, the number of samples n remains constant, and the sampling interval changes (see Fig. 3), so the value of the measured value does not depend on the change in the signal frequency (see formulas 2-4 below). On the contrary, if, with a change in the frequency of the signals, the sampling interval would remain constant, an error would appear, a decrease in which would require an increase in the number of samples for the period T of the input signal, which would lead to an increase in processing time and a decrease in the speed of measurement of parameters.

After calculating the sampling interval in VU 7, VU 7 is addressed to PID 11, setting the code of this device on address bus 8, and transmits a sampling code (T _i ) via information bus of output 19 to PID 11.

 Then WU 7 sets the address causing the appearance of the signal at the second output of the second decryptor DSh 15.

 The appearance of this signal together with the arrival of the next pulse from the output of the frequency divider to 2 DF 13 ensures the start of the PID 11: the signal at the output of the second circuit And 17 is fed to the PID input “Start”.

In PID 11, the information (F ₁ ) and reference frequency (F ₂ ) inputs (see Fig. 6) receive reference frequency pulses. After the number of incoming pulses coincides with the information in PID 11 during its programming, the output of the PID 11 generates a conversion end signal (Y _CR ), which starts the sampling and storage circuit and, with a delay, the ADC. Thus, the signal at the output of "Y _pr " PID is formed after each series of counted pulses, i.e. with sampling rate.

 The time delay is implemented using the R-C circuit. As a frequency divider by 2 - a chip type 56IE10. The readiness of the information at the output of the ADC 6 is accompanied by a signal "Ready", which is fed to the input TPR2 (interrupt requirement) of the VU 7 and transfers the VU 7 to the subroutine for reading information from the ADC 6. At the same time, the VU gives the address corresponding to the ADC address and receives it via the information bus water 20 discrete input value.

 With the arrival of the next sample in WU 7, the contents of the program counter of samples increases by one. After reaching the contents of the program counter of the specified value of the number of samples n, the WU is addressed to DSh 15 and resets the signal at its second output.

 As a result, n discrete values of the input signal taken per period are stored in the RAM of the computing device. Further processing in WU 7, these values are subjected in accordance with one of the algorithms (2-5) presented in the description of the application.

 Depending on the algorithm implemented programmatically in WU 7, the proposed device can calculate the average, mean-rectified, rms values of voltages and currents in three-phase systems of unstable frequency.

U_i,
(2)
U_ср.кв=

,
(3) где U_i - дискретные отсчеты входного сигнала (напряжение, токи).So for the average and rms values of the parameters, the calculation algorithms have the form
U _av =

U _i
(2)
U _sr =

,
(3) where U _i are discrete samples of the input signal (voltage, currents).

^Uν⁼

(4)
Результаты вычислений значений параметров объекта контроля 1 хранятся в соответствующих ячейках ОЗУ ВУ 7 и могут быть использованы в алгоритмах контроля за объектом/ которые реализует данное ВУ.In addition, it is possible to obtain the amplitudes of the harmonic components of the signals in accordance with the algorithm
U ₁ =

^U ν ⁼

(4)
The results of the calculation of the values of the parameters of the object of control 1 are stored in the corresponding cells of the RAM WU 7 and can be used in algorithms for controlling the object / which this WU implements.

The proposed device also allows you to eliminate the measurement error / associated with rounding or truncation of the calculation result in the WU according to the formula (1). This error appears due to the fact that when the frequency of the input signal N _t in the formula (1) changes, the value of the dmscritization interval T _i may turn out to be fractional. Then, when truncating the result of division, the sampling interval is taken to be equal to the integer part of the obtained number / when rounded, to the nearest integer.

n и

n при усечении и округлении соответственно. В частности, когда m = n, максимальная погрешность составит T_i или

, что соответствует смещению на эту величину последнего отсчета входного сигнала относительно точки окончания его периода (перехода через ноль) (см. фиг.4). Эта погрешность может быть устранена путем реализации вычисления значения измеряемого параметра с помощью формулы, учитывающей величину этого запаздывания.Since the division result is a code of the number of pulses of the reference frequency on the sampling interval /, the maximum error of the control signal to start the sampling-storage circuit 5 and ADC 6 can reach the period (when truncating) and half period (when rounding) of the pulse repetition of the reference frequency (T _et and T _et / 2). In this case, the control signal from PID 11 to receive the nth sample of the measured signal will be issued ahead of T _et ˙ n and n, respectively. Since T _et = T _i / m, where m is the number of pulses of the reference frequency in the sampling interval, the lead error will be

n and

n when truncating and rounding, respectively. In particular, when m = n, the maximum error is T _i or

, which corresponds to the offset by this value of the last count of the input signal relative to the end point of its period (transition through zero) (see figure 4). This error can be eliminated by implementing the calculation of the measured parameter value using a formula that takes into account the value of this delay.

,
(5) где Δt - расстояние от последнего отсчета до точки окончания периода измеряемого сигнала (см. Шалыгин В.И. Диссертация на соискание ученой степени к.т.н. с.68 "Цифровые методы измерения параметров для повышения эффективности контроля").So, when measuring the rms value in this case, you can use the following expression
U _sr =

,
(5) where Δt is the distance from the last reference to the end point of the period of the measured signal (see Shalygin V.I., Dissertation for the degree of candidate of technical sciences p.68 "Digital methods of measuring parameters to increase the effectiveness of control").

 It should be noted that the operation algorithm of WU 7 is an interrupt processing algorithm. In the period between the end of the next interruption and the beginning of the next WU 7 can perform work on other programs, taking into account their priority.

 Timing diagrams of the functioning of the PPK 10, PID 11, ADC 6 and WU 7 are shown in figure 3 of the materials.

 In FIG. 4 is presented, as an example, a fragment of a device diagram, revealing the blocks of the control panel 10, PID 11, ADC 6 and WU 7g and explaining the principle of operation of the device as a whole.

Here, to convert the period-code and to generate sampling pulses, we used a frequency-code 512PS11 conversion chip, which allows you to determine the number of pulses of the reference frequency supplied to its input F ₂ over a time interval equal to a number of signal periods arriving at the input F ₁ . The number of periods defining a time interval is programmed by WU 7.

So, for PPC 10 this number is constant and equal to one period of the input signal, and for PID 11, the information addressed from WU 7 is updated every time after WU 7 determines the sampling interval T _i (the number of pulses of the reference frequency for the sampling interval).

 For the analog-to-digital converter ADC 6 of the input signal, the chip 111ЗПВ1 is used, which is triggered by the "Start" signal initiated by the PID.

 As a buffer register for recording the result of analog-to-digital conversion, we used a 588IR1 multimode buffer register microcircuit. To organize the circulation and information exchange of the control panel, the FIF and the ADC with the VU, the address selector chip 588BT1 is used, which provides the pairing of these blocks with a common trunk like MPI according to GOST 26765.51-86 (OST 11.305.903-80). The microchip compares the codes of the address parcels with the address at its inputs A 4-12 and, if they coincide, initiates an exchange cycle.

 As a computing device of a control unit, for example, computers or microprocessor devices designed to work with a common trunk like MPI according to GOST 26755.51-86 can be used.

 Thus, the proposed device implements the measurement of average, rms and other values and voltages and currents and at the same time eliminates the error caused by the change in frequency due to the constancy of the number of samples n with a corresponding change in the sampling interval, and also improves the measurement speed due to the possibility to reduce the number of samples n and thereby reduce the processing time of the measurement algorithm.

Claims (1)

 DEVICE FOR MEASURING ELECTRICAL PARAMETERS, containing a serially connected monitoring object, matching devices for input measured parameters of the monitoring object and an analog switch, as well as a filter, a sample-storage element, an analog-to-digital converter, the information input of which is connected to the information output of the sample-storage element, a computing unit , address bus, control bus and data bus output and input data of the computing unit, the address input of the analog-to-digital converter inen with the address bus, the information outputs of the analog-to-digital converter are connected to the input of the computing unit via the data input information bus, characterized in that, in order to improve the accuracy and speed of measuring electrical parameters, a frequency pulse shaper, a period-code converter, a shaper are introduced into it sampling intervals, a reference frequency generator, a frequency divider by 2, two decoders, two AND elements and a delay element, moreover, the information output of the analogue switch is is Din through a filter with the input of the frequency pulse generator and the information input of the sample-storage element, the output of the frequency pulse generator is connected to the input of the period-code converter, the first input of the first element And and the input of the frequency divider by 2, the output of which is connected to the second input of the second element And the output of which is connected to the "Start" input of the shaper of the sampling interval, the information outputs of the period-code converter are connected to the information bus of the data input of the computing unit, information inputs The period-code converter is connected to the data bus of the data output of the computing unit, the output of the period-to-end converter-code converter is connected to the first input “Interrupt requirement” of the computing unit, and the “Start” input of the period-code converter is connected to the output of the first AND element, to the information bus of data output of the computing unit are connected the information inputs of the imager of sampling intervals, to the control bus input / output of the computing unit are connected control inputs of analog-to-digital about the converter, the sampling pulse generator and the period-code converter, the inputs “Reference frequency” of the period-code converter and the sampling interval generator are connected to the output of the reference frequency generator, the control output of the sampling interval generator is connected to the “Start” input of the sample-storage element and to the input a delay element, the output of which is connected to the "Start" input of the analog-to-digital converter, the "Ready" output of which is connected to the second input "Interrupt requirement" of the computing unit, whose information outputs are connected through the address bus to the inputs of both decoders and to the address inputs of the period-code converter, sampling interval generator, the outputs of the first decoder are connected to the control inputs of the analog switch, the first output of the second decoder is connected to the second input of the first element And, the second output of the second decoder connected to the first input of the second element I.

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