SU1410280A1 - Multichannel instrument for measuring analog signals - Google Patents

Abstract

The invention relates to a measurement technique and can be used to simultaneously measure and store various parameters of an object. The invention allows to increase the speed. This is achieved by the fact that in a multichannel signal meter containing comparators -2,3,4,5, triggers 9,10,11,12, priority block 14, memory block 16, digital-to-analog converter 24, counters 22, 23 pulses, AND elements 18, 19, the OR element 17, the delay element 15, the trigger 1, the channel fixing unit 8, the inverter 13, the pulse shaper 7, the code setting unit 25, the additional OR 21 element are entered. 1 Cp f-ly, 2 ill. S

Description

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11410280

The invention relates to electrical measuring equipment and can be used to simultaneously measure and store various parameters of an object.

The aim of the invention is to increase the speed.

FIG. 1 shows a functional diagram of the meter; in fig. 2 - time diagrams of the meter.

The device contains a trigger 1, comparators 2-5 (by number of channels), element 6 OR, pulse shaper 7, channel fixing unit 8, triggers 9-12 (by number of channels), inverter 13, priority block 14, delay element 15, storage unit 16, element 17 OR, elements 18, 19 AND, pulse generator 20, two elements 21 OR, counters 22 and 23 pulses, digital-to-analog converter 24, unit 25 code. Block

the maximum value in the counter 23 is from the setpoint 25. Thus, at the lower bits of the digital to analogue converter 24 connected to the outputs of the counter 23, the maximum value is set at the initial moment. Consequently, at the second inputs of the comparators 2-5, a sweep voltage is set in steps corresponding to one unit of counter 22 (minus the voltages of one unit of counter 23). Then, the pulse generated by the generator 15, having passed through, if the comparators did not operate, through the elements 38-41 of the block 14, goes to the element 15, from the output of which the generator 20 is restarted through the generator 20. In addition, from the output of the block 14 This pulse, elements 18 and 21, is fed to the input of the counter 22 and causes its contents to increment by one, i.e. at old20

I 8 contains elements 26-29 I (for the 25 bits of the D / A converter 24, connected with j channels), formers 30–33 by a counter 22. Therefore,

the maximum value in the counter 23 is from the setpoint 25. Thus, at the lower bits of the digital to analogue converter 24 connected to the outputs of the counter 23, the maximum value is set at the initial moment. Consequently, at the second inputs of the comparators 2-5, a sweep voltage is set in steps corresponding to one unit of counter 22 (minus the voltages of one unit of counter 23). Then, the pulse generated by the generator 20, having passed through, if the comparators did not operate, through elements 38-41 of block 14, goes to element 15, from the output of which, through element 17, the generator 20 is restarted. impulse, elements 18 and 21 are fed to the input of counter 22 and cause its contents to increment by one, i.e. at star0

pulses (by the number of channels), triggers 34-37 (by the number of channels). Block 14 contains elements 38-41 And (by the number of channels), elements 42-45 And (by the number of channels). The storage unit 16 contains the element 46 OR, the code converter 47, the delay element 48, the storage device 49.

On the timing diagram (figure 2) indicated: U - output signal of the GIF converter 24; I input voltage on; comparator 2; U is the voltage I of the input signal at comparator 3; and., - input voltage at comparator 4; i output signal of comparator 2; U is the output signal of comparator 3; output signal: on comparator 4; U - shaper output signal 7.

The device works as follows.

In the initial state the trigger 1 is in the state O. To start the meter on the bus, the trigger is given a pulse, which triggers trigger 1 to the state 1. Thus, the generator 20 is started through element 17. In addition, this pulse causes the initial state ( zero) trigger: 34-37 of block 8, zeroed the counter 22 and, through an additional element 21, pre-sets

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the trailing voltage at the second inputs of the comparators 2-5 will increase in large steps corresponding to the unit of counter 22 until the sweep voltage exceeds the value of the signal of one or several channels. In this case, one or more comparators 2-5 and the signals from their outputs through elements 26-29 of block 8 and element 6 prohibit further passage of pulses through element 18 to counter 22 and allow them to pass through element 19 to counter 23, which is is an accurate count counter. Thus, I deployed

The applied voltage begins to decrease stepwise with the magnitude of the step corresponding to the unit of counter 23, i.e. unit of lower rank of this meter. As soon as the sweep voltage again becomes less than the signal of one of the channels, i.e. triggered at the large step of counter 23, which is a coarse counter, the comparator of this channel will again be set to 0. (figure 2), so by the decay of this signal, the corresponding driver 30-33 will generate a pulse, which will set to 1 the corresponding trigger 9-12 and 34-37 (figure 1). Triggered one or more triggers 34-37

block 8 is turned off by means of elements 26-29 of the same block, their corresponding comparators so that they do not affect the further operation of element 6, which actually determines whether at least one uncommitted parameter exists in this rough counting stage. In addition, triggered 9-12 triggers break the pulse generator circuit 20 through elements 38-41 to change the state of counters 22 or 23 and turn on one or more elements 42-45 through which generator 20 pulses go to memory 16 where by means of the element 46 a pulse is written to the memory device (memory) 49, and using the converter 47, the number of the activated channel is generated. This number is the address of the memory cell 49 where the value of this parameter is stored. Pulse passing through one of the elements 42-45 returns the corresponding trigger 9-12 E to its original state, thereby restoring the path of the clock pulses through elements 38-41. Thus, until all the channels triggered at this exact reading step are locked in the memory 49, the clock pulses will go through the element 48 to repeat

starting generator 20 without causing an analog-to-digital converter.

sweeping voltage change. In this case, the values of the channels in turn determined by the configuration of block 14 will be recorded in the memory 49.

When the channel that triggered the exact countdown at this step has been detected, the pulse passing circuit through elements 38-41 is restored (all triggers 9-12 are zeroed) and the further reduction of the developing voltage will continue in small steps until - the last channel that has been triggered at this coarse count stage will be registered. At this moment, the output of element 6 establishes the signal level, which prohibits the passage of pulses through element 19 to meter 23 and restores their passage through element 18 and the first element 21 to counter 22. In addition, the signal from output of element 6 decreases the driver 7 produces a pulse, which, through an additional element 21, causes a preset of the maximum value to counter 23. (preparation for operation at the next stage), and through element 21 increases the content of counter 22 by one. Next, the meter continues to scan in range in large steps, one or more channels will not work again, and then the described procedure will be repeated. , or, if all the channels are fixed, before the counter 22 overflows, the overflow signal from its output zeroizes trigger 1 and the measurement cycle ends there.

Claims (2)

Invention Formula one . A multichannel analog signal meter containing a priority block, a storage block, an analog-to-digital converter, a pulse generator, two pulse counters, a delay element, three OR elements, a trigger, two AND elements, a group of n triggers and n comparators, where n is the number of measurement channels, the first input of each comparator is the corresponding input bus, the second inputs of all n comparators are combined and connected to the output the higher bit inputs of which are bit-wise combined with the first information inputs of the storage unit and connected to the corresponding direct outputs of the first pulse counter, the lower ones: - 1X 1 bits of the digital-to-analog converter are combined with the second information inputs of the storage block and connected to the straight lines the outputs of the second pulse counter; the inverse output of the first pulse counter is connected to the input of the installation in O of the trigger, the installation of which 1 is the Start bus, the counting input of the first pulses are connected to the output of the first OR element, the first input of which is connected to the output of the first element AND, the subtractive input of the second pulse counter is connected to the output of the second element AND, the first inputs of the first and second elements And, the input of the delay element are combined and connected to the first output of the priority block, the output of the delay element is connected to the first input of the second IL, the second input of which is connected to the output of the storage unit, the third input is connected to the inverse output of the trigger, and the output of the second IPI element is connected to the input of the pulse generator, the output of which is connected to the control the input of the priority block, the second outputs of which are connected to the corresponding address inputs of the storage unit and to the corresponding inputs of the installation in the O n-flip-flops of the group, direct and inverse Vrapsody n-flip-flop Group s are connected to the corresponding information inputs of a priority block, characterized in that, in order to increase speed, a pulse driver, an inverter, an additional OR element, a current setpoint device and a channel fixation unit, the first inputs of which are connected to the corresponding outputs of the n-comp the first outputs are connected to the installation inputs in 1 of the corresponding n-flip-flops of the group, the second outputs are connected with the corresponding codes of the third OR element, the output of which is connected to the input of the T2L form I pulses, the second input of the second element and (and the input of the inverter whose head is connected to the second input of the main element I, the output of the pulse former connected to the second input of the first element HJE l and the first input of the additional element MJM, the second input of which is combined with the input Resetting the first pulse counter, the installation input into 1 trigger and the second input of the channel fixing unit, the output of the additional OR element is connected to the data recording input of the second counter I1 pulses, the preset input of which is single with exit for code output. 2. The meter according to claim 1, which is based on the fact that the channel fixing unit is made on the n elements of the I, n-formers of pulses and p-flip-flops, inverse output of an ad i-th trigger, where i 1,2 ,, .., p, is connected to the first input of the i-ro element And, the second inputs of the n elements And are the corresponding first inputs of the fixation unit channels, the output of each i-ro element I is connected to the input of the i-ro pulse generator and is the corresponding second output of the channel fixing unit 30 35 The output of each i-ro pulse generator is connected to the installation input to 1 i-ro trigger and is the corresponding first output of the channel fixing unit, the second input of which is the installation inputs to the O n-flip-flops. cpue.Z