RU1778767C - Device for compiling and transmitting of messages - Google Patents

Abstract

The invention relates to discrete information transmission systems and can be used in remote control / shadow devices as a remote control command generator. The purpose of the invention is to increase the information content and functional reliability of the device. The device for generating and transmitting a message comprises a clock pulse generator 1, a command input unit 2, an address code generator 3, a parallel to serial code converter 4, a phased manipulator 5, Schmitt triggers 6, 7, RS-flip-flop 8, binary counter 9, multiplexer 10. In this device, the same command input unit using / - -, W is available both in the address setting mode and in the command transmission mode, and there is no need Mosti when specifying a unique address in a decimal senior discharge write address D, and by setting a two digit address to carry out a set of addresses in the reverse order. In transmission mode, the code sequence, including the identifiers of the start of the code sequence, the address code of the external device and the command code, is transmitted once, no matter how long it is pressed. Retransmission is performed by pressing the key again. The device allows accessing 100 external devices and transmitting up to 32 control commands. In this case, the operator’s productivity, information content and reliability of the transmission will be higher than that of existing devices for generating and transmitting messages. The functional reliability of the proposed device is also higher than that of existing devices for generating and transmitting messages, because when the wrong address is dialed, it is possible to reset the memory registers to their initial state, and no signal will be output. 1 C.p. f-ls, 1 ill. SB with XI x | oo xj o x |

Description

The invention relates to discrete information transmission systems and can be used in remote control devices as a remote control command generator.

A device is known which solves the problem of generating telecontrol commands. This device contains a block of control keys, a block of memory elements, a pulse shaper, a switch, a decoder, a parallel to serial code converter, a code control unit, a code adjuster, a multiplexer, a counter, triggers, AND elements, OR elements, or identification of independent control rooms.

The disadvantage of this device is that when accessing a large number of control objects, only up to 8 types can be transferred; omand.

Another device for generating and transmitting messages is known which solves the same problem. It contains a generator, clock pulses, a block for manually typing a message format, a counter, a multiplexer, a reader block, a signal converter, a block for manually dialing a pulse frequency coefficient and a pulse frequency divider.

A disadvantage of the device is the presence of two manual dialing units: a message format and a pulse frequency coefficient, as well as insufficient information content of the device. In addition, the device transmits continuously when there is a supply voltage.

The closest to the invention in technical essence and the achieved result is the control point in the remote control device. The device for generating and transmitting a message comprises an instruction input unit, an encoder, OR elements, and AND elements, a multiplexer, an address code generator, a binary counter, and a clock generator. The outputs of the group of command blocks are connected to the information inputs of the multiplexer, the output of which is connected to the information input of the address code generator, a binary counter whose outputs are connected to the inputs of the address code generator, and a clock.

The address code generator comprises two memory registers, a counter and a decoder, as well as a display unit and a switch.

The device allows using the encoding of transmitted information to significantly increase the number

executive elements of the control object.

The disadvantage of this device is that for each bit of the address code

its transmission line is required. In addition, the device has insufficient information content, due to the fact that in addition to the address code, no information is transmitted, as well as when dialing a two-digit address

0 of the control object, it is necessary to set in the reverse order, i.e. first units, and then dozens if units are written to the first memory register and dozens are written to the second.

5 If tens are recorded in the first memory register and units are written in the second memory register, then when writing the unique address of the control object, the value O is first written to the bit

0 tens, and then units are recorded. Such a recording is inconvenient for the operator and reduces his productivity.

The functional reliability of the known 5th device is low, because if you accidentally press several buttons at the same time, the binary decimal code at the output of the encoder will not be predictable. The device does not provide installation in the initial state when the button is mistakenly pressed. For this, it is necessary to perform manipulations with a further set of address and a fixed executive digit, as a result of which a control is formed

5, the signal for the switch and incorrect information recorded in the memory registers will be sent via the communication line to the inputs of the decoder of the control object, which will lead to a false positive

0 actuator.

The aim of the invention is to increase the information content and functional reliability of the device,

This goal is achieved by the fact that in the device for forming and transmitting a message containing a command input unit, the group outputs of which are connected to the information inputs of the multiplexer, the output of which is connected to the information

0, the input of the address code generator, the binary counter whose outputs are connected to the inputs of the address code generator group, and the clock generator, a parallel code converter

5 serial, phase-shifter shaper RS-flip-flop and Schmitt flip-flops, the inputs of which are connected respectively to the first and second outputs of the device operation mode setting, the outputs - with the corresponding inputs

a trigger, the first and second outputs of which are connected respectively to the first and second inputs of the parallel code to serial converter, the information output of which is connected to the information input of the phase manipulator, the output of which is the output of the device, the output of the clock generator is connected to the clock inputs of the address code generator, a parallel code to serial converter and a phase-shifted code generator and with a counting input of a binary counter, you ode which are connected to the control inputs of the multiplexer and to the inputs of the first transducer group parallel to serial inputs of the second group are connected to the output of the address code. The control output of the parallel-to-serial code converter is connected to the control input of the phase-shifted code generator. The output of the second Schmitt trigger is connected to the reset input of the binary counter and to the first control input of the address code generator, the second control input of which is connected to the second output of the RS trigger. The output of the multiplexer is connected to the counter enable input of the binary counter and to the control input of the parallel to serial converter.

In addition, the address code generator contains a D-trigger, OR-NOT elements, a NOT element, shift registers, and a divider counter, the zero-bit output of which is connected to the zero-setting input of the D-trigger, the output of which is connected to the counter account enable input -divider, the output of the first and third bits of which are connected respectively to the first and second inputs of the first OR-NOT element, the output of which is connected to the clock input of the first shift register and through the element is NOT connected to the counting input of the divider counter and the first input of an OR-NOT element, the output of which is connected to the clock input of the second shift register, the shift input of which is connected to the high-order output of the first shift register, whose control input and the second input of the second OR-NOT element are connected to the last output of the divider counter, whose reset inputs and shift registers are the first control input of the address code generator. The D-input of the D-flip-flop is the information input of the address code generator, the setup input 1 is the second control input, the D-trigger signal input and the third input of the first OR-NI element are clock inputs of the address code generator. The information inputs of the first shift register are the inputs of the address code generator group. The outputs of the shift registers are the outputs of the address code generator, and the information and control inputs of the second shift register are connected to the zero potential bus. The design of the device allows to increase the information content and reliability of the message. This is done at the expense of the organization concerned.

5 switching the address setting mode and command transmission.

The drawing shows a functional diagram of a device for generating and transmitting a message.

The device for generating and transmitting a message comprises a clock generator 1 (GTI), an instruction input unit 2, an address code generator 3, a parallel code converter 4

5 serial, shaper 5 of the phase-shift code, Schmitt triggers 6, 7, H5 trigger 8, binary counter 9, multiplexer 10.

Mode switching outputs

0 setting the address, and transmitting the command input unit 2 through the corresponding Schmitt triggers 6 and 7 are connected to the inputs of the RS-trigger 8, the first and second outputs of which are connected respectively to the first and second inputs of the parallel code converter 4 to serial, the information output of which is connected to information input of the shaper 5 of the phase-shift code, the output of which is the output of the device. The output of the clock generator 1 is connected to the clock inputs of the address code generator 3, the parallel code converter 4 to serial and the generator

5 5 phase-shift code and with the counting input of the binary counter 9. The outputs of the binary counter 9 are connected to the control inputs of the multiplexer 10, to the inputs of the first group of the converter 4

0 parallel code to the serial and to the inputs of the group shaper 3 address code. The outputs of the address code generator 3 are connected to the inputs of the second group of the parallel code converter 4 and sequential. The control output of the parallel-to-serial code converter 4 is connected to the control input of the phase shifter 5, the output of the second Schmitt trigger 7 is connected to the reset input of the binary counter 9 and to the first control input of the address code generator 3. The second control input of the address code generator 3 is connected to the second output of the RS flip-flop 8. The output of the multiplexer 10 is connected to the counter enable input of the binary counter 9 and to the control input of the parallel code converter 4 to serial. The outputs of the group of the command input unit 2 are connected to the information inputs of the multiplexer 10, the output of which is connected to the information input of the address code generator 3.

Shaper 3 of the address code contains a D-trigger 11, a counter-divider 12 (for example, a counter-divider by 8), the first element OR NOT 13, the element NOT 14, the first shift register 15, the second shift register 16, the second element OR-NOT 17. The zero-bit output of the counter-divider 12 is connected to the zero setting input of the D-trigger 11, and the counter enable input of the counter-divider 12 is connected to the output of the D-trigger 11. The outputs of the first and third bits of the counter-divider 12 are connected respectively to the first and the second inputs of the first element OR NOT 13, the output of which is connected to the clock the input of the first shift register 15 and through the element NOT 14 is connected to the counting input of the counter-divider 12 and the first input of the second OR-NOT 17. The clock input of the second shift register 16 is connected to the output of the second OR-NOT 17 element, and its shift input is connected to the high-order output of the first shift register 15. The second input of the second OR-NOT element 17 and the control input of the first shift register 15 are connected to the last output of the divider counter 12. The reset inputs of the first and second, shift registers 15 and 16, respectively, and the counter divider 12 are combined and are the first control input shaper 3 address code. The D-input of the D-flip-flop 11 is the information input of the address code generator 3, its setting input 1 is the second control input of the address code generator 3. The clock input of the D-flip-flop 11 and the third input of the first OR-NOT element 13 are clock inputs of the address code generator 3. The information inputs of the first shift register 15 are inputs of the address code generator 3 group. The outputs of the shift registers 15 and 16 are the outputs of the address code generator 3. The control and information inputs of the second shift register 16 are connected to a zero potential bus.

The correct operation of the shift registers 15 and 16 is visualized on the actuators of the transceiver system.

The parallel-to-serial code converter 4 contains a first AND-NOT 18 element, a binary counter 19, a second AND-NOT 20 element, an OR-NOT 21 element, an NOT element 22, a D-trigger 23, a multiplexer 24. The counter enable input of the binary counter 19 is connected to the direct output of the D flip-flop

0 23, the input of the initial installation of the binary counter 19 is connected to the output of the first AND-NOT 18 element, and the outputs of the binary counter 19 are connected to the control inputs of the multiplexer 24. An output older than the 5th (fifth) bit of the binary counter 19 is connected to the reset input D- trigger 23 and the first input of the second AND-NOT element 20, the output of which is connected to the first input of the first AND-NOT element 18. Clock input

0 D-flip-flop 23 is connected to the output of the element NOT 22, the D-input of the D-flip-flop is connected to the output of the element OR-NOT 21, and the inverse output of the D-flip-flop 23 is the control output of the parallel code converter 4

5 in serial. The output of the multiplexer 24 is the information output of the parallel to serial converter 4. The counting input of the binary counter 19 and the input of the element HE 22 are combined and are the clock input of the parallel to serial converter 4. The first input of the OR-NOT element 21 and the second input of the second AND-NOT element 20 are also combined and are the control input 5 of the parallel-to-serial converter 4. The second inputs of the element OR-NOT 21 and the first element AND-NOT 18 are respectively the first and second inputs

0 converter 4 parallel to serial code. The information inputs of the first and second groups of multiplexer 24 are the inputs of the first and second groups of the parallel to serial code converter 4, respectively.

 The phase-shifted code generator 5 is intended to convert a binary sequential code into a self-synchronizing phase-shifted code. It contains the first AND-NOT element 25. The NOT-element 26, the second AND-NOT element 27 and the OR-NOT 28 element. The input of the NOT-26 element is connected to the output of the AND-NOT 25 element. The outputs of the NOT 26 element and the AND-NOT 27 element connected respectively to the first and second inputs of the element OR-28, the third input of which is the control input, and its output is the output of the shaper 5 phase-manipulated code. The first and second inputs of the first and second AND-NOT elements 25 and 27 are combined in pairs and are respectively the information and clock inputs of the phase shifter 5.

The RS-flip-flop 8 through the edge shapers, the Schmitt triggers 6 and 7, at the inputs of which a high potential is supplied from the power supply via resistive loads 29 and 30, set either the address setting mode or the command transmission mode.

The device operates as follows.

When the power is turned on, the clock generator 1 starts to operate. Using the binary counter 9, the inputs of the multiplexer 10 are scanned. Before entering the address, the operator must press the key Set address of the command input unit 2. The RS flip-flop 8 will be set to a state in which its second output will have a logical state O, which will be input to the setup 1 of the D-flip-flop

11and unlocks the circuit of the shaper 3 address code. From the second output of the RS-flip-flop 8, the state of logical O also arrives at the second input of the AND-NOT element 18 and sets the binary counter 19 to its initial state. On the other output of trigger 8 there will be a logical state 1, which through the element И И NI 21 will go to the D-input of the D-flip-flop 23 The state of the logical О from the direct output of the D-flip-flop 23 goes to the counter enable input of the binary counter 19 and blocks its operation The state of the logical 1 inverse output of the D-flip-flop 23 enters the third input of the element AND L AND-NOT 28 and blocks the output of the device.

Thus, when the Set address of the command input unit 2 key is pressed, the transmission mode is locked and the address setting mode of the external device is set.

When you press the button Specify the address of the command input unit 2, the counter-divider 12, the shift registers 15 and 16 and the binary counter 9 are set to the initial state, while the outputs of the shift registers 15 and 16 display zeros and the zero bit at the output counter-divider 12 appears 1, which is fed to the zero-setting input of the D-flip-flop 11 and sets it to the logical state O, which sets the counter-divider 12 to the counting mode. Front of the first pulse of the generator 1 clock pulses counter-divider

12 changes its state: at the output of the zero bit, a logical O appears, and at the output of the first bit appears

logical state 1, which blocks the counting input of the counter-divider 12 through the element OR-NOT 13. Logical state 1, which is received from the output of multiplexer 10, is recorded in the D-trigger 11. When you press any key with the digital index of command input block 2 at the output of the multiplexer 10, a logical O value is displayed that blocks the binary counter 9, the output of which currently contains the binary decimal code of the pressed key. Logical O is written to D-flip-flop 11. A differential at the output of D-flip-flop 11 to O will change the state

5 of the counter-divider 12, moving the logical 1 to the output of its next bit, while the counting input of the counter-divider 12 and the clock input of the first shift register 15 are unlocked by the next pulse

0 of the clock generator 1, the pressed key code is written to the shift register 15, and the counter-divider 12 again changes its state and blocks the counting input. After releasing the key, trigger 11 will be written to trigger D 11 again. If the address of the external device is a single digit and no further dialing is required, press the Transfer key of command input unit 2. When dialing a two-digit address after the value of tens of decimal address codes has been entered, it is necessary to press the key a second time corresponding to the value of units of decimal address codes. In this case, along the edge of the clock pulse, a logical O will be recorded in the D-trigger 11. Counter-divider 12 will change its value and unlock the counting input. At the last output of the counter-divider 12, the state

0 logical O, which will transfer the shift register 15 to the shift mode (the shift register 16 is constantly set to the shift mode) and unlocks the clock input of the shift register 16, allowing the passage of clock

5 pulses. The state of logical O at the last output of the counter-divider 12 will be saved B for the duration of 4 clock pulses, with which the contents of register 15 shift - value

0 previous press - moves to shift register 16 - high order bit of the external device address. On the edge of the fifth clock pulse, the counter-divider 12 is set to its initial state (level

5 logical 1 at the output of the first bit), while at the last output of the counter-divider 12, logical 1 will be set, which will shift the shift register 15 from the shift mode to the parallel recording mode, and with the help of the trailing edge of the fifth pulse

a value shift will be written to the register 15 from the output of the binary counter 9 corresponding to the binary decimal code of the second key pressed.

After recording the address, it is necessary to press the transfer key of the command input unit 2, while the RS flip-flop 8 changes its state, blocks the address code generator 3 circuit and unlocks the parallel-to-serial converter 4 circuit, i.e. set the transmission mode.

Any subsequent press of the information key will transmit the command.

When you press the key of the input block 2 at the output of the multiplexer 10, a logical O level appears, which goes to the input of the OR-NOT 21 element, at the second input of which there is a logical O from the output of the RS-trigger 8. At the output of the OR-NOT 21 element logic level 1 is recorded, which is recorded by the pulses of the clock generator 1 arriving at the D-flip-flop 23 and will enable the counting of the binary counter 19. At the same time at the inverse output of the D-flip-flop 23, logic О is enabled, which will allow the transfer of 5 phase manipulator from the output nnogo code. The binary counter 19 will sequentially change its state and sequentially connect to the output of the multiplexer 24 the signal levels present at its input: the first three levels (O, O and 1), which determine the beginning of the pulse sequence, address code, command code. With a 16th pulse cut in the high order of the binary counter 19, logic 1 appears and the D flip-flop 23 is reset to the O state, while the counter of the binary counter 19 is disabled and transmission of the phase-shifted code from the generator 5 is prohibited. Logical level 1 from the output of the high order bit (5 bits) of the binary counter 19 is also supplied to the first input of the NAND 20 element, at the other input of which there is a level of logical O from the output of multiplexer 10.

In this state, the parallel-to-serial code converter 4 will remain until the key is released. When you release the keys at the output of the AND-NOT element 20, the logic level O is reached, which, through the AND-NOT element 18, sets the binary counter 19 to its original state. In this way, a 16-bit burst in the phase-shifted code is output from the output of the device.

In this device, the same command input unit is used as in

when setting an unambiguous address in the high decimal digit of the address, write O, and when specifying a two-digit address, dial the address in the reverse order. In transmission mode, the code sequence, including the identifiers of the start of the code sequence, the address code of the external device and the command code, is transmitted once, no matter how long the key is pressed. Retransmission is performed by pressing the key again. The device allows accessing 100 external devices and transmitting up to 32 control commands. In this case, the operator’s productivity, information content and reliability of the transmission will be higher than that of existing devices for generating and transmitting messages.

The functional reliability of the device is also higher than that of existing devices for generating and transmitting messages, since when typing the wrong address, it is possible to reset the memory registers to their original state, and no signal will be output.

The device will find application in remote control systems for devices that are in conditions hazardous to human health and life, or located in hard-to-reach places.

Claims (1)

1. A device for generating and transmitting a message containing a command input unit, the group outputs of which are connected to the information inputs of the multiplexer, the output of which is connected to the information input of the address code generator, a binary counter, the outputs of which are connected to the inputs of the address code generator, and a clock characterized in that, in order to increase information content and functional reliability, a parallel code to serial converter, a phase shifter, is introduced into the device pulsed code, RS-trigger and Schmitt triggers, the inputs of which are connected respectively to the first and second outputs of the device operation mode, their outputs are with the corresponding inputs of the RS-trigger, the first and second outputs of which are connected respectively to the first and second inputs of the parallel code converter in serial, the information output of which is connected to the information input of the phase shifter, the output of which is the output of the device, the output the clock generator is connected to the clock inputs of the address code generator, the parallel code converter to serial and the phase-shifted code generator and to the counter input of the binary counter, the outputs of which are connected to the control inputs of the multiplexer and to the inputs of the first group of the parallel code converter to serial, the inputs of the second the groups of which are connected to the outputs of the address code generator, the control output of the parallel to serial converter is connected to the control With the input of the phase shifter driver, the output of the second Schmitt trigger is connected to the reset input of the binary counter and to the first control input of the address code generator, the second control input of which is connected to the second output of the RS trigger. the multiplexer output is connected to the enable input of the counter of the binary counter and to the control input of the parallel to serial converter. 2, Device pop. 1, characterized in that the address code generator comprises a D-trigger, an OR-NOT element, an NOT element, shift registers and a divider counter, the zero-bit output of which is connected to the zero-setting input of the D-trigger, the output of which is connected to the counter enable input of the divider counter, the outputs of the first and third bits of which are connected respectively to the first and second inputs of the first OR-NOT element, the output of which is connected to the clock input of the first shift register and through the element is NOT connected to the counter input of the counter divider and the first input of the second the OR-NOT element, the output of which is connected to the clock input of the second shift register, the shear input of which is connected to the high-order output of the first shift register, the control input of which, the second input of the second OR-NOT element, are connected to the last output of the divider counter, reset inputs which and shift registers are the first control input of the address code generator, D-input The D-flip-flop is the information input of the address code generator, the setup input 1 is the second control input, the D-trigger clock input and the third input of the first element OR are NOT clock inputs of the address code generator, the information inputs of the first shift register are group inputs the address code driver, the outputs of the shift registers are the outputs of the driver, the information and control inputs of the second shift register are connected to the zero potential bus.