RU128045U1 - FREQUENCY SYNTHESIS USING A DIGITAL COMPUTER FREQUENCY SYNTHESIS - Google Patents

Abstract

1. A frequency synthesizer using a digital computational frequency synthesizer, comprising a digital computational frequency synthesizer (CVS), a first filter and a first phase locked loop (PLL), consisting of a series-connected phase detector (PD), a filter and a voltage controlled oscillator (VCO) ), the output of which is the output of the first PLL and connected through the divider to the PD input, characterized in that a second, third and fourth PLL are introduced, similar to the first PLL, and the output of the second PLL connected to the input of the CVC, the outputs of the third and fourth PLLs are connected to the corresponding inputs of the switching device, the output of which is connected to the corresponding input of the mixer, the output of which is the output of the synthesizer, while the output of the first PLL through the second filter is connected to another input of the mixer, in addition, the inputs of the second, third and fourth PLLs are connected and are the input for the signal of the reference oscillator. 2. The synthesizer according to claim 1, characterized in that the mixer is configured to convert up and convert down. The synthesizer according to claim 1, characterized in that the second PLL is performed with the function of a cleaning ring of the reference signal for the DAC, and the third and fourth PLLs with the function of increasing the overlapping frequency range.

Description

The utility model relates to frequency synthesizers, in particular, using a combination of a digital computer frequency synthesizer (DAC) with several phase locked loop (PLL) schemes.

Known synthesizers using a digital synthesizer with direct frequency synthesis and the PLL are described in US Pat. PLL with a sharp threshold limiter. " A frequency synthesizer, launched by a digital direct synthesizer with a PLL, can synthesize signals with high frequency resolution and high spectral purity. The PLL, designed with a narrow frequency band, suppresses noise in the reference signal of a digital synthesizer with direct frequency synthesis and produces a signal with high spectral purity. The disadvantages of the known synthesizers include an increase in the installation time of the frequency.

The closest in technical essence to the proposed one is a frequency synthesizer according to the patent of the Russian Federation 2176431, H03L 7/16, adopted as a prototype.

The prototype device contains a series-connected (DAC), a digital-to-analog converter (DAC), a filter and a divider, the output of which is connected to the input of the PLL, the output of which is the output of the device. In this case, the PLL consists of a series-connected phase detector (PD), a filter and a voltage controlled oscillator (VCO), the output of which is the output of the PLL and is connected through the divider to the input of the PD.

The phase detector serves as a comparator means for comparing the reference signal supplied from the DAC (digital synthesizer with direct frequency synthesis) circuits with the obtained after division of the output signal of the PLL. The phase detector responds to the difference in the frequencies of the reference signal and the phase-locked PLL output signal to generate a frequency control signal whose voltage level is proportional to the frequency difference of the compared signals.

The filter serves as a filter for the adjustment control signal. It receives and filters the frequency control control signal and provides a control signal for supplying a voltage controlled oscillator to the control input.

The VCO is designed to generate the PLL output signal in response to a generator control signal. In particular, the VCO changes the frequency of the output signal of the PLL in response to a change in the voltage level of the input control signal of the generator. A VCO can be a high-quality oscillator, such as a quartz oscillator, to meet additional requirements for spectral purity.

The divider is connected to the output of the VCO to receive the output signal of the PLL. The divider serves as a PLL splitter, which receives the output signal of the PLL and generates a divided signal corresponding in frequency to the output signal divided by N. The divided signal is fed to the input of the phase detector and has a frequency equal to or close to the input value. A change in the N value of the divider actually increases the difference in frequency perceived by the phase detector and causes a change in the final output frequency. The resulting output signal of the PLL generator is a spectrally pure reference signal whose frequency increases in proportion to the value N of the divider.

It should be noted that the DAC is located outside the DAC, but in one of the other design options, the digital-to-analog converter is located inside the DAC.

The characteristics of the PLL circuit of the prototype device are influenced by several factors, namely: the frequency of the reference signal, the value of the divider necessary to divide the output frequency up to the reference frequency, and the frequency bandwidth of the filter of the PLL. The frequency of the reference signal affects the frequency resolution or step size of the PLL, that is, the lower the reference frequency, the higher the frequency resolution. The magnitude of the PLL divider has a large effect on the noise performance of the PLL. As such, any phase noise or spurious noise in the reference frequency will appear at the output of the PLL, having its original value multiplied by the divider of the PLL. The filter bandwidth of the PLL filter, which is usually 5 to 10% of the reference frequency or less, affects the speed at which the PLL can be set to a new frequency.

Thus, the narrower the filter bandwidth, the slower the PLL will be able to settle at the new frequency.

Another disadvantage of the prototype device is the inability of the PLL to suppress a wide range of spurious signals present in the reference signal.

The task is to obtain a signal of high spectral purity and increase the speed of the frequency synthesizer.

To solve the problem, a frequency synthesizer containing a digital computer frequency synthesizer (CVS), a first filter and a first phase-locked loop (PLL), consisting of a series-connected phase detector (PD), a filter and a voltage-controlled generator (VCO), output which is the output of the first PLL and connected through the divider to the PD input, according to the utility model, the second, third and fourth PLLs are introduced, similar to the first PLL, and the output of the second PLL is connected to the input of the CVC, the output The third and fourth PLLs are connected to the corresponding inputs of the switching device, the output of which is connected to the corresponding input of the mixer, the output of which is the output of the synthesizer, while the output of the first PLL through the second filter is connected to another input of the mixer, in addition, the inputs of the second, third, and the fourth PLL are connected and are the input for the signal of the reference generator.

Figure 2 presents a diagram of the proposed device, where it is indicated:

1 - digital computer frequency synthesizer (DAC);

2, 4 - the first and second filters;

3, 7, 8, 9 - the first, second, third and fourth PLL;

5 - mixer;

3.1, 7.1, 8.1, 9.1 - phase detectors of the corresponding PLL;

3.2, 7.2, 8.2, 9.2 - filters of the corresponding PLL;

3.3, 7.3, 8.3, 9.3 - voltage-controlled generators (VCOs) of the corresponding PLLs;

3.4, 7.4, 8.4, 9.4 - frequency dividers of the corresponding PLL;

6 - switching device.

The proposed device contains a series-connected second PLL 7, CVC 1, a first filter 2, a first PLL 3, a second filter 4, the output of which is connected to the corresponding input of the mixer 5, the output of which is the output of the frequency synthesizer. In addition, the outputs of the third 8 and fourth 9 PLLs are connected to the corresponding inputs of the switching device 6, the output of which is connected to the corresponding input of the mixer 5. In this case, the inputs of the second 7, third 8 and fourth 9 PLLs are interconnected and are the input for signals from reference generator.

All PLLs are similar in constructive construction to the first PLL, which is used in the prototype synthesizer, and differ only in operating modes.

The first PLL 3 consists of a series-connected PD 3.1, a filter 3.2 and a VCO 3.4 whose output is the output of the PLL and through a divider 3.4 is connected to the input of the PD 3.1, which is the input of the PLL 3.

The proposed synthesizer works as follows.

The reference signal of variable frequency (from the reference generator) is generated in digital form, fed to the second 7, third 8 and fourth 9 of the PLL, in which the signal of the changing frequency is filtered.

The analog signal generated by DSP 1 is the reference frequency source for the first PLL 3. The reference signal from a digital synthesizer with direct frequency synthesis (DSP 1) is a digitally converted periodic signal whose frequency can be adjusted within a given frequency bandwidth. Such a signal may contain parasitic components due to quantization and truncation errors, as well as noise due to the phenomena of chaotic thermal motion of electrons and semiconductor phenomena.

The output signal of the generator 7.3 is the output signal of the second PLL 7 and is also fed back to the input of the divider 7.4. The output of the divider 7.4 is connected to another input of the phase detector 7.1. The second PLL 7 is designed to clean the input signal of the DAC 1. Phase detector 7.1 serves as a means for comparing the reference signal with the output signal obtained after dividing the second PLL 7. The phase detector 7.1 responds to the difference in the frequencies of the reference signal and the output signal of the second circuit PLL 7 for generating a control signal for controlling the frequency, the voltage level of which is proportional to the frequency difference of the compared signals.

Filter 7.2 serves as a filter for the control control signal. It receives and filters the control signal for adjusting the frequency and generates a control signal for applying to the control input of the generator controlled by voltage 7.3.

The generator 7.3 is designed to generate the output signal of the second PLL 7 in response to the control signal of the generator. In particular, the generator 7.3 changes the frequency of the output signal of the second PLL 7 in response to a change in the voltage level of the input control signal of the generator. Oscillator 7.3 can be a high-quality oscillator, such as a crystal oscillator, to meet additional requirements for spectral purity.

Divider 7.4 is connected to the output of generator 7.3 to receive the output signal of the second PLL 7. The divider 7.4 serves as dividing means of the PLL 7, which receives the output of the PLL 7 and generates a divided signal corresponding in frequency to the output signal divided by N. Divided the signal is fed to another input of the phase detector 7.1 and has a frequency equal to or close to the input value. A change in the value N of the divider 7.1 actually increases the difference in frequency perceived by the phase detector 7.1 and causes a change in the final output frequency. The resulting output signal of the generator 7.3 of the first PLL 7 is a spectrally pure reference signal whose frequency increases in proportion to the value N of the divider.

The principle of operation of the components of the third 8 and fourth 9 PLLs is similar to the principle of the first PLL 3. The second PLL 7 has the function of a cleaning ring of the reference signal for DAC 1. The third 8 and fourth 9 PLLs are designed to increase the overlapping frequency range.

Using the third 8 and fourth 9 PLLs at 2200 and 2600 MHz allows you to expand the output frequency range of the proposed device.

The output frequency range with DAC 1 is narrow-band, and the PLL 3 filter ring is wide-band, which improves the overall performance of the device.

Claims (3)

1. A frequency synthesizer using a digital computational frequency synthesizer, comprising a digital computational frequency synthesizer (CVS), a first filter and a first phase locked loop (PLL), consisting of a series-connected phase detector (PD), a filter and a voltage controlled oscillator (VCO) ), the output of which is the output of the first PLL and connected through the divider to the PD input, characterized in that a second, third and fourth PLL are introduced, similar to the first PLL, and the output of the second PLL connected to the input of the CVC, the outputs of the third and fourth PLLs are connected to the corresponding inputs of the switching device, the output of which is connected to the corresponding input of the mixer, the output of which is the output of the synthesizer, while the output of the first PLL through the second filter is connected to another input of the mixer, in addition, the inputs of the second, third and fourth PLLs are connected and are the input for the signal of the reference generator. 2. The synthesizer according to claim 1, characterized in that the mixer is configured to convert up and convert down. 3. The synthesizer according to claim 1, characterized in that the second PLL is performed with the function of a cleaning ring of the reference signal for the DAC, and the third and fourth PLLs with the function of increasing the overlapping frequency range.

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