RU2602990C1 - Frequency synthesizer - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to radio electronics, namely to frequency synthesizers, based on phase automatic frequency control loop (FAFC). Frequency synthesizer comprises series-connected input signal frequency multiplier, divider with fixed division factor, first microcircuit of direct digital synthesis, phase-frequency detector first low-pass filter, voltage-controlled generator, negative feedback circuit comprising mixer, connected in series, one of inputs of which is connected to output of voltage-controlled generator, and second input is connected to output of input signal frequency multiplier, second low-pass filter and second microcircuit of direct digital synthesis, output of which is connected to input of phase-frequency detector, and control device, outputs of which are connected to inputs of first and second microcircuits of direct digital synthesis. Invention provides reduced level of phase noise and discrete components in output signal spectrum, which in turn improves quality of output signal, while maintaining high resolution and wide frequency band adjustment.

EFFECT: technical result consists in reduction of level of phase noise and secondary discrete components in output signal spectrum, which in turn improves quality of output signal, while maintaining high resolution and wide frequency band adjustment.

1 cl, 1 dwg

Description

FREQUENCY SYNTHESIS

The invention relates to electronics, in particular, to frequency synthesizers based on a phase locked loop (PLL).

A known frequency synthesizer containing a series-connected frequency converter of the input signal, a phase-frequency detector, a low-pass filter, a voltage-controlled generator, a negative feedback loop including a frequency converter of the output signal, the output of which is connected to the input of the phase-frequency detector, and a control device, outputs which are connected to the inputs of the frequency converters of the input and output signals (see, for example, the article by L. Belov, “Synthesizers of stable frequencies,” in J. “E ektronika: science, technology, business, "3/2004, pp 38-44, Figure 2)...

In the known synthesizer, dividers with an integer division coefficient are used as converters of the input and output signals.

A disadvantage of the known synthesizer is its low frequency resolution, which limits its scope.

In addition, the use of dividers with an integer division coefficient leads to a significant increase in phase noise in the spectrum of the output signal of the synthesizer.

Also known is a frequency synthesizer containing a series-connected frequency converter of the input signal, which is used direct digital synthesis chip, divider with integer division coefficient, phase-frequency detector, low-pass filter, voltage-controlled oscillator, negative feedback loop, including a frequency converter the output signal, which is used as a divider with an integer division factor, the output of which is connected to the input phase clock total detector, and a control device whose outputs are connected to the inputs of the frequency converters of the input and output signals (see US 5801589, 09/01/1998).

A disadvantage of the known frequency synthesizer also lies in the relatively high level of phase noise in the spectrum of the output signal due to the use of a divider with an integer division factor in the PLL loop.

In addition, the use of a direct digital synthesis chip as a converter of the input signal inevitably leads to the appearance of secondary discrete components in the spectrum of the output signal, despite the fact that the circuit of the known synthesizer does not allow their significant suppression to be realized.

The known frequency synthesizer is adopted as the closest analogue of the claimed frequency synthesizer.

An object of the present invention is to provide a frequency synthesizer devoid of these drawbacks.

The result is a technical result, which consists in reducing the level of phase noise and secondary discrete components in the spectrum of the output signal, which, in turn, improves the quality of the output signal, while maintaining high resolution in frequency and a wide tuning band.

Specifically, the technical result is achieved by creating a frequency synthesizer containing a serial frequency multiplier of the input signal, a divider with a fixed integer division factor, a first direct digital synthesis chip (hereinafter referred to as MPCS), a phase-frequency detector, a first low-pass filter, a voltage-controlled oscillator, a circuit negative feedback (hereinafter - OOS), which includes a mixer connected in series, one of the inputs of which is connected to the output of the generator, controlling direct voltage and a second input connected to the output of the multiplier input signal, a second low-pass filter and a second MPTSS, whose output is connected to an input of phase-frequency detector, and a control unit which outputs are connected to inputs of the first and second MPTSS.

The reduction in phase noise is achieved by reducing the frequency division coefficient in the PLL loop as a result of replacing the integer divider with a mixer, a second low-pass filter and a second MPCC connected in series.

A decrease in the level of secondary discrete components is ensured by the use of two direct digital synthesis chips in the circuit of the claimed frequency synthesizer, the inputs of which are connected to the outputs of the control device, which makes it possible to implement a variational algorithm suitable for suppressing secondary discrete components with various, including constant, frequency tuning steps in a wide range of frequencies, in particular, an algorithm similar to that described in US 5801589, 09/01/1998.

In FIG. 1 presents a diagram of the claimed frequency synthesizer.

The frequency synthesizer shown in FIG. 1, contains in series a frequency multiplier of the input signal 1, a divider with a fixed integer division coefficient 2, the first MPSC 3 used as a frequency converter of the input signal, a phase-frequency detector 4, the first low-pass filter 5, the generator 6, voltage-controlled, the OOS circuit 7 and control device 8.

The OOS circuit 7 includes a mixer 9 connected in series, one of the inputs of which is connected to the output of a voltage-controlled generator 6, and the second input is connected to the output of the input signal frequency multiplier 1, a second low-pass filter 10, and a second MPCC 11 used as a converter output signal frequency.

The output of the second MPCC 11 is connected to the input of the phase-frequency detector 4 with the formation of a PLL loop.

The outputs of the control device 8 are connected to the inputs of the first and second MPTSS 3 and 11.

The claimed frequency synthesizer operates as follows.

As shown in FIG. 1, from the reference oscillator 12 (not included in the frequency synthesizer) receive an input signal of a given frequency. The frequency of the reference oscillator is multiplied using a multiplier 1 and its subsequent division by an integer coefficient D (for example, D = 2) using a divider 2.

As a result, a signal with a frequency of F _sync is received and clocked by this signal of the first MPSC 3 to obtain a reference signal with a frequency of F _dds1 = α ₁ F _sync at its output, where α ₁ is the frequency conversion coefficient in the first MPSC 3.

Next, the phase and frequency of the reference and synchronized signals are compared to generate an analog voltage proportional to the phase and / or frequency mismatch using a phase-frequency detector 4, and then filter the resulting voltage at a low frequency using the first low-pass filter 5.

Further, this voltage is supplied to a voltage controlled oscillator 6 to obtain a signal with a frequency F _o at its output, and then part of the received signal is branched into the OOS circuit 7.

In the OOS 7 loop, the synchronized signal is obtained using the second MPCC 11, clocking it with a signal with a frequency of F _output -DF _sync , to obtain a signal at its output with a frequency of:

F _dds2 = α ₂ (F _out -DF _sync ), where α ₂ is the frequency conversion coefficient in the second MPCC 11.

Signal frequency F _O are prepared by mixing -DF _sync signals at frequencies F and _O DF _sync in the mixer 9 with further isolation difference component in the lowpass filter 10.

The selection sequence of the output frequencies F _dds1 and F _{dds2 is} implemented using the control device 8, by assigning the corresponding output frequencies F _oi values α ₁ and α ₂ for the first and second MPTSS 3 and 11, selected in accordance with the frequency correction algorithm, which suppresses discrete components in the spectrum of the output signal.

In particular, an algorithm similar to the known algorithm described in US 5,801,589 may be used.

The following is an estimate of the phase noise level of the frequency synthesizer, adopted as the closest analogue, and the claimed frequency synthesizer.

For evaluation, a mathematical expression taken from Venceslav F. Kroupa was used. Phase Locked Loops and Frequency Synthesizers, 2003, John Wiley and Sons, Ltd, p. 222.

For clarity, the evaluation excludes the intrinsic phase noise of the first MPCC.

As a result:

S _{Ф, out} (ω) = [S _{Ф, вх} (ω) + S _{Ф, ООС} (ω)] · N ² · | H (jω) | ² + S _{Ф, gun} (ω) | 1-H (jω) | ² where

S _{Ф, output} (ω) is the spectral power density of the phase fluctuations (hereinafter - SPMFF) of the output signal;

S _{Ф, вх} (ω) - SPMFF of the input signal (signal of the reference generator);

S _{Ф, ООС} (ω) - SPMFF of the components of the contour of ООС;

N is the division coefficient of the frequency divider in the OOS circuit;

S _{F, gun} (ω) - SPMFF voltage-controlled generator;

H (jω) is the transfer characteristic of the closed loop PLL.

Since in the passband of the first low-pass filter S _{Ф, gun} (ω) can be neglected, and H (jω) does not depend on the choice of N in the passband of the first low-pass filter, this expression can be rewritten as follows:

S _{Φ, out} (ω) = [S _{Φ, in} (ω) + S _{Φ, OOS} (ω)] · N ² .

Thus, the main contribution to the SPMPF of the output signal of the frequency synthesizer is made by the phase noise of the signal of the reference generator and the components of the OOS circuit,

SPMFF which is multiplied by the square of the integer division coefficient of the frequency divider.

In the inventive frequency synthesizer, the division coefficient is reduced by replacing the frequency divider with a mixer, a second low-pass filter and a second MPCC connected in series.

Then the SPMFF of the output signal can be written as:

, где

where

- СПМФФ контура ООС с учетом собственных шумов смесителя и фазовых шумов сигнала с выхода умножителя сигнала опорного генератора.

- SPMFF circuit of the OOS, taking into account the intrinsic noise of the mixer and phase noise of the signal from the output of the multiplier of the signal of the reference generator.

Taking the intrinsic noise of the second MPCC approximately equal to the intrinsic noise of the frequency divider with an integer division factor, we write:

Given that the frequency at the output of the voltage-controlled generator and the frequency multiplier should slightly differ, the SPMFF at the output of the multiplier for the circuit of the claimed frequency synthesizer can be represented as:

S _{Ф, УМ} (ω) = S _{Ф, Вх} (ω) K ² ≈S _{Ф, Вх} (ω) N ² .

As a result:

Since the scheme of the claimed frequency synthesizer assumes α ₂ << N, the effect of the intrinsic noise of the components S _{Ф, ООС} (ω) + S _{Ф, СМ} (ω) ООС on the level of the SPMFF of the output signal is significantly weakened.

Claims (1)

A frequency synthesizer comprising a first direct digital synthesis chip connected in series, a phase-frequency detector, a first low-pass filter, a voltage controlled oscillator, a negative feedback loop including an output frequency converter, the output of which is connected to an input of a phase-frequency detector, and a control device, one of the outputs of which is connected to the first input of the first direct digital synthesis chip, and the second output is connected to the first input of the frequency converter one signal, characterized in that it is equipped with a frequency multiplier of the input signal and a divider connected in series with it with a fixed integer division coefficient, the output of which is connected to the second input of the first direct digital synthesis chip, and a mixer is additionally introduced into the negative feedback loop, one from the inputs of which is connected to the output of the voltage-controlled generator, and the second input is connected to the output of the frequency multiplier of the input signal, and the second filter p low frequencies, the output of which is connected to a second input the output signal of the frequency converter, which is used as the second chip direct digital synthesis.

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