RU2579570C1 - Method of producing radio-frequency signal - Google Patents

Abstract

FIELD: communication.

SUBSTANCE: invention relates to synthesizers based on phase automatic frequency control loop (PLL). For production of radio-frequency signal, signal of frequency F_sync is obtained, and with this signal first microcircuit of direct digital synthesis is clocked in order to obtain reference signal with frequency F_dds1=α₁F_sync. Phases and frequencies of reference and synchronised signals are compared to generate analogue voltage proportional to phase and/or frequency mismatch, voltage obtained is filtered at low frequency, and this voltage is supplied to voltage-controlled generator, in order to produce at its output signal with frequency F_out. Part of obtained signal is derived into negative feedback loop for its frequency conversion with subsequent supply of converted signal as synchronised one to phase-frequency detector. Frequency transformation is performed by means of second microcircuit of direct digital synthesis, which is clocked with signal of frequency F_out-DF_sync, obtained by mixing of signals with frequencies F_out and DF_sync with further separation of differential component in order to produce signal with frequency F_dds2=α₂(F_out-DF_sync) at its output, where D is frequency division factor for clocking first microcircuit of direct digital synthesis. Note here that factors α₁ and α₂ are selected based on not fitting into predetermined "prohibited" values fields.

EFFECT: technical result consists in reduction of level of unwanted discrete components in output radio-frequency signal while reducing level of phase noise.

2 cl, 3 dwg

Description

The invention relates to electronics, in particular to synthesizers based on a phase locked loop (PLL).

A known method of producing a radio frequency signal, including receiving a signal of frequency F _sync , clocking this signal microcircuit direct digital synthesis (MPTSS) to obtain a reference signal frequency

F _dds1 = α ₁ F _sync

where α ₁ is the coefficient that is selected based on the condition of its failure to fall into predefined "forbidden" ranges of values, the conversion of which to the MPCC results in an output signal with secondary discrete components in the band F _dds1 ± F _add , where F _add is half the width MPTSS frequency band, in which it is necessary to ensure the absence of secondary discrete components, comparison of the phase and frequency of the reference and synchronized signal to generate an analog voltage proportional to the phase and / or frequency resolution harmonizing business, filtering the resultant voltage at a low frequency supply this voltage to the voltage controlled oscillator to produce at its output signal frequency F _O, the branch portion of the received signal in the negative feedback loop to its frequency conversion means integer division and then supplying the signal converted to phase-frequency detector as a synchronized one (US 5801589, 09/01/1998).

The disadvantage of this method is that the width of each “forbidden” area is assumed to be constant.

In other words, when choosing α _{1, the} dependence of the width of the “forbidden” region on the harmonic number is not taken into account, which leads to the fact that some of the allowed regions are identified as “forbidden”. This, in turn, leads to the “bonding” of neighboring “forbidden” areas.

In the case of taking into account a large number of harmonics, this leads to the “sticking together” of all the “forbidden” regions and the inability to choose suitable values of the coefficient α ₁ , as well as the integer frequency division coefficient in the negative feedback loop.

This, in turn, makes it impossible to significantly reduce the level of secondary discrete components in the spectrum of the output RF signal.

Another disadvantage of this method is the use of integer frequency division in the negative feedback loop, which inevitably leads to a significant increase in the phase noise level of the PLL components in the output signal spectrum.

An increase in the integer division coefficient during the implementation of the method leads to a further increase in the phase noise level.

The objective of the invention is to provide a method for producing a radio frequency signal devoid of these disadvantages.

The result is a technical result, which consists in reducing the level of discrete side components of the output RF signal while reducing the level of phase noise.

Specifically, the technical result is achieved by implementing a method for producing an RF signal, including receiving a signal of frequency F _sync , clocking this signal with the first MPSC to obtain a reference signal of frequency

F _dds1 = α ₁ F _sync

where α ₁ is the coefficient that is selected based on the condition of its failure to fall into the predefined “forbidden” ranges of values, the conversion of which in the first MPCC results in an output signal with secondary discrete components in the band F _dds1 ± F _add , where F _add is half MPTSS frequency bandwidth, in which it is necessary to ensure the absence of secondary discrete components, comparison of the phase and frequency of the reference and synchronized signal to generate an analog voltage proportional to the phase and / or frequency y misalignment, filtering the resultant voltage at a low frequency supply this voltage to the voltage controlled oscillator to produce at its output signal frequency F _O, the branch portion of the received signal in the negative feedback loop to its frequency conversion and then supplying the converted signal to the phase frequency detector as synchronized. Frequency conversion is performed by the second MPTSS, taktiruya its signal frequency F _O -DF _sinhr obtained by mixing signals at frequencies F and _O DF _sync with the further allocation of a difference component to produce at its output a frequency signal

F _dds2 = α ₂ (F _out -DF _sync ),

where D is the frequency division coefficient for clocking the first MPTSS,

α ₂ = Cα ₁ ,

.

.

α ₁ is determined from a mathematical expression

,

,

where γ _iach is the left border of the “forbidden” region immediately following the widest “allowed” region,

γ _i-1con is the right border of the “forbidden” area, which is in front of the widest “allowed” area.

If α ₂ takes on a value inside the “forbidden” region, α _{2 is} assigned the value α ₂ ^* from the neighboring “allowed” region so that the condition

,

,

,Where

,

and produce a change in the frequency of the reference signal F _dds1 , assigning α ₁ value α ₁ ^* , where

.

.

In a particular embodiment, a signal of frequency F _{sync is} obtained by multiplying the frequency of the reference oscillator and then dividing it by a factor D.

The use of the described sequence of selecting the coefficients α ₁ and α ₂ (and, accordingly, F _dds1 and F _dds2 ) during the implementation of the method leads to a significant decrease in the level of secondary discrete components of the output RF signal and, therefore, to an increase in its quality.

Preparation synchronous signal resulting MPTSS clock signal frequency F _O -DF _sinhr obtained by mixing signals at frequencies F and _O DF _sync with the release of further difference component reduces the phase noise.

In FIG. 1 presents a diagram allowing to implement the claimed method.

In FIG. Figure 2 shows a graph of the dependence of the width of the “forbidden” regions on the output frequency of the first MPCC, normalized to its clock frequency F _dds1 / F _sync .

In FIG. 3 shows an illustration of the frequency selection sequence of the first and second MPTS F _dds1 and F _dds2 for the formation of output frequencies outside the "forbidden" areas.

The claimed method is implemented as follows.

As shown in the diagram of FIG. 1, a reference signal of a given frequency is obtained from the reference oscillator 1. The frequency of the reference oscillator is multiplied using the multiplier 2 and its subsequent division by an integer coefficient D using the divider 3.

As a result, a signal with a frequency of F _sync is received and clocked by this signal to the first MPSC 4 to obtain a reference signal with a frequency of F _dds1 = α ₁ F _sync at its output.

Next, the phase and frequency of the reference and synchronized signals are compared to generate an analog voltage proportional to the phase and / or frequency mismatch using a phase-frequency detector 5, and then filter the resulting voltage at a low frequency using a low-pass filter 6,

Further, this voltage is supplied to a voltage controlled oscillator (VCO) 7 to obtain a signal with a frequency of F _o at its output, and then part of the received signal is branched into a negative feedback loop (OOS) 8.

The circuit DUS synchronized signal obtained by the second MPTSS 9 taktiruya its signal frequency F _O -DF _sync to obtain at its output a frequency signal

F _dds2 = α ₂ (F _out -DF _sync ).

Signal frequency F _O are prepared by mixing -DF _sync signals at frequencies F and _O DF _sync in a mixer 10 with subsequent separation of the difference component in the low pass filter 11.

The sequence of selection of the output frequencies F _dds1 and F _dds2 can be implemented using the control device 12 by assigning the corresponding output frequencies F to the _output codes α ₁ and α ₂ for the first and second MPSC 4 and 9, selected in accordance with a previously defined and stored in the control memory devices 12 with a set of “forbidden” areas.

,"Prohibited" areas are found using a program that runs, for example, on a personal computer. The program calculates a set of ratios

,

where F _dds1кp is a set of frequencies, the receipt of signals at which in the first MPTS 4 leads to the coincidence of the frequencies of the main harmonics and higher order harmonics of these signals due to the superposition effect.

In other words, this is a set of frequencies of the first MPCC multiple of its clock frequency F _sync (hereinafter referred to as multiple frequencies)

± F _ddd1cr = mF _sync -nF _dds1cr ,

,

,

where n is the harmonic number of the signal from the output of the first MPTS 4, taken in the range from 1 to N,

.m is the corresponding n harmonic number of the clock frequency, and

.

определяют ширину «запрещенной» области из условия попадания гармоник выходного сигнала F_dds1 в некоторую окрестность F_dds1±F_доп.For everybody

determine the width of the “forbidden” region from the condition that the harmonics of the output signal F _{dds1 fall} into some neighborhood F _dds1 ± F _add .

,

,

where F _dds1 = F _dds1cr + ΔF,

where ΔF is the detuning F _dds1 from the nearest multiple frequency F _dds1cr .

Divide both sides of the inequality by F _sync , getting

,

,

where γ is the set of output frequencies F _dds1 normalized to the clock frequency F _sync .

,

,

where γ _kr is the set of multiple frequencies from the output of the first MPSC, normalized to the clock frequency F _sync ,

Δγ is the detuning F _dds1 from the nearest multiple frequency F _dds1кр , normalized to the clock frequency F _sync .

и ширину «запрещенной» области определяют как

.Receive

and the width of the “forbidden” region is defined as

.

The calculation result in the form of a graph of the dependence of the width of the “forbidden” areas on the output frequency of the first MPTS 4 normalized to its clock frequency F _dds1 / F _sync is shown in FIG. 2.

The set of forbidden areas is as follows:

,

,

where γ _1nach , γ _2nach , ..., γ _knach - coefficients that determine the left boundaries of the “forbidden” areas;

γ _1con , γ _2con , ..., γ _kcon — coefficients that determine the right boundaries of the “forbidden” areas;

k is the number of “forbidden” areas,

Then, the coefficients α ₁ and α ₂ are selected in accordance with the previously calculated “forbidden” areas.

α _{1 is} determined from a mathematical expression by assigning a value corresponding to the middle of the widest allowed area:

,

,

where i is the number of the “forbidden” area immediately following the widest “allowed” area.

The coefficient α _{2 is} recalculated from α ₁ as follows:

α ₂ = Сα ₁ , where

,

,

If α ₂ takes on a value inside the “forbidden” region, α _{2 is} assigned the value α ₂ ^* from the neighboring “allowed” region so that the condition

,

,

,Where

,

and make a change in the frequency F _{dds1 of the} signal from the output of the first MPTS 4, assigning α ₁ value α ₁ ^* , where

.

.

If α ₂ does not fall into the “forbidden” region, then the values of α ₁ and α _{2 are} recorded in MPTSS 4 and 9. Accordingly, if α ₂ falls into the “forbidden” region, then α ₁ ^* and α ₂ ^{* are} recorded in microcircuits of direct digital synthesizers.

The sequence of selecting the output frequencies F _dds1 and F _{dds2 of the} first and second MSCS 4 and 9 for generating the output frequencies F _oi outside the “forbidden” areas is illustrated in FIG. 3.

.Suppose you want to receive the signal from the output frequency F _O = 2,3583F _sync misses with the first N = 200 F _O harmonics ± F _ext where

.

The coefficient α _{1 is} assigned a value corresponding to the middle of the widest “allowed” region α ₁ = 0.143292.

Α ₂ = C ₁ = 0.400071 is calculated.

Since α ₂ falls into the “forbidden” region, the coefficient α _{2 is} assigned the value α ₂ ^* = 0.4006, which corresponds to the middle of the closest “allowed” region.

.Calculate

.

Check the values of α ₁ ^* and α ₂ ^* to get inside the "forbidden" areas.

Since the values α ₁ and α ₂ ^{* *} are out of the "forbidden" regions, therefore, in MPTSS 4 and 9 are recorded and α ₁ ^* α ₂ ^*.

Claims (2)

1. A method of obtaining a radio frequency signal, including
receiving a signal with a frequency of F _sync , clocking this signal of the first direct digital synthesis chip to obtain a reference signal with a frequency

where α ₁ is the coefficient that is selected based on the condition of its failure to fall into predefined "forbidden" ranges of values, the conversion of which in the first direct digital synthesis chip leads to an output signal with secondary discrete components in the band F _dds1 ± F _add , where F _dop - half the frequency bandwidth of the first direct digital synthesis chip, in which it is necessary to ensure the absence of secondary discrete components, a comparison of the phase and frequency of the reference and synchronized signal for analog voltage, proportional to the phase and / or frequency mismatch, filtering the received voltage at a low frequency, applying this voltage to a voltage-controlled generator to receive a signal with a frequency F _o at its output, branching a part of the received signal into the negative feedback loop for its frequency conversion with subsequent supply of the converted signal to the phase-frequency detector as a synchronized one, characterized in that the frequency conversion is carried out by by a second direct digital synthesis circuit, taktiruya its signal frequency F _O -DF _sinhr obtained by mixing signals at frequencies F and _O DF _sync with the further allocation of a difference component to produce at its output a frequency signal:

where D is the frequency division coefficient for clocking the first chip direct digital synthesis,

α ₁ is determined from a mathematical expression

where γ _iach is the left border of the “forbidden” region immediately following the widest “allowed” region,
γ _i-1con - the right border of the “forbidden” area in front of the widest “allowed” area,
in this case, if α ₂ takes on a value inside the “forbidden” region, α _{2 is} assigned the value

from the neighboring “allowed” area so that the condition is met

Where

and produce a change in the frequency of the reference signal F _dds1 , assigning α ₁ value

Where

2. The method according to p. 1, characterized in that the signal with frequency F _{sync is} obtained by multiplying the frequency of the reference oscillator and its subsequent division by D.

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