CN114157294B - Low phase noise frequency synthesizer captured by cooperation of analog phase discriminator and digital frequency discriminator - Google Patents

Low phase noise frequency synthesizer captured by cooperation of analog phase discriminator and digital frequency discriminator Download PDF

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CN114157294B
CN114157294B CN202111516820.2A CN202111516820A CN114157294B CN 114157294 B CN114157294 B CN 114157294B CN 202111516820 A CN202111516820 A CN 202111516820A CN 114157294 B CN114157294 B CN 114157294B
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phase
frequency
locked loop
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CN114157294A (en
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杨远望
罗鼎
焦利彬
邓建华
游长江
朱学勇
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The invention discloses a low-phase noise frequency synthesizer captured by cooperation of an analog phase discriminator and a digital frequency discriminator, which comprises the steps of firstly multiplying the frequency of an input reference signal to a required frequency band through two serially connected frequency multipliers, and obtaining signals of different frequency bands from output ends of different frequency multipliers; when the frequency is synthesized, the multiplexer closes the phase-locked loop of the analog phase-locked loop, opens the phase-locked loop of the digital phase-locked loop, sends the signal with lower frequency band output by the first frequency multiplier and the feedback signal output by the voltage-controlled oscillator to the digital phase-locked loop for preliminary capture, and when the signal enters the phase-locked range of the analog phase-locked loop, the multiplexer controls to close the phase-locked loop of the digital phase-locked loop, opens the phase-locked loop of the analog phase-locked loop, sends the signal with higher frequency band output by the second frequency multiplier and the feedback signal output by the voltage-controlled oscillator to the phase-locked loop of the analog phase-locked loop for continuous capture and finally enters a synchronous state, thereby obtaining the phase-locked signal with high precision and low phase noise.

Description

Low phase noise frequency synthesizer captured by cooperation of analog phase discriminator and digital frequency discriminator
Technical Field
The invention belongs to the technical field of frequency synthesis, and particularly relates to a low-phase-noise frequency synthesizer captured by cooperation of an analog phase discriminator and a digital frequency discriminator.
Background
Phase locked clock technology refers to obtaining a high precision clock signal through a phase locked loop. With the development of digital communication systems, the more widely used are high-precision clocks and phase-locked loops. For example, reference carrier extraction for coherent demodulation, bit synchronization establishment, etc. are all independent of phase-locked loop applications. In terms of electronic instruments, phase locked loops play an important role in frequency synthesizers, phase meters, and the like. To date, phase locked loops are widely used in addition to conventional applications in the manufacture of high precision clock sources. In the electronic informatization construction, equipment put into long-term use often depends on a special clock circuit; however, in the process of independently running the clocks, the clocks which are independently running often generate different errors, and the errors between the devices are larger and larger along with the accumulation of time. To solve this problem, a high-precision clock source technology has also been proposed, and a high-precision clock source based on a phase-locked loop has also been proposed.
A phase locked loop is a feedback control circuit, referred to as a Phase Locked Loop (PLL). The phase-locked loop is characterized in that: the frequency and phase of the oscillation signal inside the loop are controlled by using an externally input reference signal. Phase locked loops are commonly used in closed loop tracking circuits because they enable automatic tracking of the frequency of an output signal to the frequency of an input signal. In the working process of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the phase difference value between the output voltage and the input voltage is kept fixed, namely the phase of the output voltage and the input voltage is locked, which is the origin of the name of the phase-locked loop. The phase-locked loop is typically composed of three parts, a Phase Detector (PD), a Loop Filter (LF), and a Voltage Controlled Oscillator (VCO).
The phase-locked loop can be divided into an analog structure phase-locked loop, an all-digital structure phase-locked loop and a digital-analog hybrid phase-locked loop according to different structures. The invention mainly adopts an analog phase-locked loop, which mainly comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled oscillator and an N frequency divider.
A phase detector is a circuit that makes a certain relationship between an output voltage and a phase difference between two input signals. The function representing the relationship therebetween is called phase discrimination characteristic. Phase detectors are one of the basic components of phase locked loops and are also used for demodulation of frequency and phase modulated signals. Common phase discrimination characteristics are cosine type, sawtooth type, triangle type, etc. The phase detector may be classified into an analog phase detector and a digital phase detector. The phase-locked loop formed by the digital phase discriminator is wide in capture bandwidth and relatively low in phase discrimination frequency capable of working normally; in contrast, analog phase detectors can discriminate relatively high frequencies, but tend to have a narrow capture bandwidth.
A loop filter is a filter having a certain specific filtering characteristic, the loop characteristic of a phase locked loop depending on the characteristics of the filter. The output of the filter is used as the input voltage of a voltage-controlled oscillator to change the output frequency, the voltage-controlled oscillator is an important module in the phase-locked loop, and the performance of the resonance signal determines the performance of the output signal of the phase-locked loop. The frequency divider forms a feedback loop of the phase-locked loop, and is limited by the operating frequency of the phase detector, and the output high-frequency signal of the voltage-controlled oscillator needs to be divided down to a lower frequency by the frequency divider so that the phase detector can compare the output high-frequency signal with a reference clock.
Along with the progress of technical development, the frequencies of clocks and local oscillation signals used in reality are higher and higher, and when the frequency band used is increased to the gigahertz magnitude or above, the traditional digital phase discriminator is difficult to realize, the phase discrimination range of the analog phase discriminator is very narrow, and the original application value of the analog phase discriminator is gradually lost. Therefore, a phase-locked loop for higher frequency band with high enough loop acquisition and synchronization accuracy has application value.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a low-phase-noise frequency synthesizer which is captured by combining an analog phase discriminator with a digital phase discriminator, and the phase-locked signal with high precision and low phase noise is obtained by capturing the phase-locked signal by combining the analog phase discriminator with the digital phase discriminator and finally entering a synchronous state.
In order to achieve the above object, the present invention provides a low phase noise frequency synthesizer captured by cooperation of an analog phase discriminator and a digital frequency discriminator, comprising: the phase-locked loop circuit comprises a frequency multiplication circuit, a digital phase-frequency detector phase-locked loop, an analog phase-detector phase-locked loop, a multipath selection module and a voltage-controlled oscillator;
the frequency doubling circuit consists of two serially connected frequency multipliers, and the frequency doubling parameters of the frequency doublerN and M respectively; frequency f c The inherent frequency difference is delta omega 0 The reference signal of the phase-locked loop is input to the digital phase-locked loop after frequency multiplication treatment is carried out by an N-time frequency multiplier, and then is input to the analog phase-locked loop after frequency multiplication treatment is carried out by an M-time frequency multiplier; wherein the frequency of the reference signal input into the phase-locked loop of the digital phase-frequency detector is f' c ＝N*f c The reference signal input to the phase-locked loop of the analog phase detector has a frequency f' c ＝M*N*f c ；
The maximum capture bandwidth of the digital phase frequency detector phase-locked loop is delta omega' p The structure of the digital phase frequency detector comprises the digital phase frequency detector, a second loop filter and a high-multiplying power frequency divider, and the digital phase frequency detector has the function of completing the preliminary capturing process, so that the frequency difference of a phase-locked loop of the digital phase frequency detector is controlled in the locking range of the analog phase detector;
the specific process of preliminary capture is: first, the frequency is f' c The input signal of the frequency divider is sent into a phase-locked loop of a digital phase-frequency detector, and the digital phase-frequency detector performs difference on the input signal and a feedback signal output by a voltage-controlled oscillator of the high-multiplying power frequency divider to obtain a frequency difference delta omega and a phase difference delta theta; wherein the frequency difference Deltaω is directly input to the multiplexer, and the phase difference Deltaθ is output as an error voltage Deltau by the digital phase frequency detector d Error voltage Deltau d Then the control voltage u is obtained through the filtering process of the second loop filter c Finally control voltage u c After being controlled by a multiplexer, the signals are input into a voltage-controlled oscillator, the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of a digital phase-frequency detector, in the process, the difference between the oscillation frequency of the oscillation signal and the frequency and the phase of the input signal is gradually reduced, the multiplexer continuously judges the frequency difference delta omega, and when the frequency difference delta omega is converged to be smaller than delta omega' p When the multiplexer is switched to the analog phase detector phase-locked loop;
the maximum capture bandwidth of the phase-locked loop of the analog phase detector is Deltaomega'. p The structure specifically comprises an analog phase discriminator, a first loop filter and a low-multiplying power frequency divider, and the functions of the analog phase discriminator, the first loop filter and the low-multiplying power frequency divider are to finish final capturing andsynchronizing;
the specific process of final capture and synchronization is: when the multiplexer is switched to the phase-locked loop of the analog phase discriminator, the frequency is first set to f' c The input signal of (2) is sent into a phase-locked loop of an analog phase discriminator, and the analog phase discriminator makes a difference between the input signal and a feedback signal output by a voltage-controlled oscillator of a low-multiplying power frequency divider to obtain a frequency difference
Figure BDA0003406919890000031
Phase difference->
Figure BDA0003406919890000032
The method comprises the steps of carrying out a first treatment on the surface of the Wherein the frequency difference->
Figure BDA0003406919890000033
Directly input to the multiplexer, phase difference +.>
Figure BDA0003406919890000034
Output as an error voltage by means of an analog phase detector>
Figure BDA0003406919890000035
Error voltage->
Figure BDA0003406919890000036
Filtering with a first loop filter to obtain control voltage +.>
Figure BDA0003406919890000037
Finally control voltage->
Figure BDA0003406919890000038
After being controlled by the multiplexer, the multiplexer is input into a voltage-controlled oscillator, the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of the analog phase discriminator, and in the process, the multiplexer continuously performs frequency matching>
Figure BDA0003406919890000039
Judging to track the convergence state of the phase-locked loop until the frequencies are combinedThe forming process is completed, and the oscillation frequency of the oscillation signal deviates towards the direction close to the input signal, so that the difference between the oscillation frequency and the phase of the input signal finally tends to be zero, thereby outputting a phase-locked signal with high precision and low phase noise, and the frequency synthesis process is completed;
the multi-path selection module is mainly used for realizing the switching process between the digital phase frequency detector phase-locked loop and the analog phase detector phase-locked loop; at the initial moment, the multi-path selection module is switched in a digital phase frequency detector phase-locked loop by default;
the voltage-controlled oscillator is used for receiving the control voltage selected by the multiplexer, adjusting the oscillation frequency of the voltage-controlled oscillator and feeding back the control voltage to the multiplexer.
The invention aims at realizing the following steps:
the invention relates to a low-phase noise frequency synthesizer which is captured by cooperation of an analog phase discriminator and a digital frequency discriminator, wherein an input reference signal is multiplied to a required frequency band through two serially connected frequency multipliers, and the required signals in different frequency bands are obtained from the output ends of different frequency multipliers; when the frequency is synthesized, the multiplexer closes the phase-locked loop of the analog phase-locked loop, opens the phase-locked loop of the digital phase-locked loop, sends the signal with lower frequency band output by the first frequency multiplier and the feedback signal output by the voltage-controlled oscillator to the digital phase-locked loop for preliminary capture, and when the signal enters the phase-locked range of the analog phase-locked loop, the multiplexer controls to close the phase-locked loop of the digital phase-locked loop, opens the phase-locked loop of the analog phase-locked loop, sends the signal with higher frequency band output by the second frequency multiplier and the feedback signal output by the voltage-controlled oscillator to the phase-locked loop of the analog phase-locked loop for continuous capture and finally enters a synchronous state, thereby obtaining the phase-locked signal with high precision and low phase noise.
Meanwhile, the low-phase noise frequency synthesizer captured by cooperation of the analog phase discriminator and the digital frequency discriminator has the following beneficial effects:
(1) The invention multiplexes a voltage-controlled oscillator in the phase-locked loop of the analog phase discriminator and the phase-locked loop of the digital phase discriminator, which reflects the characteristic of low cost;
(2) The invention adopts two frequency multipliers to solve the contradiction caused by different phase discrimination frequency bands of the analog phase discriminator and the digital phase discriminator, so that different phase discriminators can be multiplexed in the same circuit;
(3) The invention introduces the multiplexer, so that the synthesizer can realize the switching between the analog phase discriminator and the digital phase discriminator under certain conditions in the frequency synthesis process, thereby ensuring that the capturing process of the whole loop is more stable;
(4) The invention adopts a structure of combining the analog phase detector and the digital phase detector, thereby not only playing the advantages of wide capture bandwidth of the digital phase detector and high capture precision of the analog phase detector, but also avoiding the defects that the digital phase detector cannot work in a high frequency band and the loop of the analog phase detector cannot be locked due to insufficient capture bandwidth.
Drawings
Fig. 1 is a schematic diagram of a low phase noise frequency synthesizer captured in cooperation with an analog phase detector and a digital frequency detector in accordance with the present invention.
Detailed Description
The following description of the embodiments of the invention is presented in conjunction with the accompanying drawings to provide a better understanding of the invention to those skilled in the art. It is to be expressly noted that in the description below, detailed descriptions of known functions and designs are omitted here as perhaps obscuring the present invention.
Examples
Fig. 1 is a schematic diagram of a low phase noise frequency synthesizer captured in cooperation with an analog phase detector and a digital frequency detector in accordance with the present invention.
In this embodiment, as shown in fig. 1, a low-phase noise frequency synthesizer captured by cooperation of an analog phase discriminator and a digital phase discriminator according to the invention comprises: the phase-locked loop circuit comprises a frequency multiplication circuit, a digital phase-frequency detector phase-locked loop, an analog phase-detector phase-locked loop, a multipath selection module and a voltage-controlled oscillator;
the frequency doubling circuit consists of two serially connected frequency multipliers, and the frequency doubling parameters of the frequency doubler are N and M respectively; frequency f c The inherent frequency difference is delta omega 0 Reference signal of (2)The number is firstly subjected to frequency multiplication through a frequency multiplier of N times and then is input into a digital phase frequency detector phase-locked loop, and then is subjected to frequency multiplication through a frequency multiplier of M times and then is input into an analog phase detector phase-locked loop; wherein the frequency of the reference signal input into the phase-locked loop of the digital phase-frequency detector is f' c ＝N*f c The reference signal input to the phase-locked loop of the analog phase detector has a frequency f' c ＝M*N*f c ；
In this embodiment, the first frequency multiplier outputs a signal with a lower frequency band, the second frequency multiplier outputs a signal with a higher frequency band, and the required signals with different frequency bands are obtained from the output end of the different frequency multipliers;
the maximum capture bandwidth of the digital phase frequency detector phase-locked loop is delta omega' p As shown in fig. 1, the structure specifically includes a digital phase frequency detector, a second loop filter and a high-multiplying power frequency divider, which are used for completing the preliminary capturing process, so that the frequency difference of the phase-locked loop of the digital phase frequency detector is controlled within the locking range of the analog phase detector; in this embodiment, the frequency division multiple of the high-multiplying power frequency divider is k×m;
the specific process of preliminary capture is: first, the frequency is f' c The input signal of the frequency divider is sent into a phase-locked loop of a digital phase-frequency detector, and the digital phase-frequency detector performs difference on the input signal and a feedback signal output by a voltage-controlled oscillator of the high-multiplying power frequency divider to obtain a frequency difference delta omega and a phase difference delta theta; wherein the frequency difference Deltaω is directly input to the multiplexer, and the phase difference Deltaθ is output as an error voltage Deltau by the digital phase frequency detector d Error voltage Deltau d Then the control voltage u is obtained through the filtering process of the second loop filter c The magnitude of the voltage determines the oscillation frequency of the voltage-controlled oscillator, and finally controls the voltage u c After being controlled by a multiplexer, the signals are input into a voltage-controlled oscillator, the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of a digital phase-frequency detector, in the process, the difference between the oscillation frequency of the oscillation signal and the frequency and the phase of the input signal is gradually reduced, the multiplexer continuously judges the frequency difference delta omega, and when the frequency difference delta omega is converged to be smaller than delta omega' p When the multiplexer will be cutSwitching to an analog phase detector phase-locked loop;
the maximum capture bandwidth of the phase-locked loop of the analog phase detector is Deltaomega'. p As shown in fig. 1, the structure specifically includes an analog phase detector, a first loop filter and a low-multiplying power frequency divider, and the functions of the analog phase detector, the first loop filter and the low-multiplying power frequency divider are to complete final capturing and synchronization; in this embodiment, the frequency division multiple of the low-power frequency divider is K;
the specific process of final capture and synchronization is: when the multiplexer is switched to the phase-locked loop of the analog phase discriminator, the frequency is first set to f' c The input signal of (2) is sent into a phase-locked loop of an analog phase discriminator, and the analog phase discriminator makes a difference between the input signal and a feedback signal output by a voltage-controlled oscillator of a low-multiplying power frequency divider to obtain a frequency difference
Figure BDA0003406919890000061
Phase difference->
Figure BDA0003406919890000062
The method comprises the steps of carrying out a first treatment on the surface of the Wherein the frequency difference->
Figure BDA0003406919890000063
Directly input to the multiplexer, phase difference +.>
Figure BDA0003406919890000064
Output as an error voltage by means of an analog phase detector>
Figure BDA0003406919890000065
Error voltage->
Figure BDA0003406919890000066
Filtering with a first loop filter to obtain control voltage +.>
Figure BDA0003406919890000067
Finally control voltage->
Figure BDA0003406919890000068
Is controlled by a multiplexer and then is input into a voltage-controlled oscillator,the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of the analog phase discriminator, and in the process, the multiplexer continuously pairs the frequency difference +.>
Figure BDA0003406919890000069
Judging to track the convergence state of the phase-locked loop until the frequency synthesis process is completed, and shifting the oscillation frequency of the oscillation signal to the direction close to the input signal, so that the difference between the oscillation frequency and the phase of the input signal finally tends to be zero, thereby outputting a phase-locked signal with high precision and low phase noise, and the frequency synthesis process is completed up to the point;
in the present embodiment, the natural frequency difference Δω 0 Maximum acquisition bandwidth Δω 'of digital phase frequency detector phase-locked loop' p Maximum acquisition bandwidth Δω "of an analog phase detector phase locked loop" p The method meets the following conditions: Δω' p ＞Δω 0 ＞Δω” p ；
The multi-path selection module is mainly used for realizing the switching process between the digital phase frequency detector phase-locked loop and the analog phase detector phase-locked loop; at the initial moment, the multi-path selection module is switched in a digital phase frequency detector phase-locked loop by default;
the voltage-controlled oscillator is used for receiving the control voltage selected by the multiplexer, adjusting the oscillation frequency of the voltage-controlled oscillator and feeding back the control voltage to the multiplexer.
In summary, the low phase noise frequency synthesizer is capable of performing high-precision low phase noise locking on the reference signal, and outputting the locked signal to an external circuit through an interface.
While the foregoing describes illustrative embodiments of the present invention to facilitate an understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but is to be construed as protected by the accompanying claims insofar as various changes are within the spirit and scope of the present invention as defined and defined by the appended claims.

Claims (2)

1. A low phase noise frequency synthesizer captured in cooperation with an analog phase detector and a digital frequency detector, comprising: the phase-locked loop circuit comprises a frequency multiplication circuit, a digital phase-frequency detector phase-locked loop, an analog phase-detector phase-locked loop, a multipath selection module and a voltage-controlled oscillator;
the frequency doubling circuit consists of two serially connected frequency multipliers, and the frequency doubling parameters of the frequency doubler are N and M respectively; frequency f c The inherent frequency difference is delta omega 0 The reference signal of the phase-locked loop is input to the digital phase-locked loop after frequency multiplication treatment is carried out by an N-time frequency multiplier, and then is input to the analog phase-locked loop after frequency multiplication treatment is carried out by an M-time frequency multiplier; wherein the frequency of the reference signal input into the phase-locked loop of the digital phase-frequency detector is f' c ＝N*f c The frequency of the reference signal input to the phase-locked loop of the analog phase detector is f c ＝M*N*f c ；
The maximum capture bandwidth of the digital phase frequency detector phase-locked loop is delta omega' p The structure of the phase-locked loop circuit specifically comprises a digital phase-frequency detector, a second loop filter and a high-multiplying power frequency divider, and the function of the phase-locked loop circuit is to complete the initial capturing process, so that the frequency difference of the phase-locked loop of the digital phase-frequency detector is controlled in the locking range of the analog phase detector;
the specific process of preliminary capture is: first, the frequency is f' c The input signal of the frequency divider is sent into a phase-locked loop of a digital phase-frequency detector, and the digital phase-frequency detector performs difference on the input signal and a feedback signal output by a voltage-controlled oscillator of the high-multiplying power frequency divider to obtain a frequency difference delta omega and a phase difference delta theta; wherein the frequency difference Deltaω is directly input to the multiplexer, and the phase difference Deltaθ is output as an error voltage Deltau by the digital phase frequency detector d Error voltage Deltau d Then the control voltage u is obtained through the filtering process of the second loop filter c Finally control voltage u c After being controlled by the multiplexer, the signals are input into the voltage-controlled oscillator, the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of the digital phase-frequency detector, in the process, the difference between the oscillation frequency of the oscillation signal and the frequency and the phase of the input signal is gradually reduced, and the multiplexer continuously carries out the frequency difference delta omegaJudging when the frequency difference delta omega is converged to be smaller than delta omega' p When the multiplexer is switched to the analog phase detector phase-locked loop;
the maximum capture bandwidth of the phase-locked loop of the analog phase discriminator is delta omega' p The structure of the device specifically comprises an analog phase discriminator, a first loop filter and a low-multiplying power frequency divider, and the function of the device is to finish final capturing and synchronization;
the specific process of final capture and synchronization is: when the multiplexer is switched to the phase-locked loop of the analog phase discriminator, the frequency is f c The input signal of (2) is sent into a phase-locked loop of an analog phase discriminator, and the analog phase discriminator makes a difference between the input signal and a feedback signal output by a voltage-controlled oscillator of a low-multiplying power frequency divider to obtain a frequency difference
Figure FDA0003406919880000011
Phase difference->
Figure FDA0003406919880000012
Wherein the frequency difference->
Figure FDA0003406919880000013
Directly input to the multiplexer, phase difference +.>
Figure FDA0003406919880000014
Output as an error voltage by means of an analog phase detector>
Figure FDA0003406919880000015
Error voltage->
Figure FDA0003406919880000016
Filtering with a first loop filter to obtain control voltage +.>
Figure FDA0003406919880000017
Finally control voltage->
Figure FDA0003406919880000018
After being controlled by the multiplexer, the multiplexer is input into a voltage-controlled oscillator, the voltage-controlled oscillator generates an oscillation signal with frequency offset and is used as a feedback signal of the analog phase discriminator, and in the process, the multiplexer continuously performs frequency matching>
Figure FDA0003406919880000021
Judging to track the convergence state of the phase-locked loop until the frequency synthesis process is completed, and shifting the oscillation frequency of the oscillation signal to the direction close to the input signal, so that the difference between the oscillation frequency and the phase of the input signal finally tends to be zero, thereby outputting a phase-locked signal with high precision and low phase noise, and the frequency synthesis process is completed up to the point;
the multi-path selection module is mainly used for realizing the switching process between the digital phase frequency detector phase-locked loop and the analog phase detector phase-locked loop; at the initial moment, the multi-path selection module is switched in a digital phase frequency detector phase-locked loop by default;
the voltage-controlled oscillator is used for receiving the control voltage selected by the multiplexer, adjusting the oscillation frequency of the voltage-controlled oscillator and feeding back the control voltage to the multiplexer.
2. The low phase noise synthesizer captured in cooperation with an analog phase detector and a digital frequency detector of claim 1, wherein said natural frequency difference Δω 0 Maximum acquisition bandwidth Δω 'of digital phase frequency detector phase-locked loop' p Maximum capture bandwidth Δω″ of analog phase detector phase locked loop p The method meets the following conditions: Δω' p ＞Δω 0 ＞Δω″ p 。
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