RU122533U1 - DEVICE FOR DEMODULATION OF PHASOMANIPULATED SIGNALS - Google Patents

Abstract

A device for demodulating phase-shift keyed signals containing first, second and third multipliers, first and second low-pass filters, a loop filter, a first governor, a first phase shifter, a controlled generator, the input of the device being connected to the first inputs of the first and second multipliers, to the second input of the first multiplier the output of the controlled generator is connected directly, and the output of the controlled generator is connected to the second input of the second multiplier through the cascaded first phase shifter, the output of the first multiplier is connected to the first input of the third multiplier through the cascaded first low-pass filter, the output of the second multiplier is connected to the second input of the third multiplier through the cascade the second low-pass filter is switched on, the output of the third multiplier is connected to the input of the controlled generator through a cascaded loop filter, the first controller and the second adder, characterized in that re a scattering device, an autocorrelation frequency discriminator and a second adder, and the decider has two inputs and two outputs and consists of the fourth, fifth, sixth and seventh multipliers, the first and second delay lines, the first adder, the first and second subtractors, the third and fourth low filters frequencies, the first functional converter and the second controller, and the first inputs of the fourth and sixth multipliers and the input of the first delay line are connected in parallel to the first input of the solver, to the output of which the second inputs of the fourth and fifth

Description

The utility model relates to the field of radio monitoring of phase-shift keyed signals (PMS) with a large a priori unknown range of Doppler frequency shift.

The known FMS demodulator according to the Pistolkors scheme [1 - Petrovich N.T. "Transmission of discrete information in channels with phase shift keying." - M .: Owls. Radio, 1965], consisting of an input band-pass filter, a phase detector, and a carrier wave recovery channel including a frequency doubler, a narrow-band filter, a frequency divider, and a phase shifter.

The disadvantage of this analogue is the low noise immunity, due to the fact that with a large range of a priori uncertainty of the Doppler frequency shift of the signal, it is necessary to significantly increase the passband of the narrow-band filter.

Also known is the FMS autocorrelation demodulator [2 - Feer K. "Wireless Digital Communication". - M .: radio and communication, 2000], consisting of an input bandpass filter, two multipliers, two low-pass filters, two limiters, a delay line, a 90 ° phase shifter, and a parallel-serial converter.

The disadvantages of this analogue include the presence of a threshold effect that reduces noise immunity at an input signal-to-noise ratio close to unity.

Of the known devices similar to the claimed utility model, the closest in technical essence is the FMS demodulator according to the Kostas scheme [3 - B. Shakhtarin. "Synchronization in radio communications and radio navigation." - M .: Gemos ARV, 2007. - 256 s], taken as a prototype, containing the first, second and third multipliers, first and second low-pass filters, a loop filter, a first phase shifter, a controlled oscillator, a first controller, and the demodulator input is connected in parallel the output of the controlled generator is directly connected to the first inputs of the first and second multipliers, to the second input of the first multiplier, and the output of the controlled generator is connected to the second input of the second multiplier through the first phase shifter, the output of the first multiplier The amplifier is connected to the first input of the third multiplier through the first low-pass filter, the output of the second multiplier is connected to the second input of the third multiplier through the second low-pass filter, the output of the third multiplier is connected to the control input of the controlled generator through a cascade loop filter and the first controller, the output of the demodulator is the output first low pass filter.

The disadvantages of the prototype should include an increase in the time of regulation of the frequency of the controlled local oscillator to the demodulator entering synchronism in the case of receiving FMS with a large range of a priori uncertainty in Doppler frequency shift.

The technical result of creating a utility model is to reduce the time it takes for the controlled generator to go into synchronization with the FMS demodulation device at a fixed probability of erroneous decisions and to improve the performance of the demodulation device by using a digital element base with a low sampling frequency.

To achieve the technical result, a device for demodulating the FMS is proposed, comprising first, second and third multipliers, first and second low-pass filters, a loop filter, a first driver, a first phase shifter, a controlled oscillator, the device input being connected to the first inputs of the first and second multipliers, the output of the controlled generator is connected directly to the second input of the first multiplier, and the output of the controlled generator is connected to the second input of the second multiplier, through the helmet a bottom mounted first phase shifter, the output of the first multiplier is connected to the first input of the third multiplier through a cascaded first low-pass filter, the output of the second multiplier is connected to the second input of the third multiplier through a cascaded second low-pass filter, the output of the third multiplier is connected to the input of the controlled generator through cascaded loop filter, the first controller and the second adder.

According to the utility model, a solver, an autocorrelation frequency discriminator and a second adder are additionally introduced, the solver having two inputs and two outputs and consists of a fourth, fifth, sixth and seventh multipliers, a first and second delay line, a first adder, a first and a second subtractor , the third and fourth low-pass filters, the first functional converter and the second controller, and the first inputs of the fourth and net multipliers and the input of the first delay line, to the output of which the second inputs of the fourth and fifth multipliers are connected in parallel, the first inputs of the fifth and seventh multipliers and the input of the second delay line, the second inputs of the sixth and seventh multipliers are connected in parallel to the second input of the resolver , the first inputs of the first adder and the second subtractor are connected in parallel to the output of the fourth multiplier, the first input of the first is connected to the output of the fifth multiplier of the subtractor, the second input of the first subtracter is connected to the output of the sixth multiplier, the second input of the first adder and the second input of the second subtracter are connected in parallel to the output of the seventh multiplier, the output of the first adder is connected through the cascade-connected third low-pass filter to the first input of the first functional converter, the output of the first subtractor is the fourth low-pass filter cascaded on is connected to the second input of the first functional converter, the output of which is cascaded on The second manager is connected to the first output of the solver and then fed to the second input of the second adder, the output of the second subtractor is connected to the second output of the solver and then fed to the input of the autocorrelation frequency discriminator, which consists of the fifth, sixth and seventh low-pass filters, the second phase shifter , the third delay line, the eighth and ninth multipliers, the second functional converter and the third ruler, and the input of the autocorrelation frequency discrimination the nator is connected through the fifth low-pass filter, to the output of which the inputs of the second phase shifter, the third delay line and the first input of the ninth multiplier are connected in parallel, the second inputs of the eighth and ninth multipliers are connected in parallel to the output of the third delay line, the first input of the eighth multiplier is connected to the output of the second phase shifter, the output of which through the cascade-connected sixth low-pass filter is connected to the first input of the second functional converter, the output of the ninth multiplier through to the cascade-connected seventh low-pass filter is connected to the second input of the second functional converter, the output of which through a cascade-connected third controller is connected to the output of the autocorrelation frequency discriminator and then fed to the third input of the second adder, which is connected to the gap between the first controller and the controlled generator.

The figure shows a functional diagram of the claimed device for demodulation (UD).

In the claimed UD: 1 - the first multiplier P ₁ ; 2 - the first low-pass filter of the low-pass filter ₁ ; 3 - the fourth multiplier P ₄ ; 4 - the first adder Cym ₁ ; 5 - the third low-pass filter low-pass filter ₃ ; 6 - the first phase shifter Фв ₁ ; 7 - the third multiplier P ₃ ; 8 - loop filter PTF; 9 - the first delay line LZ ₁ ; 10 - the fifth multiplier P ₅ ; 11 - the first functional Converter FP ₁ ; 12 - second delay line LZ ₂ ; 13 - the sixth multiplier P ₆ ; 14 - the first subtracter of Calcul ₁ ; 15 - the fourth low-pass filter low-pass filter ₄ ; 16 - the second multiplier P ₂ ; 17 - the second low-pass filter of the low-pass filter ₂ ; 18 - seventh multiplier P ₇ ; 19 - the second subtractor Calcul ₂ ; 20 - the second ruler of Upr ₂ ; 21 - a controlled generator of UG; 22 - second adder Sum ₂ ; 23 - the first ruler of Upr ₁ ; 24 - decisive device RU; 25 - fifth low-pass filter low-pass filter ₅ ; 26 - the second phase shifter Фв ₂ ; 27 - the third delay line LZ ₃ ; 28, 29 - the eighth and ninth multipliers, respectively, P ₈ , P ₉ ; 30, 31 - the sixth and seventh low-pass filters, respectively, low-pass filter ₆ , low-pass filter ₇ ; 32 - the second functional converter FP ₂ , 33 - the third ruler Upr ₃ , 34 - autocorrelation frequency discriminator AFD.

The principle of operation of the claimed device is as follows.

At the input of the DD and the first and second multipliers (1) and (16), a phase-shifted signal is received

S (t) = U _ms P (t) cos (2πƒ _s t + φ _s ); ƒ _s = ƒ ₀ + ƒ _d ,

P (t) ∈ [-1; +1]

where U _ms , ƒ _s , φ _s - amplitude, frequency, initial phase of the signal S (t);

ƒ ₀ is the radiation frequency;

ƒ _d - Doppler frequency shift;

P (t) is a manipulating function, which is a sequence of positive and negative rectangular pulses with a unit amplitude and a duration of T _e .

The second inputs of the first and second multipliers (1) and (16) from the output of the UG (21) receive voltage

U _gf (t) = U _g cos (2πƒ _g t + φ _g ); ƒ _g ≈ƒ ₀ ,

U _gs (t) = U _s sin (2πƒ _g t + φ _g ),

where U _g , ƒ _g , φ _g - amplitude, frequency, initial phase of the voltage UG (21) at the time of signal reception.

After the signal passes through the quadrature channels of the DD at the inputs of the third multiplier (7), we have the processes

;

;

Δƒ → ƒд; Δφ = φ _s -φ _g ;

h _F1 (t) = 2ƒ _F1 sinc (πΔƒ _F1 t); ,

where h _Ф1 (t) is the impulse response of the low-pass filter ₁ (2), low-pass filter ₂ (17) with a passband Δƒ _Ф1 ;

Δƒ is the frequency mismatch;

Δφ is the phase mismatch;

K ₁ - transmission coefficient in quadrature channels.

After the processes U _c (t) and U _s (t) pass through P ₃ (7) and PTF (8), we obtain the mismatch voltage

;

h _Ф2 (t) = 2ƒ _Ф2 sinc (πΔƒ _Ф2 t); Δƒ _Ф2 ≥Δƒ,

where h _Ф2 (t) is the PTF impulse response (8) with a passband Δƒ _Ф2 .

Then, through Upr ₁ (23), the mismatch voltage is supplied to the control input of the UG (21) and since the feedback is closed, the process of regulating the frequency of the UG (21) begins in the phase-locked loop (PLL) before entering synchronism. The frequency control time T _p1 is determined from the following expression

; Δƒ _Z1 = Δƒd,

where Δƒ _w is the noise band of the PLL;

Δƒ _d is the range of a priori uncertainty of the Doppler frequency shift.

At Δƒ _d = 3 · 10 ³ Hz and Δƒ _w = 10 ² Hz, the PLL ensures synchronism (Δƒ _g → ƒ _s ) through T _p1 = 31.5 s, which is not acceptable when receiving packet phase-shifted signals.

In order to reduce the frequency regulation time, the claimed UD additionally introduces a resolver (24) and an autocorrelation frequency discriminator (34), which form a two-scale frequency discriminator.

The solver (24) provides a “rough” estimate of the frequency mismatch Δƒ, and the PSA (34) provides an “accurate” estimate of Δƒ.

In this case, after tuning, the frequency of UG (21) is where and - “rough” and “accurate” estimates of frequency mismatch.

The autocorrelation processing of quadrature components of the FMS in RU (24) consists of several operations, described as follows:

;

;

;

;

Δω = 2πΔƒ; τ _lz = T _e

where U ₁ (t, τ _lz ), U ₃ (t, τ _lz ), U ₂ (t, τ _lz ), U ₄ (t, τ _lz ) are the output voltages P ₇ (18), P ₆ (13 ), P ₅ (10), P ₄ (3);

k _s - transmission coefficient of multipliers P ₇ (18) P ₆ (13), P ₅ (10), P ₄ (3).

The stresses obtained above after processing in P ₇ (18), P ₆ (13), P ₅ (10), P ₄ (3), Sum ₁ (4), Vych ₁ (14), followed by averaging in low-pass filter ₃ (5) and low-pass filters ₄ (15) take the following form:

;

,

where U ₅ (T ₁ , T _e ), U ₆ (T ₁ , T _e ) are the voltage at the outputs of the low-pass filter ₃ (5) and low-pass filter ₄ (15);

T ₁ - integration constant of the low-pass filter ₃ (5) and low-pass filter ₄ (15).

The voltage at the output of Calcul ₂ (19) has the form

After converting the voltages U ₅ (T ₁ , T _e ) and U ₆ (T ₁ , T _e ) in the functional converter FP ₁ (11), we obtain at the output of Upr ₂ (20) the voltage U ₈ (T ₁ ) proportional to the “rough” estimate frequency mismatch

In Exit ₂ (20), a “rough” estimate of the frequency mismatch is formed , which is served on Sum ₂ (22) and then on UG (21).

At the input of the PSA (34), U ₇ (T ₁ , T _e ) enters through the low-pass filter ₅ (25), the impulse response of which has the form

h _Ф3 (t) = 2ƒ _Ф3 sinc (πΔƒ _Ф3 t); Δƒ _Ф3 ≥Δƒ _d ,

where Δƒ _Ф3 is the passband of the low-pass filter ₅ (25).

Processing voltage U ₇ (T ₁ , T _e ) is carried out in accordance with the following algorithm

; ;

;

;

; Δω ₂ = 2πΔƒ ₂ ,

where U ₉ (T ₂ ) is the voltage proportional to twice the "exact" estimate of the frequency mismatch at the output of FP ₂ (32);

U _sa (T ₂ , τ _lz2 ) and U _ca (T ₂ , τ _lz2 ) is the voltage of the quadrature components at the outputs of the low-pass filter ₆ (30) and low-pass filter ₇ (31);

T ₂ is the integration constant of the low-pass filter ₆ (30) and the low-pass filter ₇ (31);

U _7s (t) and U _7c (t) - voltage at the input P ₈ (28) and P ₉ (29);

K ₄ - transmission coefficient of the multipliers P ₈ (28) and P ₉ (29);

τ _lz2 is the time shift introduced by LZ ₃ (27);

Δƒ ₂ is the frequency mismatch in the AFD (34).

In Ex ₃ (33), an “exact” estimate of the frequency mismatch is formed which is fed to Sum ₂ (22) and then to UG (21).

The root mean square errors of frequency estimation in RU (24) and AFD (34) can be calculated from the following relations

; ; ; ;

; ; Δƒ _od = 4σƒ ₁ , with P _dov = 0.95;

; ,

where σƒ ₁ and σƒ ₂ are the root-mean-square errors of estimating the frequency mismatch in RU (24) and AFD (34);

g _BX is the input signal-to-noise ratio by voltage at the input of the detector;

g _d - the signal-to-noise ratio for voltage at the outputs of the low-pass filter ₁ (2) and low-pass filter ₂ (17);

g ₁ , g ₂ - signal-to-noise ratio at the outputs of FP ₁ (11) and FP ₂ (32);

Δƒ _od - the range of unambiguous estimation of frequency in the AFD (34);

g _a is the signal-to-noise ratio by voltage at the output of the low-pass filter ₅ (25);

P _dov - confidence probability.

The frequency control time of the UG (21) in the claimed UD is

T _p2 = T ₁ + T ₂ + T _PLL ; ,

where T _PLL - regulation time in PLL, corresponding in structure to the prototype.

We determine the time of frequency control of the UG (21) at Δƒ _d = 3 · 10 ³ Hz, Δƒ _ш = 10 ² Hz, T _e = 10 ^-6 s, g _d = 3.3, which ensures the probability of erroneous decisions in the UD P _osh = 10 ^-6 .

To ensure σƒ ₁ = 10 ² Hz, it is necessary to have T ₁ = 2.45 · 10 ^-2 s, to ensure σƒ ₂ = 25 Hz it is enough to have T ₂ = 1.5 · 10 ^-4 . Since this capture band of the PLL is determined at P = 0,94 Δƒ _{rows zah2} = 4σƒ ₂ and ² is 10 Hz, then this is obtained with the _PLL T = 5 · 10 ^-2 s, and the total amount of frequency control time T _p2 = 7 5 · 10 ^-2 s.

The results show that the claimed UD provides a reduction in the time of regulation of the frequency mismatch of the UG (21) by 420 times.

In addition, it should be noted that the processing of processes in switchgear (24) and AFD (34) is carried out in the field of video frequencies, which can significantly reduce the sampling frequency when switching to a digital element base and improve operational characteristics (mass, dimensions, power consumption) compared to the implementation of UD on an analog element base.

Thus, the implementation of the device for demodulating FMS does not cause difficulties. The presented diagram on the figure and a detailed description of the principle of operation of each unit, the implementation of which is possible on typical functional units using a modern element base, makes it possible to manufacture a device for FMS demodulation in an industrial way according to its purpose, which characterizes the utility model as industrially applicable.

Claims (1)

A device for demodulating phase-shifted signals containing the first, second and third multipliers, the first and second low-pass filters, a loop filter, a first controller, a first phase shifter, a controlled generator, the input of the device being connected to the first inputs of the first and second multipliers, to the second input of the first multiplier the output of the controlled generator is connected directly, and the output of the controlled generator is connected to the second input of the second multiplier through a cascade-mounted first phase shifter Eh, the output of the first multiplier is connected to the first input of the third multiplier through a cascaded first low-pass filter, the output of the second multiplier is connected to the second input of the third multiplier through a cascaded second low-pass filter, the output of the third multiplier is connected to the input of the controlled generator through a cascaded loop filter, the first controller and the second adder, characterized in that it additionally introduced a solver, an autocorrelation frequency discriminator and a second the adder, and the solver has two inputs and two outputs and consists of the fourth, fifth, sixth and seventh multipliers, the first and second delay lines, the first adder, the first and second subtractors, the third and fourth low-pass filters, the first functional converter and the second controller moreover, the first inputs of the fourth and sixth multipliers and the input of the first delay line, to the output of which the second inputs of the fourth and fifth of the second multipliers, the first inputs of the fifth and seventh multipliers and the input of the second delay line, the second inputs of the sixth and seventh multipliers are connected in parallel to the second input of the resolver, the first inputs of the first adder and the second subtracter are connected in parallel to the output of the fifth multiplier, the first input of the first subtractor is connected, the second input of the first subtracter is connected to the output of the sixth multiplier, to the output of the seventh steam multiplier the second input of the first adder and the second input of the second subtractor are connected in parallel, the output of the first adder through a cascade-connected third low-pass filter is connected to the first input of the first functional converter, the output of the first subtractor through a cascade-connected fourth low-pass filter is connected to the second input of the first functional converter, the output of which through a cascade-connected second controller connected to the first output of the deciding device and then fed to the second input of the second adder , the output of the second subtractor is connected to the second output of the resolving device and then fed to the input of the autocorrelation frequency discriminator, which consists of the fifth, sixth and seventh low-pass filters, the second phase shifter, the third delay line, the eighth and ninth multipliers, the second functional converter and the third controller, moreover, the input of the autocorrelation frequency discriminator is connected through the fifth low-pass filter, to the output of which the inputs of the second phase shifter are connected in parallel, the third delay line and the first input of the ninth multiplier, the second inputs of the eighth and ninth multipliers are connected in parallel to the output of the third delay line, the first input of the eighth multiplier is connected to the output of the second phase shifter, the output of which is connected in cascade to the sixth low-pass filter to the first input of the second functional converter, the output of the ninth multiplier through a cascade-connected seventh low-pass filter is connected to the second input of the second functional converter, you the path of which through a cascade-connected third controller is connected to the output of the autocorrelation frequency discriminator and then fed to the third input of the second adder, which is included in the gap between the first controller and the controlled generator.