PH12015501117B1 - Substrate for mounting semiconductor element and method for manufacturing said substrate - Google Patents
Substrate for mounting semiconductor element and method for manufacturing said substrate Download PDFInfo
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- PH12015501117B1 PH12015501117B1 PH12015501117A PH12015501117A PH12015501117B1 PH 12015501117 B1 PH12015501117 B1 PH 12015501117B1 PH 12015501117 A PH12015501117 A PH 12015501117A PH 12015501117 A PH12015501117 A PH 12015501117A PH 12015501117 B1 PH12015501117 B1 PH 12015501117B1
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- Philippines
- Prior art keywords
- resist layer
- light
- layer
- metal plate
- front surface
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims abstract description 79
- 238000007788 roughening Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000003746 surface roughness Effects 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 abstract description 14
- 229920005989 resin Polymers 0.000 abstract description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 239000007788 liquid Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 7
- 229910052753 mercury Inorganic materials 0.000 description 7
- 229910052763 palladium Inorganic materials 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000001994 activation Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910000029 sodium carbonate Inorganic materials 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Provided is a substrate for mounting a semiconductor element with enhanced adhesiveness between an electrode layer and resin and a method for manufacturing the substrate thanks to a substantially inverted-trapezoidal sectional shape and roughened side surfaces of the electrode layer. The method for manufacturing a substrate for mounting a semiconductor element includes following steps in sequence: a) a step of forming, on a front surface of a metal plate, a two-layered resist layer formed of a lower resist layer and an upper resist layer by using resists each having a different main photosensitive wavelength; b) a step of light-exposing the upper resist layer in a predetermined pattern while the lower resist layer is in a non-light exposed state; c) a developing step of forming openings in a predetermined pattern in the upper resist layer and forming further openings with the pattern of the upper resist layer in the non-light-exposed lower resist layer to partially expose the front surface of the metal plate; d) a step of light-exposing and curing the lower resist layer; e) a step of forming predetermined plated layers on the front surface of the metal plate exposed from the lower resist layer; f) a step of entirely peeling off the two-layer resist layer formed of the lower resist layer and the upper resist layer; and g) a step of roughening side surfaces of each of the plated layer formed in the step (e).
Description
¢ ' ’ ry 1.1 on mounting with better adhesiveness to resin can be easily zo obtained. =
Figure 1-1 illustrates diagrams depicting a method - for manufacturing a substrate for semiconductor element o mounting of the present invention for each step: (1) is £0 a sectional view showing a lower resist layer 30 formed = on a front surface of a metal plate and a rear-surface = resist layer 30a formed on a rear surface thereof in a step (a); (2) dis a sectional view showing an upper resist layer 40 formed on a front surface side of the metal plate and having a main photosensitive wavelength different from that of a lower resist layer 30 previously formed in a step (a); (3) is a sectional view in a light-exposing step as a step (b), wherein the front surface side is covered with a mask 50 in a predetermined pattern, a band-pass filter 60 is provided between a light source (not shown) and the mask, and thereby the upper resist layer 40 is irradiated only with ultraviolet light having a main wavelength required for 1light-exposing the upper resist layer 40, of ultraviolet light from the light source, while the entire surface on a rear surface side is exposed to light; (4) is a sectional view in a developing step as a step (c), wherein by performing development, openings are formed in a predetermined pattern in the upper resist layer 40, through the openings the lower resist layer 30 in a non-light-exposed state is then developed, and the front surface of the metal plate is partially exposed, so that, a lower resist layer 3la having a sectional shape of each opening being an inverted trapezoid is formed; (5) is a sectional view showing the oo 5 — 1.1 lower resist layer 31a in the non-light-exposed state light-exposed and cured in a step (d); and (6) is a = sectional view showing a plated layer 10 formed on the Ee front surface of the exposed metal plate in a step (e). =
Figure 1-2 illustrates diagrams continued from -
Figure 1-1, depicting the method for manufacturing the bot substrate for semiconductor element mounting of the = present invention for each step: (7) is a sectional view ~ in a step (f), wherein all resist layers provided to the - metal plate are peeled off and the plated layer having a substantially inverted trapezoidal shape in section is formed on the front surface of the metal plate; (8) is a sectional view showing side surfaces of the plated layer 10 roughened by using a selective etchant in a step (9); and (9) is a sectional view showing a substrate 1 for semiconductor element mounting according to the present invention with the side surfaces of the plated layer being roughened surfaces.
Figure 2 illustrates detailed explanatory diagrams showing the lower resist layer with an inverted- trapezoid sectional shape in the step (c) (developing step) of Figure 1-1(4): (1) is a sectional view in which an upper resist layer 41 with openings is formed by development and, through the openings, a liquid developer is in contact with the front surface of the lower resist layer 30 in the non-light-exposed state; and (2) to (5) are sectional views each depicting flowing of a liquid developer and, as depicted in (5), the lower resist layer 3la in the non-light-exposed state is formed with openings each having an inverted trapezoid shape in section.
Lr —
Lr
Figure 3 is a diagram for describing a typical = example of a substantially trapezoidal sectional shape = of the resist layer according to the present invention. oe
Description of Embodiments w
Next, embodiments of the method for manufacturing oO a substrate for mounting a semiconductor element of the oy present invention are described based on Figure 1-1, =
Figure 1-2, and Figure 2. i [Step (a)] (Formation of Lower Resist Layer)
First, as depicted in the sectional view of Figure 1-1(1), of a lower resist layer 30 and an upper resist layer 40 having a thickness higher than a necessary height of a plated layer 10, the lower resist layer 30 is formed on a front surface of a metal plate 20 on a side where the plated layer 10 is formed in a later step.
Here, a resist layer 30a of the same resist as that of the lower resist layer 30 may be provided also on a rear surface of the metal plate.
This lower resist layer 30 is a resist layer photosensitive with an i line, an h line, or a g line, and is a resist layer in a pre-development state.
By making the thicknesses of these lower resist layer 30 and the upper resist layer 40 higher than a height required for the plated layer 10, the plated layer 10 having a section in an inverted-trapezoidal shape and having the necessary height can be reliably formed. (Formation of Upper Resist Layer)
Next, as depicted in Figure 1-1(2), the upper resist layer 40 is formed on the lower resist layer 30 on a side where the plated layer 10 is to be provided,
¢ :
LA
” by using a resist having a main photosensitive = wavelength different from that of the lower resist layer = 30. i. [Step (b)] =
Next, as depicted in Figure 1-1(3), by using a mask 50 having a predetermined pattern formed therein, the upper resist layer 40 is exposed to light with a oo predetermined pattern. Here, the lower resist layer 30 = is in a non-light-exposed state. =
To expose this upper resist layer 40 to light, for a light source of a mercury lamp (for example, ultraviolet light 70), a band-pass filter 60 is used which lets only a main wavelength for light-exposing the upper resist layer 40 without light-exposing the lower resist layer 30, thereby allowing only the upper resist layer 40 to be exposed to light, with the lower resist layer 30 being left in a non-light-exposed state.
Note that the rear-surface resist layer 30a provided on the rear surface of the metal plate is also exposed to light with the ultraviolet light 70 to form a cured rear-surface resist layer 30b. [Step (c): Developing Step]
Next, as depicted in Figure 1-1(4), an upper resist layer 41 having openings in a predetermined pattern is formed by performing development. Here, the lower resist layer 30 in a non-light-exposed state becomes a lower resist layer 3la in which development proceeds from the openings of the upper resist layer 41 to partially expose the front surface of the metal plate 20.
With this process, the lower resist layer 31 becomes 3la having openings with a section being in a substantially inverted-trapezoidal shape. Note that the substantially inverted-trapezoidal shape in the present
LA on invention refers to a shape in which a maximum value of ~ the resist layer width is present above the width of the 2 bottom side (side in contact with the metal plate 20) in i a section of the resist layer, and its typical shape is oT depicted in Figure 3. v [Details of Developing Step] iy
Here, details of the developing step are described = by using Figure 2, in which the lower resist layer 31la = in Figure 1-1(4) described above has an inverted o trapezoidal sectional shape.
In the developing step as a step (cc), as depicted in Figure 2(1), the resist layer 41 having openings is formed by first developing the upper resist layer, and then a liquid developer 80 is brought into contact with the lower resist layer 30.
Next, as depicted in Figure 2(2), the liquid developer 80 flows to cause the lower resist layer 30 to be dissolved and removed downwardly, and the liquid developer 80 also flows in a lateral direction.
Furthermore, as depicted in Figure 2(3), the liquid developer 80 flows in a swirl shape to remove the lower resist layer 30 so that its section is shaped in an arc.
Then, as depicted in Figure 2(4), the lower resist layer 30 exposes the metal plate 20, and the liquid developer 80 removes the lower resist layer 30 in a lateral direction.
As a result, as depicted in Figure 2(5), the lower resist layer 3la in a non-light-exposed state with openings each having a sectional shape being an inverted trapezoid is formed. [Step (d)]
[a -
Next, as depicted in Figure 1-1(5), the entire - surface of the lower resist layer 3la having the non- © light-exposed openings are exposed to light by using a mercury lamp as a light source (for example, ultraviolet oy light) and cured, thereby forming the lower resist layer = 31. o [Step (e)] =
Next, as depicted in Figure 1-1(6), after pre- = plating process is performed on the front surface of the - exposed metal plate 20, the plated layer 10 having a required height is formed.
The plated layer may be formed by laminating a plurality of plated layers, and can be formed by selecting plating with gold, silver, palladium, nickel, copper, cobalt, and the like and an alloy thereof and sequentially laminating layers. [Step (f)]
After the plated layer 10 is formed, as depicted in
Figure 1-2(7), all of the resist layers 31, 41, and 30b are removed, thereby forming the plated layer 10 having a sectional shape being a substantially inverted trapezoidal shape on the front surface of the metal plate 20. [Step (9)]
Then, as depicted in Figure 1-2(8), by using a selective etchant (100), the metal plate 20 having the plated layer 10 in a substantially-inverted-trapezoidal shape is processed to make side surfaces of the plated layer 10 as roughened surfaces 90. Thus, the substrate 1 for semiconductor element mounting with a sectional shape being an inverted trapezoid and side surfaces being the roughened surfaces 90 depicted in Figure 1-
co | A or - 2(9) can be fabricated on the upper surface of the metal 7 plate 20. py
The selective etchant for providing asperities on > the side surfaces of the plated layer can be selected = according to the type of the plated layer. Hw
Note that, regarding light exposure, by using an - ultraviolet LED lamp with a specific wavelength without — using a mercury lamp as a light source, the upper-layer © resist layer can also be exposed to light without using o a band-pass filter. ;
By using examples, the present invention is further described below. <Example 1>
SUS430 having a thickness of 0.15 mm was used as the metal plate 20, and a film resist (manufactured by
Asahi Kasei E-materials Corporation: AQ-5038) having a thickness of 50 um was laminated to both surfaces to form the lower resist layer 30 and the resist layer 30a on the rear surface of the metal plate. Lamination conditions were such that the roll temperature was 105°C, the roll pressure was 0.5 MPa, and the feed speed was 2.5 m/min. Note that the laminated film resist is a negative-type resist, and is a resist capable of light exposure with i-line radiation (wavelength: 365 nm) (refer to Figure 1-1(1)).
Next, a film resist (manufactured by Asahi Kasei
E-materials Corporation: ADH-252) having a main photosensitive wavelength different from that of the lower resist layer 30 having a thickness of 25 um was laminated only on a front surface (surface where the plated layer 10 is to be formed later) side of the metal plate formed with the lower resist layer 30 so as to be
: i57 ge superposed on the lower resist layer 30 under the same - conditions as those of the lower resist layer 30 to form o the upper resist layer 40. This film resist is also a i. negative-type resist, but is a resist capable of light oo exposure with h-line radiation (wavelength: 405 nm). +
Thus, the state is such that a resist layer (the - lower resist layer 30 and the upper resist layer 40) = formed of two layers with different main photosensitive = wavelengths is formed on the front surface side of the - metal plate 20 where the plated layer 10 is to be formed - and the rear-surface resist layer 30a is formed on a rear surface side, with the same resist as that of the lower resist layer 30 on the front surface side (refer to Figure 1-1(2)).
Next, the mask 50 having a predetermined pattern formed was put over the upper resist layer 40 on the front surface side, and the band-pass filter 60 having a transmission wavelength of 405 nm was set between the mask 50 and a light source for light exposure.
Then, light exposure was performed by using, as a light source, a mercury lamp (manufactured by Oak
Corporation: short arc lamp) with the mixed-line ultraviolet light 70 in which a peak wavelength includes an 1 line, an h line, and a g line. By using ultraviolet light having a transmission wavelength of 405 nm, the upper resist layer 40 on the front surface side was exposed to light in a predetermine pattern with an exposure amount of 10 mJ/cm?® to 20 mJ/cm? and cured. On the other hand, on the rear surface side, the entire surface of the resist layer 30a was exposed to light by the same light source (the ultraviolet light 70) with a wavelength of 365 nm and an exposure amount of 60 mJ / cm? and cured to form the rear-surface resist layer 30b.
© on
Here, the front surface side is exposed to light =o with h-line radiation 71 by the band-pass filter 60 = having a transmission wavelength of 405 nm, and the py lower resist layer 30 is not exposed to light and in a gc non-light-exposed state. The rear surface side becomes = the rear-surface resist layer 30b with the entire o ‘surface cured by light exposure with the mixed-line = ultraviolet light 70 (refer to Figure 1-1(3)). =
Next, development is performed, and the upper ow resist layer 40 on the front surface side is formed into a predetermined pattern and becomes the upper resist layer 41 having openings (refer to Figure 1-1(4)).
Then, in the lower resist layer 30 in a non-light- exposed state, development proceeds from the openings of the upper resist layer 41 as depicted in Figure 2, and the front surface of the metal plate 20 is exposed. With this process, the lower resist layer 3la on the front surface side has openings each having a sectional shape being an inverted trapezoid.
In this developing process, process was performed with a 1% sodium carbonate solution at a solution temperature of 30°C and a spray pressure of 0.08 MPa for approximately eighty seconds.
Next, the lower resist layer 31 was formed by light-exposing and curing the entire surface of the lower resist layer 3la in a non-light-exposed state having the openings formed therein on the front surface side by using the mixed-line ultraviolet light 70 (refer to Figure 1-1(5)).
Then, after removal of a surface-oxidized coating formed on the front surface of the metal plate 20 exposed from the lower resist layer 31 having the openings formed in a predetermined pattern on the front i. surface side and a surface activation process by a - general pre-plating process were performed, plating was & performed in a sequence of gold plating of 0.05 um, palladium plating of 0.05 pm, nickel plating of 1 pm, eT copper plating of 35 um, nickel plating of 1 pm, = palladium plating of 0.05 pm, and gold plating of 0.03 o pm to form the plated layer 10 formed of a plurality of oy layers (refer to Figure 1-1(6)). =
Then, all of the resist layers 31, 41, and 30b o formed on both surfaces of the metal plate 20 were peeled off with an alkaline solution to form the plated layer 10 having a sectional shape being a substantially inverted trapezoidal shape on the front surface of the metal plate 20 (refer to Figure 1-2(7)).
As depicted in Figure 1-2(8), a copper-roughening etchant (CZ-8100 manufactured by MEC CO., Ltd.) was used to process the metal plate 20 having the plated layer 10 having inverted-trapezoidal shapes formed thereon, thereby forming the roughened surfaces 90 on the side surfaces of the plated layer 10.
With this, the substrate 1 for semiconductor element mounting (refer to Figure 1-2(9)) having a sectional shape being a substantially inverted trapezoidal shape and the roughened surfaces 90 on the side surfaces can be obtained on the front surface of the metal plate 20.
And, an angle formed by an oblique side of the formed plated layer 10 having a sectional shape being in a substantially inverted trapezoidal shape and the metal plate was 65 degrees to 70 degrees, and the surface roughness of asperity parts of the side surface parts was 0.4 pm to 0.5 pum in SRa.
LT
E
The roughness was measured by OLS-3000 of OLYMPUS -
CORPORATION, a scanning-type confocal infrared laser 5 microscope. oo
Also, in the developing process, by changing a Ty development time, pressure conditions, and other ow conditions, it was possible to control the angle and i dimensions of the substantially inverted trapezoidal = shape of the lower resist layer and, with the angle = between the oblique side of the plated layer 10 and the o metal plate being any angle from 25 degrees to 90 degrees, it was possible to perform fabrication with extremely small unevenness.
In the present example, the resist layer capable of light exposure with i-line radiation identical to that of the lower resist layer 30 on the front surface side is formed on the rear surface side of the metal plate 20. However, this is not necessarily restrictive because the mixed-line mercury lamp including an i line, an h line, and a g line is used as a light source, and a resist layer of any type may be formed as long as the photosensitive wavelength is different from that of the upper resist layer 40. Furthermore, since the entire surface of the resist layer formed on the rear surface side is cured, using a resist of any type does not pose a problem. <Example 2>
SUS430 having a thickness of 0.15 mm was used as the metal plate 20, and two film resists (manufactured by Asahi Kasei E-materials Corporation: BAQ-4096) each having a thickness of 38 um were laminated on the front surface side of the metal plate and one same film resist was laminated on the rear surface side, thereby forming
Lr on the lower resist layer 30 having a thickness of 76 um on =o : the front surface side and the rear-surface resist layer = 30a having a thickness of 38 pum on the rear surface side. oo
Lamination conditions were such that the roll or temperature was 105°C, the roll pressure was 0.5 MPa, and sv the feed speed was 2.5 m/min. 0
Next, a film resist (manufactured by Asahi Kasei _
E-materials Corporation: ADH-252) having a thickness of = 25 pm was laminated on the front surface of the metal - plate 20 so as to be superposed on the lower resist layer 30 under the same conditions as those of the lower resist layer to form the upper resist layer 40.
Next, from above the upper resist layer 40 on the front surface side, the mask 50 formed with a predetermined pattern was used to perform light exposure with h-line radiation, and the entire surface on the rear surface side was exposed to light, thereby light- exposing and curing the upper resist layer 40 on the front surface side in a predetermined pattern. The entire surface of the rear-surface resist layer 30a on the rear surface side was cured to be made as the rear- surface resist layer 30b. The light exposure method was such that, as with Example 1, a mercury lamp was used as a light source, and a band-pass filter having a photosensitive wavelength of 405 nm was set between the light source and the mask 50 on the front surface side, thereby letting only the h line pass through. Here, the lower resist layer 30 on the front surface side is in a non-light-exposed state.
Next, development is performed, and the upper resist layer 40 on the front surface side becomes the upper resist layer 41 having openings formed in a predetermined pattern. Then, in the lower resist layer on — 30 in a non-light-exposed state, development proceeds - from the openings of the upper resist layer 41 to expose : the front surface of the metal plate 20. With this o process, the lower resist layer becomes the lower resist pr layer 3la including the openings each having a sectional w shape being an inverted trapezoid. o
The development process was performed under = specific conditions of a 1% sodium carbonate solution at = a solution temperature of 30°C and a spray pressure of - 0.08 MPa for approximately eighty seconds.
Next, the entire surface of the lower resist layer 3la on the front surface side was light-exposed by the mercury lamp to form the lower resist layer 31 by curing the lower resist layer 3la having a section being an opening in an inverted trapezoidal shape. In this case, normal light exposure was performed in a state without the above-described band-pass filter.
Then, after a surface activation process by a general pre-plating process was performed on the front surface of the metal plate 20 exposed from the lower resist layer 31 formed in a predetermined pattern, gold plating of 0.05 um, palladium plating of 0.1 pm, nickel plating of 65 pum, and palladium plating of 0.1 pum were performed to form the plated layer 10.
Then, all of the lower resist layer 31, the upper resist layer 41, and the rear-surface resist layer 30b formed on both surfaces of the metal plate 20 were peeled off with an alkaline solution to form the plated layer 10 having a sectional shape being a substantially inverted trapezoidal shape on the front surface of the metal plate 20.
Furthermore, as depicted in Figures 1(8) and 1(9), a nickel-roughening etchant 100 (manufactured by MEC CO.,
n g
Ltd.: NR-1870) was used to perform a roughening process - on the metal plate 20 having the plated layer 10 in an & inverted-trapezoidal shape formed thereon, thereby forming the roughened surfaces 90 on the side surfaces Pon of the plated layer 10 and fabricating the substrate 1 = for semiconductor element mounting having a sectional i shape being a substantially inverted trapezoidal shape - and the roughened surfaces on the side surfaces on the = front surface of the metal plate. o
An angle formed by an oblique side of the formed plated layer 10 having a section being in a substantially inverted trapezoidal shape and the metal plate 20 was 65 degrees to 70 degrees, and the surface roughness of asperity parts of the side surface parts was 0.4 um to 0.5 pm in SRa.
The roughness was measured by OLS-3000 of OLYMPUS
CORPORATION, a scanning-type confocal infrared laser microscope.
Also, as with the above-described Example 1, in the developing process, by changing the development time, pressure conditions, and other conditions, it was possible to control the angle and dimensions of the substantially inverted trapezoidal shape of the lower resist layer and, with the angle between the oblique side of the plated layer 10 and the metal plate being any angle from 25 degrees to 90 degrees, it was possible to perform fabrication with extremely small unevenness.
Reference Signs List 1 substrate for semiconductor element mounting 10 plated layer 20 metal plate o on
30 lower resist layer (lower layer of a resist ol layer in a non-light-exposed state, laminated on the = metal plate) iu 30a rear-surface resist layer (resist layer = provided on a rear surface side of the metal plate - having the lower resist layer 30 provided on a front surface thereof) vo 30b rear-surface resist layer cured by light- = exposing and curing the rear-surface resist layer 30a =
31a lower resist layer (resist layer obtained by forming the lower resist layer 30 in a non-light- exposed state into a predetermined pattern [openings] by development)
31 lower resist layer (resist layer formed after the entire surface of the lower resist layer 3la is light-exposed and having cured openings)
40 upper resist layer (upper layer of the resist layer in a non-light-exposed state, formed on the lower resist layer 30)
41 upper resist layer (cured resist layer formed into a predetermined pattern (openings) by light- exposure and development of the upper resist layer 40)
50 mask 60 band-pass filter 70 ultraviolet light 71 ultraviolet light having a specific wavelength after passing through the band-pass filter 80 liquid developer 90 roughened surface
100 bonding rare-metal plating (selective etchant)
’ oA ’ | - N hey . Ln
SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD
FOR MANUFACTURING SAID SUBSTRATE' BR
Ce Aga
Tn
Description oS le NL
S oT a iL a . oN ~
Technical Field aN
The present invention relates to a substrate for IK; mounting a semiconductor element, thee substrate = including a plated layer serving as a terminal or the - like on a front surface of a metal plate, and a method = for manufacturing the substrate.
It is known that a substrate for semiconductor element mounting is formed by forming a resist mask subjected to predetermined patterning on one surface side or both surface sides of a conductive base material, forming a metal layer for semiconductor element mounting and an electrode layer for connecting outside by electrically depositing a conductive metal on the base material exposed from the resist mask, and removing the resist mask; resin sealing is performed after a : semiconductor element is mounted on the formed substrate for semiconductor element mounting and wire-bonding is performed; the base material is removed; and a semiconductor device is obtained with a rear surface side of the conductive metal electrically deposited on a resin side being exposed.
PTL 1 describes that by electrically depositing a conductive metal as exceeding a formed resist mask, a substrate for semiconductor element mounting is obtained which has an overhanging portion on the perimeter of an upper-end portion of a metal layer for semiconductor
Lo » rl : oe element mounting and an electrode layer for connecting ~ } outside, and the overhanging portion of the metal layer & and the electrode layer is jammed into the resin at the time of resin sealing so as to be reliably left on a oo) resin side. w
PTL 2 describes that when a resist mask is formed, - scattered ultraviolet light is used to form the resist = mask into a trapezoid, thereby forming a metal layer or = an electrode layer into an inverted trapezoidal shape. " -
Patent Literature
PTL 1: Japanese Patent Application Laid-Open No. 2002-9196
PTL 2: Japanese Patent Application Laid-Open No. : 2007-103450
In the method for electrically depositing the conductive metal as exceeding the resist mask described in PTL 1, a plated layer to be formed is formed by overhanging its resist mask, and it is difficult to control its overhanding amount, thereby posing problems in which the entire plated layer to be formed does not have the same canopy length and that when the overhanging portion is increased, the overhanging portion is linked to its adjacent plated layer. Moreover, when the plated layer is thinned, the thickness of the overhanging portion is also decreased. Therefore, there is also a problem of a decrease in adhesiveness to resin.
And, since the overhung upper surface of the plated :
a —— c : | —
LAT layer is in a spherical shape in relation to a growth 7 ratio of plating between a vertical direction and a = lateral direction, this can become a factor in degrading reliability of bonding. oy
Also, the method for forming a sectional shape of He an opening of the resist layer into a trapezoid by using oO scattered ultraviolet light described in PTL 2 is I. effective for the thickness of the resist layer for use > up to a thickness on the order of 25 pm, and the - thickness of the metal layer or the electrode layer is up to on the order of approximately 20 um. For example, when the resist layer is thickened to be on the order of 50 pm, light is more attenuated as ultraviolet light is absorbed to the resist to become more in a base-material direction. Therefore, the angle of the trapezoid, which is a sectional shape of the opening, becomes close to 90 degrees (that is, a rectangle) and, furthermore, longer, and the shape becomes an ordinarily trapezoidal shape with a short upper side, thereby causing the shape of the metal layer or the electrode layer not to be an inverted trapezoid, thereby resulting in a decrease in adhesiveness between the metal layer or the electrode layer and the resin.
To more increase this adhesiveness between the electrode layer and the resin, it is effective to thicken the thickness of the electrode layer, provide an electrode shape with a sectional shape being an inverted trapezoidal shape so as to be further jammed into the resin, and give a roughened-surface property capable of increasing an adhesive area to resin to the front surface of the electrode.
That is, an inverted-trapezoidal resist layer can be formed also by using a resist having a thickness
EY B E oi : - equal to or more than 25 um so that the electrode layer - can be thickened. Furthermore, by giving roughened- - surface shapes to side surfaces of the electrode, a substrate for mounting a semiconductor element can be = manufactured in which the electrode layer having a He thickness on the order of 5 pm to 100 pm (a side where - the plated layer 10 is to be formed later) has a _ sectional shape being an inverted trapezoidal shape and @ the side surfaces are formed as roughened surfaces. =
Thus, the method for manufacturing a substrate for - mounting a semiconductor element of the present invention has been made in view of the problems described above. With a sectional shape of an electrode layer being a substantially inverted trapezoidal shape and side surfaces thereof formed as roughened surfaces, a substrate for mounting a semiconductor element with enhanced adhesiveness between the electrode layer and resin is provided.
Solution to Problems
Thus, a first aspect of the method for manufacturing a substrate for mounting a semiconductor element, the method including following steps (a) to (g) in sequence: (a) a step of forming a laminated resist layer on a front surface of a metal plate, the laminated resist layer being formed of two layers of a lower resist layer and an upper resist layer by using two types of resists, each resist having a different wavelength as a main photosensitive wavelength; (b) a step of light-exposing the upper resist layer in a predetermined pattern while the lower resist layer is in a non-light-exposed state;
¢ | : | a
Lr ’ (c) a developing step of forming openings in a - predetermined pattern in the upper resist layer and, = through the openings, forming further openings with the ~ pattern of the upper resist layer in the non-light- oo exposed lower resist layer to partially expose the front = surface of the metal plate; (d) a step of light-exposing and curing the lower - resist layer; = (e) a step of forming predetermined plated layers ~ on the front surface of the metal plate exposed from the - lower resist layer; (f) a step of peeling off all of the resist layers including the two-layered resist layer of the lower resist layer and the upper resist layer; and (dg) a step of roughening side surfaces of each of the plated layers formed in the step (e).
A second aspect of the present invention provides the method for manufacturing the substrate for mounting a semiconductor element, wherein in the developing step (c) of the first aspect, in the lower resist layer, the lower resist layer is provided with the openings by partially exposing the front surface of the metal plate with the development proceeding in the lower resist layer from the openings provided in the upper resist layer, so that the openings provided in the lower resist layer each have an inverted trapezoidal shape in cross- section.
A third aspect of the present invention provides the method for manufacturing the substrate for mounting a semiconductor element, the two-layered resist layer with the lower resist layer and the upper resist layer combined together in the first and second aspects has a
_— em ye i ge thickness larger than a thickness of the plating formed - on the front surface of the metal plate in the step (e). @
A fourth aspect of the present invention provides on the method for manufacturing the substrate for mounting oT a semiconductor element, wherein in the step (b) of the + first to third aspects, a filter is provided between a - light source for light exposure and a mask having the = predetermined pattern formed thereon, the filter = extracting light of a predetermined wavelength from - light of the light source, and the upper resist layer is only exposed by the light of the predetermined wavelength extracted through the filter.
A fifth aspect of the present invention is the method for manufacturing the substrate for mounting a semiconductor element, wherein in the step (g) of the first to fourth aspects, pattern side surfaces of each of the plated layers formed by performing desired plating at each part exposed on the front surface of the metal plate are treated with a selective etchant, so that roughened surfaces are formed on the pattern side surfaces.
A sixth aspect of the present invention provides a substrate for mounting a semiconductor element, the substrate being manufactured by the following steps in sequence: a step of forming a laminated resist layer on a front surface of the metal plate, the laminated resist layer being formed of two layers of a lower resist layer and an upper resist layer, by using resists each having a different main photosensitive wavelength; a step of light-exposing the upper resist layer in a predetermined pattern while the lower resist layer is in a non-light- exposed state; a developing step of forming openings in a predetermined pattern in the upper resist layer and,
Ln through the formed openings, forming further openings with the pattern of the upper resist layer in the non- - light-exposed lower resist layer to partially expose the - front surface of the metal plate; a step of light- © exposing and curing the lower resist layer; a step of y forming a plurality of plated layers on the front surface of the metal plate exposed from the lower resist = layer; a step of peeling off all of the resist layers - including the two-layered resist layer of the lower = resist layer and the upper resist layer; and a step of roughening side surfaces of each of the formed plated layers, wherein the plated layers each have a substantially inverted trapezoid shape in cross-section and the side surfaces of roughened surfaces.
A seventh aspect of the present invention provides a substrate for mounting a semiconductor element, wherein in the plurality of plated layers formed on the front surface of the metal plate in the sixth aspect, a plated layer which occupies a portion with a largest plated layer thickness is formed of copper, nickel, or an alloy composition thereof.
According to the method for manufacturing a substrate for semiconductor element mounting, while following conventional processes roughly, a plated layer f having an inverted-trapezoidal sectional shape is formed and the side surfaces of the plated layer are roughened : with a selective etchant, and thereby causing sealing resin to enter recesses on roughened surfaces of side surfaces of a terminal in addition to a mold lock function due to the inverted-trapezoidal sectional shape, and as a result, a substrate for semiconductor element
Claims (4)
- > ~ : me, ' ‘ ‘ . ‘ An. . x CLAIMS px A method for manufacturing a substrate for mounting a semiconductor element, the method comprising following steps (a) to (g) in sequence:(a) a step of forming a laminated resist layer on a front surface of a metal plate, the laminated resist layer being formed of two layers of a lower resist layer and an upper resist layer by using two types of resists,each resist having a different wavelength as a main photosensitive wavelength;(b) a step of light-exposing the upper resist layer in a predetermined pattern while the lower resist layer is in a non-light-exposed state;(c) a developing step of forming openings in a predetermined pattern in the upper resist layer and, through the openings, forming further openings with the pattern of the upper resist layer in the non-light- exposed lower resist layer to partially expose the front surface of the metal plate;(d) a step of light-exposing and curing the lower resist layer;(e) a step of forming laminated plated layers on the front surface of the metal plate exposed from the lower resist layer, the laminated plated layers having a sectional shape being a substantially inverted trapezoidal shape, an angle formed between an oblique side of the laminated plated layer and the metal plate being in a range of 25 degrees to 90 degrees;(f) a step of peeling off all of the resist layers including the two-layered resist layer of the lower resist layer and the upper resist layer; and(g) a step of roughening side surfaces of each of the laminated plated layers formed in the step (e) to have a surface roughness (SRa) of 0.4 pum to 0.5 um.
- 2 The method for manufacturing a substrate for mounting a semiconductor element according to claim 1, wherein in the developing step (c), the lower resist layer is provided with the openings by partially exposing the front surface of the metal plate with the development proceeding in the lower resist layer from the openings provided in the upper resist layer, so that the openings provided in the lower resist layer each have an inverted trapezoidal shape in cross-section. BN
- 3. The method for manufacturing a substrate for mounting a semiconductor element according to claim 1 or 2, wherein the two-layered resist layer with the lower resist layer and the upper resist layer combined together has a thickness larger than a thickness of the plating formed on the front surface of the metal plate in the step (e).A 4. The method for manufacturing a substrate for mounting a semiconductor element according to Claims 1 or 2, wherein in the step (b), a filter is provided between a light source for light exposure and a mask having the predetermined pattern formed thereon, the filter extracting light of a predetermined wavelength from light of the light source, and the upper resist layer is only exposed by the light of the predetermined wavelength extracted through the filter.xX O- The method for manufacturing a substrate for \ mounting a semiconductor element according to Claims 1 or 2, wherein in the step (g), pattern side surfaces of each of the laminated plated layers formed by performing desired plating at each part exposed on the front surface of the metal plate are treated with a selective etchant, so that roughened surfaces are formed on the pattern side surfaces.6. A substrate for mounting a semiconductor element, the substrate comprising laminated plated layers on a front surface of a metal plate, wherein the laminated plated layers have a sectional shape being a substantially inverted trapezoidal shape and an angle formed between an oblique side of the laminated plated layer and the metal plate is in a range of 65 degrees to 70 degrees, and wherein the laminated plated layers each have side surfaces of roughened surfaces having a surface roughness (SRa) of 0.
- 4 pm to 0.5 um7. The substrate for mounting a semiconductor element according to claim 6, wherein in the plurality of plated layers formed on the front surface of the metal plate and constituting the laminated plated layers, a plated layer which occupies a portion with a largest plated layer thickness is formed of copper, nickel, or an alloy composition thereof.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012254654A JP6099369B2 (en) | 2012-11-20 | 2012-11-20 | Semiconductor device mounting substrate and manufacturing method thereof |
| PCT/JP2013/079765 WO2014080745A1 (en) | 2012-11-20 | 2013-11-01 | Substrate for mounting semiconductor element and method for manufacturing said substrate |
Publications (2)
| Publication Number | Publication Date |
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| PH12015501117B1 true PH12015501117B1 (en) | 2015-08-17 |
| PH12015501117A1 PH12015501117A1 (en) | 2015-08-17 |
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|---|---|---|---|
| PH12015501117A PH12015501117A1 (en) | 2012-11-20 | 2015-05-20 | Substrate for mounting semiconductor element and method for manufacturing said substrate |
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| Country | Link |
|---|---|
| JP (1) | JP6099369B2 (en) |
| KR (1) | KR101691763B1 (en) |
| CN (1) | CN104813465A (en) |
| MY (1) | MY169149A (en) |
| PH (1) | PH12015501117A1 (en) |
| TW (1) | TWI637424B (en) |
| WO (1) | WO2014080745A1 (en) |
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| CN109378270A (en) * | 2018-09-29 | 2019-02-22 | 大连芯冠科技有限公司 | The preparation method of the more field plates of power device |
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| JP3626075B2 (en) * | 2000-06-20 | 2005-03-02 | 九州日立マクセル株式会社 | Manufacturing method of semiconductor device |
| JP2002374066A (en) * | 2001-06-14 | 2002-12-26 | Ibiden Co Ltd | Method for manufacturing multilayered printed circuit substrate |
| JP3960302B2 (en) * | 2002-12-18 | 2007-08-15 | Ｔｄｋ株式会社 | Substrate manufacturing method |
| WO2006009030A1 (en) * | 2004-07-15 | 2006-01-26 | Dai Nippon Printing Co., Ltd. | Semiconductor device and semiconductor device producing substrate and production methods therefor |
| JP4508064B2 (en) * | 2005-09-30 | 2010-07-21 | 住友金属鉱山株式会社 | Manufacturing method of wiring board for semiconductor device |
| JP5370330B2 (en) * | 2010-10-01 | 2013-12-18 | 住友金属鉱山株式会社 | Manufacturing method of semiconductor device mounting substrate |
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2012
- 2012-11-20 JP JP2012254654A patent/JP6099369B2/en active Active
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- 2013-11-01 WO PCT/JP2013/079765 patent/WO2014080745A1/en active Application Filing
- 2013-11-01 MY MYPI2015701633A patent/MY169149A/en unknown
- 2013-11-01 CN CN201380060226.4A patent/CN104813465A/en active Pending
- 2013-11-01 KR KR1020157016478A patent/KR101691763B1/en active IP Right Grant
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| Publication number | Publication date |
|---|---|
| WO2014080745A1 (en) | 2014-05-30 |
| KR20150087388A (en) | 2015-07-29 |
| JP6099369B2 (en) | 2017-03-22 |
| TWI637424B (en) | 2018-10-01 |
| TW201430907A (en) | 2014-08-01 |
| KR101691763B1 (en) | 2017-01-09 |
| PH12015501117A1 (en) | 2015-08-17 |
| CN104813465A (en) | 2015-07-29 |
| MY169149A (en) | 2019-02-18 |
| JP2014103277A (en) | 2014-06-05 |
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