CN109378270A - The preparation method of the more field plates of power device - Google Patents
The preparation method of the more field plates of power device Download PDFInfo
- Publication number
- CN109378270A CN109378270A CN201811145353.5A CN201811145353A CN109378270A CN 109378270 A CN109378270 A CN 109378270A CN 201811145353 A CN201811145353 A CN 201811145353A CN 109378270 A CN109378270 A CN 109378270A
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- exposure region
- photoresist layer
- region
- incomplete
- layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 46
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 22
- 238000003754 machining Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 12
- 230000005684 electric field Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The present invention discloses a kind of preparation method of simple, at low cost, high-efficient and certifiable machining accuracy the more field plates of power device of process flow, difference with the prior art is that photoresist layer is gradually divided to region and controls each area exposure time, photoresist layer is set to be divided into complete exposure region, incomplete exposure region and unexposed area in the horizontal direction, the complete exposure region is located at middle part, complete exposure region two sides from the bottom to top respectively with incomplete exposure region medial surface, incomplete exposure region upper surface and unexposed area connects and interface is continuously stepped；Control developing time is dissolved in the complete exposure region of photoresist layer in developer solution and retains incomplete exposure region and unexposed area；It is etched to until forming multiple field plate steps on dielectric layer.
Description
Technical field
The present invention relates to a kind of preparation method of power device, especially a kind of process flow is simple, at low cost, high-efficient
And it can guarantee the preparation method of the more field plates of power device of machining accuracy.
Background technique
As the third generation semiconductor after first generation semiconductor silicon (Si) and second generation Semiconductor GaAs (GaAs)
Material representative, gallium nitride (GaN) has many excellent material properties, such as broad stopband, high temperature resistant, high electron concentration, high electronics
Mobility, high-termal conductivity etc..Therefore, GaN base high electron mobility transistor (HEMT) turns in microwave communication and power electronics
The field of changing possesses brilliant performance, is particularly suitable for manufacture high-power electronic device.
Gallium nitride power device belongs to a kind of planar channeling field effect transistor, when the voltage applied between grid and drain electrode
When increase, grid often will form a high electric field spike close to the edge of drain directions, easily device creepage be caused to increase
Greatly, component failure is often led to, device reliability is influenced.The problems in excessively collect to solve electric field, generallys use multiple fields
Plate disperses electric field, this is mainly due at each field plate edge can all result from a peak value electric field, is cut by partial pressure effect
The peak electric field of weak gate edge, so that a high electric field spike is dispersed into several small electric field spikes, to realize that raising is hit
Voltage is worn, the purpose of device lifetime and reliability are increased.
The method that GaN device realizes more field plates at present is the dielectric layers such as first grown silicon nitride or silica, later whole
A dielectric layer surface gluing simultaneously exposes (as shown in figure 1 shown in A) first layer field plate stepped area completely, develops later, makes
The photoresist exposed completely is dissolved in developer solution, and then is performed etching to the dielectric layer of development, processes first layer in dielectric layer
Field plate step (the side pattern after etching is as shown in figure 1 shown in B), removes the photoresist of unexposed area (as shown in figure 1 shown in C).
It exposes (as shown in figure 1 shown in D) in entire dielectric layer surface gluing and to second layer field plate stepped area, is carried out later completely again
Development, is dissolved in the photoresist exposed completely in developer solution, and then perform etching to the dielectric layer of development, processes in dielectric layer
Second layer field plate step removes the photoresist (as shown in figure 1 shown in E) ... ... of unexposed area until being formed on dielectric layer more
A field plate step, finally evaporation metal and stripping metal or sputtering and etching technics are formed at the multiple field plate steps of dielectric layer
Final more field plate structures.To repeat n times gluing to realize n field plate i.e., n times exposure, n times development, n times etch and
N times are removed photoresist.There is process flow complexity, produce a systems such as time-consuming, manufacturing cost is high and is difficult to ensure alignment precision
Column problem.
Summary of the invention
The present invention be in order to solve above-mentioned technical problem present in the prior art, provide a kind of process flow it is simple, at
The preparation method of the more field plates of power device of this low, high-efficient and certifiable machining accuracy.
The technical solution of the invention is as follows: a kind of preparation method of the more field plates of power device, it is characterised in that successively press
It is carried out according to following steps:
A. the preparation media layer on substrate；
B. the coating photoresist layer on dielectric layer；
C., photoresist layer is gradually divided to region and controls each area exposure time, is divided into photoresist layer in the horizontal direction
Complete exposure region, incomplete exposure region and unexposed area, the complete exposure region are located at middle part, complete exposure region two sides by down toward
It is upper to connect respectively with incomplete exposure region medial surface, incomplete exposure region upper surface and unexposed area and interface is continuously in ladder
Shape；
D. control developing time is dissolved in the complete exposure region of photoresist layer in developer solution and retains incomplete exposure region and do not expose
Light area；
E. it is etched to until forming multiple field plate steps on dielectric layer；
F. remaining photoresist layer (2) are removed；
G. more field plates are prepared at multiple field plate steps.
The present invention compared with the existing technology, though also needing multiple exposure, only needs once to develop, once etches and can be situated between
Multiple field plate steps are formed on matter layer, realize the preparation of more field plates.Process flow is greatly simplified, process time is shortened,
Processing efficiency is improved, manufacturing cost is reduced.It is etched simultaneously because single is aligned, so that alignment deviation problem is not present in multiple field plates,
It ensure that the stability of technique and the precision of device to the greatest extent.
Detailed description of the invention
Fig. 1 is prior art process schematic diagram.
Fig. 2 is the process schematic diagram of the embodiment of the present invention 1.
Fig. 3 is the process schematic diagram of the embodiment of the present invention 1.
Specific embodiment
Embodiment 1:
A kind of preparation method of the more field plates of power device of the invention as shown in Figure 1, successively carry out in accordance with the following steps:
A. the preparation media layer 1 on substrate:
It is same as the prior art, the dielectric layer of 100nm ~ 2 μm is prepared using the methods of PECVD or ALD, such as silica, silicon nitride
Deng.
B. the coating photoresist layer 2 on dielectric layer 1:
It is same as the prior art, using positive adhesive process on dielectric layer 1 coating photoresist, such as SPR220-3 photoresist, form 1 ~
The photoresist layer 2 of 10 μ m-thicks.
C., photoresist layer 2 is gradually divided to region and controls each area exposure time: dividing region such as Fig. 2A institute for the first time
Show, using existing photolithography plate, is directed at the region post-exposure 0.05 ~ 2 second with Stepper board, forms 2 upper layer of photoresist layer
Complete exposure region 2.1, lower layer are incomplete exposure region 2.2, and two sides are unexposed area 2.3；Second of division region such as Fig. 2 B institute
Show, using photolithography plate, quasi-full exposure region 2.1 is exposed 0.05 ~ 2 second again with Stepper board, makes as shown in Figure 2 A endless
Complete 2.2 part of exposure region exposes completely, even if photoresist layer 2 is divided into complete exposure region 2.1, not exclusively exposure in the horizontal direction
Area 2.2 and unexposed area 2.3, the complete exposure region 2.1 are located at middle part, and complete 2.1 two sides of exposure region are symmetrically from the bottom to top
Respectively with incomplete 2.2 medial surface of exposure region, 2.2 upper surface of incomplete exposure region and unexposed area 2.3 connects and interface is continuous
It is stepped.
D. control developing time is 10 ~ 200 seconds, since each area development of photoresist layer 2 is different, therefore result such as Fig. 2 C
Shown, the complete exposure region 2.1 of photoresist layer 2 is dissolved in developer solution (AZ300MIF) shows net completely, retains incomplete exposure region
2.2 and unexposed area 2.3.
E. performed etching using the boards such as ICP or IRE: due to corrasion have to photoresist and dielectric layer it is certain
Ratio is selected, therefore the photoresist of dielectric layer 2, the photoresist of incomplete exposure region 2.2 and unexposed area 2.3 is all with respective rate quilt
Etching；With the progress of etching, the photoresist of incomplete exposure region 2.2 is carved net and starts etch media layer 2 downwards, until such as
Shown in Fig. 2 D, until forming satisfactory multiple field plate steps 3 on dielectric layer 2.
F. because the photoresist of unexposed area 2.3 rate that is etched is low, therefore still there is residual after etching, need according to existing
There is the method for technology to remove, as a result as shown in Figure 2 E.
G. as shown in Figure 2 F, according to the method for the prior art at multiple field plate steps 3 evaporation metal and stripping metal shape
At more field plates 4.
Embodiment 2:
A kind of preparation method of the more field plates of power device of the invention as shown in Figure 1, successively carry out in accordance with the following steps:
A. the preparation media layer 1 on substrate:
It is same as the prior art, the dielectric layer of 100nm ~ 2 μm is prepared using the methods of PECVD or ALD, such as silica, silicon nitride
Deng.
B. the coating photoresist layer 2 on dielectric layer 1:
Same as the prior art, using positive adhesive process, coating photoresist forms 3 μm such as SPR220-3 photoresist on dielectric layer 1
Thick photoresist layer 2.
C., photoresist layer 2 is gradually divided to region and controls each area exposure time: dividing region such as Fig. 3 A institute for the first time
Show, using existing photolithography plate, is directed at the region post-exposure 0.05 ~ 2 second with Stepper board, forms 2 upper layer of photoresist layer
Two complete exposure regions 2.1, lower layer are incomplete exposure region 2.2, and between two complete exposure regions 2.1 and two sides are unexposed
Area 2.3；Second of division region is as shown in Figure 3B, using photolithography plate, with Stepper board between quasi-full exposure region 2.1
Unexposed area 2.3 expose again 0.05 ~ 2 second, be allowed to expose completely, it is as shown in Figure 3A, make photoresist layer 2 in the horizontal direction
It is divided into complete exposure region 2.1, incomplete exposure region 2.2 and unexposed area 2.3, the complete exposure region 2.1 is located at middle part, completely
2.1 two sides of exposure region from the bottom to top respectively with incomplete 2.2 medial surface of exposure region, 2.2 upper surface of incomplete exposure region and do not expose
Light area 2.3 connects and interface is continuously stepped.
D. control developing time is 10 ~ 200 seconds, since each area development of photoresist layer 2 is different, therefore result such as Fig. 3 C
Shown, the complete exposure region 2.1 of photoresist layer 2 is dissolved in developer solution (AZ300MIF) shows net completely, retains incomplete exposure region
2.2 and unexposed area 2.3.
E. performed etching using the boards such as ICP or IRE: due to corrasion have to photoresist and dielectric layer it is certain
Ratio is selected, therefore the photoresist of dielectric layer 2, the photoresist of incomplete exposure region 2.2 and unexposed area 2.3 is all with respective rate quilt
Etching；With the progress of etching, the photoresist of incomplete exposure region 2.2 is carved net and starts etch media layer 2 downwards, until such as
Shown in Fig. 3 D, until forming satisfactory multiple field plate steps 3 on dielectric layer 2.
F. because the photoresist of unexposed area 2.3 rate that is etched is low, therefore still there is residual after etching, need according to existing
There is the method for technology to remove, as a result as shown in FIGURE 3 E.
G. as illustrated in Figure 3 F, according to the method for the prior art at multiple field plate steps 3 evaporation metal and stripping metal shape
At more field plates 4.
Claims (1)
1. a kind of preparation method of the more field plates of power device, it is characterised in that successively carry out in accordance with the following steps:
A. preparation media layer (1) on substrate；
B. the coating photoresist layer (2) on dielectric layer (1)；
C., photoresist layer (2) is gradually divided to region and controls each area exposure time, makes photoresist layer (2) in the horizontal direction
On be divided into complete exposure region (2.1), incomplete exposure region (2.2) and unexposed area (2.3), complete exposure region (2.1) position
In middle part, complete exposure region (2.1) two sides from the bottom to top respectively with incomplete exposure region (2.2) medial surface, incomplete exposure region
(2.2) upper surface and unexposed area (2.3) connect and interface is continuously stepped；
D. control developing time is dissolved in the complete exposure region (2.1) of photoresist layer (2) in developer solution and retains not exclusively exposure
Area (2.2) and unexposed area (2.3)；
E. it is etched to until forming multiple field plate steps (3) on dielectric layer (1)；
F. remaining photoresist layer (2) are removed；
G. more field plates (4) are prepared at multiple field plate steps (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811145353.5A CN109378270A (en) | 2018-09-29 | 2018-09-29 | The preparation method of the more field plates of power device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811145353.5A CN109378270A (en) | 2018-09-29 | 2018-09-29 | The preparation method of the more field plates of power device |
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| Publication Number | Publication Date |
|---|---|
| CN109378270A true CN109378270A (en) | 2019-02-22 |
Family
ID=65402505
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811145353.5A Pending CN109378270A (en) | 2018-09-29 | 2018-09-29 | The preparation method of the more field plates of power device |
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| CN (1) | CN109378270A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114269076A (en) * | 2021-12-22 | 2022-04-01 | 无锡天杨电子有限公司 | Etching method for two-step pattern of thick-coated copper ceramic substrate |
| CN115023055A (en) * | 2022-07-08 | 2022-09-06 | 南京中江新材料科技有限公司 | Etching method for step pattern of metalized circuit substrate |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546727A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Process for Damascus |
| CN102023429A (en) * | 2009-09-17 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCK array substrate and method for manufacturing same and method for repairing broken lines |
| CN102116977A (en) * | 2009-12-31 | 2011-07-06 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN102148185A (en) * | 2010-02-09 | 2011-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnection structure |
| CN102738063A (en) * | 2011-04-07 | 2012-10-17 | 上海微电子装备有限公司 | Circuit interconnecting structure preparation method |
| CN103199060A (en) * | 2013-02-17 | 2013-07-10 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and thin film transistor array substrate manufacturing method and display device |
| US8518825B1 (en) * | 2012-12-24 | 2013-08-27 | Shanghai Huali Microelectronics Corporation | Method to manufacture trench-first copper interconnection |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| CN104813465A (en) * | 2012-11-20 | 2015-07-29 | 友立材料股份有限公司 | Substrate for mounting semiconductor element and method for manufacturing said substrate |
| CN106684157A (en) * | 2016-07-27 | 2017-05-17 | 西安电子科技大学 | Three-stage field plate terminal-based 4H-SiC schottky diode and manufacturing method |
| CN107275194A (en) * | 2017-06-29 | 2017-10-20 | 杭州士兰集成电路有限公司 | The manufacture method of hierarchic structure |
| CN107546114A (en) * | 2017-09-07 | 2018-01-05 | 中国工程物理研究院电子工程研究所 | A kind of preparation method of SiC Junction Termination of High Voltage Power Devices |
| CN108109910A (en) * | 2017-12-08 | 2018-06-01 | 深圳市晶特智造科技有限公司 | In the method that semiconductor base forms step |
-
2018
- 2018-09-29 CN CN201811145353.5A patent/CN109378270A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546727A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Process for Damascus |
| CN102023429A (en) * | 2009-09-17 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCK array substrate and method for manufacturing same and method for repairing broken lines |
| CN102116977A (en) * | 2009-12-31 | 2011-07-06 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN102148185A (en) * | 2010-02-09 | 2011-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnection structure |
| CN102738063A (en) * | 2011-04-07 | 2012-10-17 | 上海微电子装备有限公司 | Circuit interconnecting structure preparation method |
| CN104813465A (en) * | 2012-11-20 | 2015-07-29 | 友立材料股份有限公司 | Substrate for mounting semiconductor element and method for manufacturing said substrate |
| US8518825B1 (en) * | 2012-12-24 | 2013-08-27 | Shanghai Huali Microelectronics Corporation | Method to manufacture trench-first copper interconnection |
| CN103199060A (en) * | 2013-02-17 | 2013-07-10 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and thin film transistor array substrate manufacturing method and display device |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| CN106684157A (en) * | 2016-07-27 | 2017-05-17 | 西安电子科技大学 | Three-stage field plate terminal-based 4H-SiC schottky diode and manufacturing method |
| CN107275194A (en) * | 2017-06-29 | 2017-10-20 | 杭州士兰集成电路有限公司 | The manufacture method of hierarchic structure |
| CN107546114A (en) * | 2017-09-07 | 2018-01-05 | 中国工程物理研究院电子工程研究所 | A kind of preparation method of SiC Junction Termination of High Voltage Power Devices |
| CN108109910A (en) * | 2017-12-08 | 2018-06-01 | 深圳市晶特智造科技有限公司 | In the method that semiconductor base forms step |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114269076A (en) * | 2021-12-22 | 2022-04-01 | 无锡天杨电子有限公司 | Etching method for two-step pattern of thick-coated copper ceramic substrate |
| CN114269076B (en) * | 2021-12-22 | 2024-04-09 | 无锡天杨电子有限公司 | Etching method of second step pattern of thick copper-clad ceramic substrate |
| CN115023055A (en) * | 2022-07-08 | 2022-09-06 | 南京中江新材料科技有限公司 | Etching method for step pattern of metalized circuit substrate |
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Application publication date: 20190222 |
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