NO844929L - APPARATUS FOR A EQUIPMENT SEQUENCE OF LIGHT BLINK FROM A LAMP - Google Patents

Description

The present invention relates to light flash generators for lamps and more specifically an apparatus for causing lamps to emit light flashes in a distinctive code sequence and for synchronizing a number of such generator systems for light flashes.

Buoys and beacons for navigation usually use incandescent lamps which are caused to flash periodically in various sequences of short and long flashes of light separated by short and long blacked-out spaces in order to identify channels, obstacles and other navigational conditions. Many such devices are battery powered and conservation of primary power is important. In recent years, older turn signal systems that used motors and relays have been replaced by timing and regulating transistor circuits. See e.g. the following US patents in the name of Seidler: 3,244,892, 3,310,708 and 3,596,113. To obtain reliable and accurate timed signals, the drive voltages must be regulated. To exclude relays, transistor switches are used. Previously used transistors for regulation and switching have usually been of the germanium type to reduce the voltage drops. However, these transistor types have a high leakage current, particularly at high temperatures. Lower leakage at high temperatures can be achieved by using silicon transistors, but on the basis of high voltage drops.

In many applications, beacons or buoys are required to operate in synchronism, and usually a master flasher controls a set of slave units. When the master unit fails, incorrect operation of the slave units usually occurs. A need exists for a flexible and easily programmable turn signal control circuit which is capable of reducing the primary power requirement to a minimum, and which will allow any unit to synchronize the remaining units, and further will not fail simply because other units fail and will allow the formation of almost which

preferably coded signals.

The present invention relates to a new and improved lamp control system which overcomes the problems which are common in previously developed systems. The voltage-regulating and switching-controlling circuits here utilize silicon transistors with low leakage in a new connection that produces low voltage drops. The current to the relevant lamp is monitored during the light flashes and a lamp changeover switch is closed when lamp failure is detected, at the same time as an automatic lamp changer is energized.

A solid-state circuit for producing light flashing sequence is produced using mostly integrated logic circuits. Almost any code sequence or sequence of short and long light flashes and darkened spaces can be produced. The sequence generator uses an electronic counter which produces a counting step for each pair of light flashes and darkened space in the relevant sequence. A set of electronically switched RC constants is controlled from the counter to produce the desired durations of light flashes and gaps in each successive set of light flashes and gaps. The selected time constants for a certain flash/gap period control a timing signal generator which clocks the counter at the beginning of each such period of light flash and blacked-out gap.

When a number of light flash generators are to work together, synchronization of the light flashes and the darkened spaces is permitted according to the invention. Synchronization pulses are produced at the beginning of each flashing light and are transmitted to a cable or other connecting link with the other flashing units in the system. If not all units are in synchronism, these sync pulses will bring all other units back to synchronized operation. Any unit can advantageously serve as the master unit, while the remaining units are operated as slave units. Failure of such a main unit will not affect the other units.

A daylight regulator is also arranged to switch on the flashing lights during the day, so that the primary effect can be preserved. When darkness falls, the daylight regulator will ensure that at least one turn signal unit starts working. The synchronization pulses from this first activated unit will automatically bring the remaining units into operation, regardless of whether their daylight controller has been triggered. In the morning, all units will remain in operation until the least sensitive daylight controller is triggered, at which time all units will stop flashing. Thus, if a very sensitive daylight regulator on a turn signal unit tries to disconnect the relevant unit too early, sync pulses from the other units will also maintain the operation of this unit, so that a system is created that is secured against operational failure.

It is therefore a main object of the present invention to produce a flashing light unit for use in a system of such units and which can be programmed to produce a desired sequence of short and long flashes of light mutually separated by short and long darkened spaces, and which produces synchronizing pulses thereby to synchronize other link-connected turn signal units.

It is another object of the invention to produce a turn signal unit with a daylight regulator for use in a system of several such units interconnected by communication lines, all such units being equipped with daylight control circuits and arranged so that all units will continue to produce flashing lights until the least sensitive daylight regulator unit switches off its flashing lights, and in which the first flashing light unit that is activated when the light level in the surroundings decreases will cause all the other units to start their

blinking.

Another object of the invention is to produce a turn signal unit with a silicon transistor switch and a regulator with a low voltage drop across it when the drive voltage drops below the regulated value.

A further object of the invention is to provide a switch and voltage regulator which uses silicon transistors connected to form a darlington circuit for a first current level and to change to a single regulator circuit at another current level.

It is a further object of the invention to provide a switch and regulator which uses a darlington circuit which is modified so that the switch transistor can be operated with a pre-selected low voltage drop.

It is still a further object of the invention to produce a sensor circuit for the lamp current in order to thereby determine when a lamp has failed and in response to this to energize an automatic lamp changing mechanism.

It is another object of the invention to produce a new generator circuit for light flashing sequence from a lamp using integrated logic circuits which reduce the power draw from the power source to a minimum and have a long life and low costs.

It is still a further object of the invention to

provide a sequence generator circuit which allows the selection of a very large variety of short and long light flash sequences without the use of mechanical equipment, relays or motors.

The invention has yet another purpose to produce a sequence generator circuit that utilizes a step-displaceable counter controlled by time signal pulses, where a first time signal pulse steps the counter to the next counting step, and where the time to the next time signal pulse is controlled in accordance with the length of the required light flash as well as dark space for the counting step in question, as well as where the next time signal pulse that is generated steps the counter to the next counting step.

These and other objects and advantages of the present turn signal system will be better understood from the following detailed description with reference to the accompanying drawings, in which: Fig. 1 is a waveform diagram of a simple code sequence that can be generated by the turn signal unit shown in fig. 2. Fig. 2 is a simplified functional block diagram for a turn signal unit according to the invention. Fig. 3 is a simplified functional diagram for a system of turn signal units which are interconnected by means of communication lines. Fig. 4 is a wiring diagram of the voltage regulator and switch parts of a turn signal unit. Fig. 5 is a wiring diagram of the logic circuits for producing a sequence of flashing lights in a flashing light unit. Fig. 6 is a waveform diagram showing two periods of the flashing light sequence produced by the device shown in Figs. 4 and 5.

Reference should first be made to fig. 2 which indicates a greatly simplified functional block diagram of the lamp controlling and synchronizing system according to the invention, and to fig. 1 which illustrates certain waveforms that occur during operation of the system, whose basic operating mode will be explained. The lamp 24 shown in fig. 2, can be an incandescent lamp mounted in a buoy or on obstacles in a waterway, such as an oil drilling platform or the like. It will be required to bring the lamp 24 to produce a distinctive light flashing sequence in order to thereby form a code which enables the vessel to determine what the buoy or structure in question stands for. In fig. 1 is a particular light flash cycle shown only as an example and it must be understood that a large number of different coded signals can be produced by the present invention. Line B shows a sequence of light flashes FL in which a code consisting of three code elements has been entered, which in this case consists of two short light flashes and a long flash, indicating the letter U in Morse code. The first short light flash 10 can e.g. have a duration of the order of three-tenths of a second. The lamp is then switched off for a short period indicated at 12. This OFF period EC is called "dark space". This gap is again followed by a short flash of light and a short dark gap. The long light flash shown at 16 is much longer than the short flash and is indicated to be about 3 times the duration of the short flash in this example, or about 1 second. A long dark space 18 follows the end of the Morse letter U, after which the coded letter is repeated again. It should be understood that the ratio between light flashes and dark space can be varied as desired. An example of a certain time setting is as follows: Short light flash, ON for 0.3 seconds, OFF for 0.7 seconds, as well as long light flash, ON for 1 second, OFF for 3 seconds.

According to fig. 2, the lamp 24 is made to flash or is turned ON by means of lamp regulator circuits 22 which close a circuit to one side of the lamp 24. Power from the power source 32 which can usually be made up of primary or secondary batteries or other types of power sources. In order to achieve a long life for the lamp, the output voltage for the flashing light is controlled by a regulator 28 which effectively determines the highest voltage that can be applied to the lamp 24. The current that flows through the lamp 24 is monitored by the lamp current sensor 26. As will become closer explained in the following, it is not required with a series resistance in the current circuit for the lamp 24 for current monitoring according to the invention. An instruction from the lamp regulator 22 via wire 27 indicates to the lamp sensor 26 that the lamp 24 is ON. If at this time the sensed lamp current is not within the normal limits for this lamp 24, a control signal is issued to an automatic lamp changer 30, which is described in US patent no. 3,308,338, and which replaces the lamp 24 with a new one lamp unit. The regulator 28 also includes means for regulating the operating voltage for the electronic flashing control circuits according to the present invention.

It will now be described how the required regulation of the lamp 24 is achieved according to the present invention. A counter 40 is used to determine time periods for each set of light flashes and dark space, such as 10 and 12, as well as 16 and 18 in fig. 1. As will be seen, the time periods 10 and 12 are much shorter than the time periods 16 and 18. The counter 40 is therefore controlled to produce counting periods of different lengths during its work cycle. In the preferred example, only three counting periods are required to produce the flash of light representing the Morse code for U, as indicated by line B in FIG.

1. During a duty cycle, the counter 40 will therefore step from the counter stage ZERO to the counter stage ONE and from there to the counter stage TWO, and will then be automatically reset by virtue of the connection of the counter stage THREE with the reset terminal of the counter 40. The duty cycles of the counter, which are shown on the lines C , D and E, thus produces a short pulse 14 on the NULL output, a short pulse 15 on the ENER output and a long pulse 20 on the TOER output.

The necessary control to produce long and short periods is achieved by a set of switches 44, 48, 52 and 58 with associated resistors 60, 62, 64 and 66. In a special counting stage, the desired resistors are connected to charge up a code capacitor 68 ( C^), with the thus formed time constants determining the duration of the light flash and dark space during the relevant output pulse from the counter 40. In the present example, the resistance 60 (R^) is chosen to produce a time constant proportional to the length of the counter's output pulses 14 and 15, as will be explained in more detail below. The switch 40 is controlled by the gate circuits 42 to produce a short light flash 10 with the necessary gate control signals produced by the 1amp regulator circuit 22. In a similar manner, the switch 48, which is connected to the resistor 62 (R£), is controlled by the gate 46 for short intervals, and which in turn is also controlled from the lamp regulator circuit 22. The value of the resistor R2 thus determines the lamp's OFF period 12, and in the present embodiment R^ and R2

have the same resistance value if equal duration of light flash and dark space is desired. In certain cases, the light flash and the dark space are of different durations, and a ratio of 3 to 7 is commonly used. In a similar manner, the switches 52 and 58 control the resistors 64 (R3) and 66 (R^), the time constants of the selected resistors together with the capacitor 68 (C^) producing either long light flash duration 16 or long duration 18 of the subsequent blackout. In order to produce a long flash of light and a long darkening, a set of gates 50 and 54 are used, each of which has four inputs for this purpose. Within one and the same work cycle, it is therefore possible to achieve four long light flashes and four long blackouts. However, the present invention is not limited to this number

and it is obvious that further gate entrances may be provided for this purpose. Selection of the points in a series of light flashes where a long flash and a long subsequent blackout is required is selected by connecting an input for gate 50 and gate 54 to the slope output that occurs at the desired point in the cycle. In the present example, a long flash of light 16 and a long dark pause 18 are desired in the third counting stage, which is counting stage TWO on line E, and the outputs from gates 50 and 54 are therefore connected to the output for counting stage TWO in the counter 40. As this is the only counting stage in the cycle that requires a long light flash and a dark gap, the rest of the gate's inputs are grounded.

The control that produces long and short output pulses from the counter 40 is achieved by using the clock and time signal generator 34. As will be described in more detail below, the clock and time generator 34 produces a sequence of time signal pulses on the wire 35 to the lamp regulator circuit 22, as is shown on line A in fig.

1. The time between these pulses is controlled by choosing the resistors R^ through R^. The timing signal pulses may be short pulses in the range of one millisecond to ten milliseconds at the beginning of each required light flash or blackout as well as in the middle of each such flash or blackout. These time signal pulses are routed by the lamp regulator circuit 22 via wire 23 to the clock input of the counter 40 and thereby bring the counter 40 to a step shift one step shortly after the beginning of each light flash. If the time between the first pulse 11, which is referred to as the START pulse, and the third pulse 13, is short, the lamp regulator circuit 22 will activate gate 42 at the START pulse and gate 46 at the STOP pulse, both of which occur during the counting step ZERO of the counter 40. The resistors 60 and 62 are then connected in sequence. When the START pulse 11 activates the gate 44, it will be understood that a short time constant corresponding to R^C-^ will cause the clock and timing signal generator 34 to produce the STOP pulse 13 in that pair, which causes the lamp regulator circuit 22 to activate the gate 46 for short darkened space. When the START pulse 17 for the long flashing period occurs as the counter 40 is stepped to produce output pulse 20 above its output TO, in a similar way the pulse 20 will activate one input for ports 50 and 54. A flashing pulse will then appear on wire 41 from the lamp regulator circuit 22 to gate 50 for long flash, and which then drives switch 52 to connect resistor R^ to capacitor C^, creating a long time constant for long flash 16. When the STOP signal pulse 19 appears on wire 35 of lamp regulator circuit 22, a blackout pulse on line 43 activates long blackout gate 54, which engages resistor R^ to produce blackout period 18.

The present invention also applies to a subsystem for daylight control and which comprises a control circuit 70 and a photocell 72. The purpose of this control is to switch off the flashing light system during the hours of daylight and to switch the system on at night. As will be further explained below, the clock and timing signal generator 34 will be prevented from generating timing signal pulses during daylight and when sufficient incident light hits the photocell 72. When the system is turned on, it is desirable that all units in the system will start at the beginning of the cycle shown on line B in fig. 1. To this end, the lamp controller circuit 22 generates a short synchronizing pulse at the beginning of each light flash as well as during the first flash of each cycle. In the present example, a sync pulse will appear at the same time as the pulse 11 and as the second time signal pulse on line A. This sync pulse will appear on line 29 from the lamp regulator circuit 22 to the sync output amplifier 36. The sync pulses will then be externally accessible on the output line 37 for purposes which be described below. These sync pulses also reset the clock and timing signal generator 36 above the regulator circuit 22 and the counter 40, thereby ensuring that the first sequence of light flashes begins at the beginning of a cycle.

Reference must now be made to fig. 3, where there is shown a series of N turn signal systems, each of which is of the type shown in fig. 2. It will be understood that when each of the photocells 72 is exposed to sufficient incident light, contemporary turn signal systems will be disabled, as described above. The purpose of the present invention is to get all systems in the row to be switched on at the same time and function in synchronism. It is usually not practically possible to make the sensitivity exactly the same for all photocells, and even if this could be achieved, the incident light would not normally have the same intensity at each cell, as the different systems will be in different places. For the sake of clarity, it can be assumed that all systems are switched off and that system 2 experiences sufficient light reduction on its photocell 72 to start the light flashing, as described above. When this occurs, the sync signals appearing on wire 29 from the lamp regulator 22 in fig. 2 will be sent out via wire 3 7 via the sync output 36. At this point, the sync pulses will be transmitted via connections 39 to system 1, system 3 and the other systems in the series. As each of the other systems receives these sync pulses, the system in question will thus reset its clock and time signal generator 34 and counter 40, which causes each of the systems to overlook its own daylight regulator 70, which is then blocked by a control signal on the conductor 71 from the lamp regulator circuit 22. It should now be noted that each system produces its own sync signals, but all such signals appear simultaneously and are present on each output line. When the light conditions change to such an extent that the photocells 72 are energized, it is also an object of the present invention to achieve that all units continue their light flashing until the least sensitive or last unit is switched off from the daylight regulator 70. It shall now be assumed that system 3 with its photocell 2 is the last unit to receive sufficient light to switch off the turn signal system. At this point, all the other units will have been influenced by their assigned photocells to cause the daylight regulator 70 to try to stop the light flashing from the unit in question. Synchronization pulses from system 3 which appear on the sync input for line 37 in each of the other systems will, however, again perform their work function, which is to keep each of the units in operating condition. When system 3 is finally switched off due to sufficient illumination of its photocell 72, the system's sync pulse will disappear from line 37 and all systems will therefore be switched off simultaneously. Although fig. 3 shows a wiring line 39 between the wires 37 from each unit, it will be understood that any type of interconnection can be used, depending on the available environment for the systems. Cable connection can e.g. are used on large building structures such as oil drilling platforms, while a radio line can be appropriately used for buoys. However, such interconnection is not intended to form any part of the present invention.

Now that the basic operating principles for the subject of the present invention have been described, the distinctive new circuits will be explained in more detail. Fig. 4 shows a connection core of the power supply regulator and the lamp circuit sensor according to the present invention. This circuit consists of three basic elements, namely a voltage regulator 80 for the electronic circuits, a voltage regulator 90 for regulating the voltage applied to the incandescent lamp 24, and a lamp current sensor 26 which operates a switch consisting of transistors 205, 202 and 109.

It is assumed that the present invention will mainly be used with turn signals powered from a battery-type power supply. However, the supplied battery power will vary with respect to output voltage during the life of the battery or over a charge cycle. For

to make the lifespan as long as possible for an incandescent lamp 24, it is necessary to regulate the voltage applied to the lamp. With battery operation, it is also necessary to reduce the losses in the regulator circuits in order to be able to maintain correct working function even when the battery voltage drops to a value lower than normal. This has previously been achieved by using germanium-type power transistors for switching and regulating the current through the relevant incandescent lamp. Although the voltage drop across the main switching transistor could be kept at around 0.5 to 0.6 volts with germanium transistors, these devices have a high leakage current that increases with rising temperature. In the present regulator 90, however, a silicon-type power transistor 62 is used as the primary switching and regulating element. At low battery voltage, one has thereby advantageously been able to keep the voltage loss across the transistor 92 much lower than has previously been possible with a transistor switch and regulator of the silicon type. The transistor 92 is driven by a transistor 94 which in turn is driven by a further transistor 96. When the main transistor 92 is switched off, the collectors of the transistors 94 and 96 are connected to the collector of the transistor 92 via a diode 93, so that a darlington circuit. The collectors of the transistors 94 and 96 are connected via a bypass resistor 95 to the negative side of the power source, which is considered ground potential in the circuit shown in fig. 4. A differential amplifier 98 and 99 is connected in a regulator circuit with a zener diode 97 for voltage reference, and is used to regulate the collector voltage of the transistor 92. When the lamp 24 is first switched on, the operating current will pass through the emitter/base layer

in transistor 92, through transistors 94 and 96, and also through diode 93 and the present load. However, as the collector voltage on transistor 92 rises, diode 93 will be biased in the blocking direction and the operating current will therefore pass through bypass resistor 95 to ground. The circuit is thus automatically switched from a darlington circuit to a single transistor circuit driven by another transistor, where the drive current is now not part of the load current. With the transistor 92 in the conducting state, the filament in the lamp 24 will draw a high current once it is switched on, but will increase its resistance as the filament heats up, so that the required operating and load current decreases. The resulting collector voltage and consequently also the voltage across the lamp 24 will be determined by the zener diode 97 as well as the setting of the resistor 201 in the regulator circuit formed by the transistors 98 and 99. When the currents through the transistors 94 and 96 flow through the bypass resistor 95, minimal voltage loss between

emitter and collector of transistor 92 are not limited by the collector-to-emitter voltages of transistors 94 and 96. When the input voltage falls below the desired regulated output voltage in the conventional darlington regulator circuit, the reduced voltage drop across transistor 92 will approach a value determined of the voltage drop across transistors 94 and 96, when the input voltage falls below the desired regulated output voltage in

When the supplied voltage is greater than the desired regulated output voltage, a voltage divider formed by the resistors 205 and 103 will produce a voltage across the zener diode 97 which is greater than the voltage which produces ignition of this diode. The base of the transistor 98 in the differential amplifier will then be held constant at the reference voltage created by the zener diode

97. The voltage at the base of the transistor 99 will be determined by the voltage divider formed by the resistors 197 and 201 from the regulated lamp voltage. The ratio of resistors 197 and 201 is adjusted to produce only that current through transistors 94 and 96 which will provide the desired maximum output voltage on the collector of transistor 92.

When the applied voltage to the emitter of the switching transistor 92 approaches or falls below the desired value of the regulated output voltage, the voltage at the base of the transistor 98 will drop below the breakdown voltage of the zener diode 97 and further to a value determined by the voltage ratio in the voltage section 205 , 103. Base voltage for the transistor 99 is determined by the voltage ratio in the divider 197, 201. The resistance ratio between the resistors 205, 103 is set so that a low predetermined voltage drop between emitter and collector across the switching transistor 92 is achieved. However, this voltage is higher than the voltage drop would be in the event that transistors 98, 96 and 94 were fully turned on. The addition of the resistor 103 to form the voltage section 205, 103 when the zener diode 97 is not conducting therefore allows limiting the drive current through the transistor 92 to the current value required to maintain the desired minimum voltage drop across the transistor 92 at any given load current.

In an alternative arrangement of the circuit in fig. 4, where it is only required that the transistor 92 should be able to switch off

the load and without regulation of the load voltage, the zener diode 97 can be omitted and the voltage across the junction transistor maintained at a very low value over a wide range of applied voltage values. In this case, the resistor 103 prevents the direction of the transistors 98, 96 and 94. Without the resistor 103, the drive current for the transistor 92 would only be limited by the values of the counter-

positions 95 and 211. Selection of the resistor 95 for the supply of sufficient drive current for a high current-carrying load would in such a case lead to an extremely high drive current also for a low current load, which would represent a waste of energy. With the resistor 103, the drive current is dynamically set to just the value required to maintain the selected voltage drop across the transistor 92 for any instantaneous or stable value of the load current, and the drive current can then be maintained as a small percentage of the load current to achieve maximum degree of effectiveness.

As will now be appreciated, the new voltage dividers associated with the differential amplifier 98, 99 and the drivers 94, 96 allow the voltage drop across the junction transistor 92 to approach the directional value, but without excessively high drive current at any given lamp load current.

As an example of a special operating case for the new regulator 90, it can be assumed that the input voltage can vary between 13 and 18 volts and that an output voltage of 12 volts is desirable. With input voltage in the range of 13 to 18 volts and resistor 103 omitted, the first step would be to set resistor 201 to provide an output voltage of 12 volts. The input voltage is then reduced to below 12 volts, e.g. 11 volts. The resistor 103 is then inserted and set to give the desired voltage drop from emitter to collector in the transistor 92 at the highest lamp load for which the unit is designed.

As will be understood, the voltage drop across the bypass resistor 95 will decrease if the lamp's filament fails, and this voltage can then be used to sense such filament failure. A sensor resistor in series with the lamp 24 is therefore not necessary, and the power loss such a resistor would entail is thus avoided. The voltage across bypass resistor 95 produced by the drive current is consequently sensed by comparator 195. If lamp 24 fails, comparator 195 controls transistor switch 202, which in turn brings junction transistors 204 and 109 into conduction to energize an automatic lamp changer, the operation of which involves removing the failing lamp 24 and inserting a new lamp.

The regulator 80, which supplies regulation power to the timing circuits according to the invention and also to the comparator 190, is a simple voltage regulator with a transistor 206, a zener diode 208 and a resistor 108.

The preferred embodiment of the electronic control circuits for flashing lights and corresponding time signal circuits according to the invention is shown in schematic form in fig. 5, but it will be readily understood that other circuits can also be arranged to produce the desired functions, which would be obvious to those skilled in the art. The working function of the circuits shown will be explained with reference to the curves shown in fig. 6 of waveforms at different points in the relevant circuits. As previously discussed with reference to fig. 2, the present object of invention can produce up to 10 flashing periods with the counter shown which allows light flashing in the form of different coded signals, and by appropriate selection of capacitor 68 and resistors 60, 62, 64 and 66 the durations of the light flashes and the darkened spaces can be regulated. It should be understood that larger counters can be used to provide more than 10 flashing periods. For the circuits shown in fig. 5, 6 periods (N=6) have been selected to illustrate the invention, with the counter 50 connected to produce the coded flash sequence indicated on line T in FIG. 6. The given sequence of two dashes, two dots and two further dashes is of course an arbitrary code as just an illustrative example. A short darkened space is produced between successive code elements, while a long darkened space is produced at the end of the code. As will be appreciated, FIG. 6 two complete cycles of the relevant code. It can be noted in fig. 5 that the counter 40 has its counter outputs ZERO and ONE connected to two inputs for the NOR gate 146 with four inputs, to thereby produce two long flashes of light at the beginning of the code, while the counter outputs FOUR and FIVE are connected to the other two inputs to produce the two long flashes at the end of the code. The four-input NELLER gate 148 has one of these inputs connected to the count output FEM to produce the extra long blackout period at the end of the code. The rest of this port's inputs are grounded, as previously discussed.

The multivibrators 101 and 102 are key timing elements in the circuit. As shown on lines G and H in fig. 6, the multivibrators 101 and 102 are interconnected to cause the multivibrator 101 to produce equal length pulses of HIGH and LOW level respectively across its Q output for each HIGH or LOW level output from the Q output of the multivibrator 102. When e.g. . multivibrator 102 produces a HIGH level pulse 170 of long duration, the multivibrator 101 will emit a HIGH level pulse 171 followed by a LOW level pulse 172, each of which has a duration corresponding to half the duration of the HIGH level pulse 170. The multivibrator 102 thus changes state a time while two state changes occur in the multivibrator 101. The clock and timing signal generator shown in its entirety at 34 outputs the sequence of timing signal pulses indicated on line F over wire 35 which clocks the multivibrator 101 and outputs input signals to several gates. The output levels of Q.^, Q^,<Q>2, Q2 are used to control different gates in the lamp's control circuit.

An initial sequence for the flashing controller system can be visualized by assuming that the circuits are in the state indicated by the "start" arrow on line F in FIG. 6, with the timing pulse line 35 at the HIGH level, Q1 and Q2 at the LOW level and the lamp switched OFF. Counter 40 will be in its sixth counting step. When counter 40 completes its sixth count step, which occurs at output 5, counter 50 will, as shown, be shifted to its N + 1 or seventh count step which occurs at output 6 and is connected across OR gate 132 to the reset input of counter 40. The reset pulse to counter 40 also resets both multivibrators 101 and 102. At this time both and Q_2 are at the LOW level. When a negative-going time pulse occurs on line 35 from the time signal generator 34, all inputs to the NOR gate 110 will be at a LOW level to produce a HIGH level on the gate's output side. The output for the OR gate 126 will then be at a HIGH level, thereby producing a HIGH level signal at one of the inputs to the NOR gate 112 and for the NOR gate 114. The gate 114 will produce a low level at an input to the OR -gate 125, which has a low level on its other input from the OR gate 112. The LOW level produced on the output side of the OR gate 124 then turns off the transistor 141.

The collector of the transistor 141 is connected to the input X in fig. 4, which controls the lamp's switching transistor 92 over the transistors 98 and 99. When the transistor 141 is in the conductive state, the point X will be at the LOW level to cut off the current to the lamp 24. When the OR gate 124 thus turns off the transistor 141, the lamp's switching means is activated and turns on the lamp 24. The effect of the START signal pulse 174 going LOW also brings a HIGH signal level from the output side of the NOR gate 110 to an input of the NOR gate 120. Both and<*>Q2

is then at a high level and produces a HIGH level signal at the input side of the NELLER gate 118, which has a LOW input signal from wire 35. The NELLER gate 120

produces a LOW output signal, turns on transistor 125 and brings its collector and sink output line 37 to HIGH level. This produces the leading edge of the sink pulse 178 on line F in FIG. 6. It should be noted that the sink pulse 178 occurs substantially simultaneously with the START signal pulse 174. When the START signal pulse 174 goes positive (the trailing edge), the multivibrators 101 and 102 are clocked to produce pulses 171 and 170 on and "Q^, such as shown on lines G and H. The output of the NORTH gate 110 then assumes a LOW level and thereby brings the output side of the NORTH gate 102 to a HIGH signal level. The transistor 125 is then turned off and the line 37 goes to the LOW level. The process just described therefore produces the sink pulse 178 on line 37. When transistor 125 is switched on, transistor 121 is also switched on, while transistor 123 is switched off.

Before the START signal pulse 174, the transistor 123 was switched on to charge the capacitor 145. When the first sync pulse 178 occurs, one input for the AND gate 136 goes to HIGH level, while the other input is already at HIGH level from the charge on the capacitor 135. A HIGH signal level therefore occurs on the output side of the AND gate 136. The resistor 143 is chosen to be able to charge the capacitor 146 to close the AND gate 136 before the end of the sync pulse 178. This process causes the sync pulses 178 and 180 to be duplicated on wire 161, but is here of shorter duration to prevent line 161 from remaining at a high level, which would bring a latching condition to the reset input of transistor 139. Multivibrators 101 and 102 are set by the short setting pulses 182 (line J in Fig. 6 ) as well as being reset by short pulses 183 through gate 132, which also reset counter 40. The short pulses 183 on line 161 to AND gate 138 are also transmitted to the base of transistor 139 in the clock and time signal generator 34 for resetting this generator. The AND gate 106 has both its inputs at the HIGH level, and the reset pulse

is therefore transferred to reset the counter 40.

It should be noted that the output side of the NOR gate 118 goes HIGH during the timing pulse 176, which occurs in the middle of each light flash in the flash sequence. When the counter's ZERO output shown on line M is preset, the timing signal pulse 136 will produce an additional sync pulse 180 on line S in FIG. 6. This pulse is therefore propagated through the NOR gate 120 to bring the signal on the sync output line 37 to the HIGH level. The inverter 130, the output of which is connected to an input of the AND gate 128, serves to prevent a reset pulse that may occur from a remote device during the last counter step of the counter 40, if the last light flash has been of long duration. The additional sync pulse 180, which appears on the sync output 37, will be transmitted to all the other flash systems in the network, and will reset each of the counters in the other flash systems connected to the sync line 37, through their corresponding ports 136, 138, 106, 128 and 132. If all turn signal systems in a group were not synchronized, the first turn signal system to reach the ZERO count step would produce sync pulse 80 and reset all other systems except those that happened to be in the last count step. However, when such a unit goes to its NULL counter step, the generated sync pulse will in turn reset and therefore synchronize all the other units to this unit. From the above-described lamp turn-on sequence, it will be appreciated that the lamp is turned off controlled by a low input level to the OR gate 114, which places a high input level on the OR gate 124 to turn on the transistor 141. When it is in the conducting state, transistor 141 applies a LOW signal level to the X input of the lamp switching circuits of FIG. 4, which causes the lamp to switch off. The NELLER gate 112 serves as a latch to keep the transistor 141 turned on until the next turn-on signal occurs. During a turn-on pulse, a high signal level from the output side of the AND gate 104 will set the multivibrators 101 and 102 and bring Q2 low. During a darkened period, the transistor 105 is conductive and charges the capacitor 107, thereby allowing a sync signal on the AND gate 104 to produce a HIGH signal level on the output side for setting the multivibrators 101 and 102. When the transistor 105 is turned off, the capacitor 107 is allowed to discharge which blocks the AND gate 104. The set pulse is thus truncated and cannot occur again during a flashing period, as the capacitor will remain discharged. It can be noted that during synchronisation, both the sync pulse and the counter reset pulse from the output side of the AND gate 137 will also appear on the transistor 139 in the clock and time signal generator, thereby causing it to be reset as will be discussed in more detail below.

The next time signal pulse 176 will occur while Q, and Q_2 are both at HIGH level, as shown by pulses 171 and 170 in fig. 6. The wire 35 to the one input for the NELLER gate 118 will then go to LOW level.

As will be apparent from line M in fig. 6, the ZERO output of the counter 40 will be at the HIGH level and the inverter 122 will bring another input to the NOR gate 118 to the LOW signal level. The outputs Q1 and Q2 are low, thereby producing a low-level signal from the output side of the OR gate 116 to the third input of the NOR gate 118. Its output then outputs a HIGH level to one input of the NOR gate 120, whose other input is held on LOW level of the NOR gate 110. The output of the NOR gate 120 then goes to a low level and turns the transistor 125 to produce sink pulses with a HIGH level on the output line 37, as previously described. At the end of the timing signal pulse 176, the input to the NOR gate 118 goes high and thereby brings the sync output line 37 to the LOW level. It should be noted that generating a sync pulse using the NOR gate 118 requires the input from the counter 40 above the inverter 122 to produce a low signal level at the relevant input to the NOR gate 118. This can only take place during the ZERO count step, and no sync pulses will therefore appear during the rest of the sync cycle. The reset pulse produced on line 161 during the second sync pulse 180 during the ZERO count step will again reset the clock and timing signal generator 34, and will also be transmitted through AND gate 106, AND gate 128 and OR gate 132 to the reset terminals of the multivibrators 101 and 102. As will now be recognized, the sync pulses 178 and 180 on the sync output 3 7 will occur at all the other interconnected flashing lamp systems. An incoming sync pulse will be transmitted over the relevant unit's own ports 136 and 138 to the unit's clock and time signal generator for resetting this, as well as over ports 106, 128 and 132 for resetting the counter. This will start the relevant unit in synchronism with the transmitting unit to produce the desired simultaneous flashing of all units in the system. On line L in fig. 6, a series of blocking pulses is shown. These negative-going pulses are generated by gate 140 during the latter half of each blink period to disable gate 138, preventing the device in question from being reset by an incoming sync pulse occurring during such time.

Reference must now be made to the circuits in the clock and time signal generator which are shown in their entirety at 34 in fig. 5, and with reference to line F in fig. 6, its working function will be described. The time signal generator 34 utilizes a transistor 137 and a transistor 139. The base of the transistor 137 is kept at a fixed bias by means of a voltage divider formed by a resistor 43 and a variable resistor 47. The variable resistor 47 can be set to give the desired bias. The transistor 139 is not conductive during the time period between the time signal pulses, so that the START signal pulse 174 and the pulse 176 in fig. 6 so that a HIGH output signal is thereby produced on line 35. When transistor 139 is in the conducting state, its collector voltage will drop and produce a LOW level on line 35 during a timing signal pulse. Immediately after such a pulse, one of the bilateral switches 52, 58, 44 or 46 of the selected gate circuit is closed, causing the capacitor 68 (C^) to begin charging through the selected resistor. In that time signal pulse 176 in fig. 6 is used as an example, the switch 52 is closed and the resistor 64 is connected to +V for the regulated power source, the capacitor 68 being charged. When the voltage on the capacitor 68 has risen sufficiently to overcome the bias on the basis of the transistor 137, this transistor will become conductive and place a HIGH signal level on the basis of the transistor 139, whose collector then assumes a LOW level, as described above. The charge on capacitor 68 is discharged by diode 149, while diode 147 serves to hold the output side of resistor 64 at a LOW level to prevent recharging of capacitor 68 for the duration of the timing signal pulse. When the charge is quickly removed from the capacitor 68, the LOW signal level on the collector of the transistor 139 will regeneratively turn off the transistor 137, allowing the capacitor 68 to be recharged through the resistor 64 connected to this capacitor across the switch 52. It should be noted that the switch 52 is kept on by the ZERO counting stage output from the counter 40, as shown on line M in fig. 6, and is thus still leading. As indicated, the diode 147 will prevent recharging of the capacitor 68 during the time signal pulse 176 which occurs in the middle of a light flash or a dark period. As will also now appear, a reset pulse from the AND gate 138 to the base of the transistor 139 will bring this transistor 139 to the conducting state and thereby produce a time signal pulse and initiate a new time cycle.

Bilateral switches 52, 58, 44 and 48, which may be elements of a four-way switch 160, are closed by their respective AND gates 152, 154, 156 and 158. When a short light flash is to be produced, such as 184 on line T in FIG. . 6, during count step TWO of the counter 40, the START signal pulse 185 clocks the multivibrators 101 and 102 and thereby produces a HIGH signal level 186 on Q2. This HIGH level appears on one input of the AND gate 156, which also has a HIGH signal level on its other side from the OR gate 146, whose inputs are all at the LOW level. A HIGH signal level at the output side of 156 turns on gate 44 for the period that Q2 remains HIGH. When the STOP signal pulse 187 occurs, the multivibrator 102 is clocked by the multivibrator 101 to produce the LOW level of Q2 as shown at 189 in FIG. 6. A short dark period 188 on line T is then required, and is achieved by the high level from Q2 appearing on one input for the AND gate 158, while the other input has a high signal level from the output side of the NOR gate 148. The switch 48 is therefore closed and connects the resistor 62 to charge the co-capacitor 68. As the resistors 60 and 62 in this case have the same value, the charging time will be the same as for the short light flash, and the transistor 141 will therefore be controlled to keep the lamp switched off during darkness period 188 during the same time interval as the light flash 184. It should be pointed out that it is not necessary that the short light flash and the short dark period have the same duration. The resistor 60 can e.g. is chosen to produce a short light flash of 0.3 seconds, while resistor 62 is chosen to produce a short dark period of 0.7 seconds.

The long light flashes and long dark periods are respectively controlled by the switches 52 and 58, the gates 152 and 154 being kept closed during short light flashes and dark periods by the inverting action of the inverter 144 and the NELLER gate 150. When a long light flash is required, as in counting stage 1, the counting pulse 190 is pressed on.:<!>line N in fig. 6 the one input for the NOR gate 146, which then produces a LOW signal level on its output side above the inverter 144, while a high signal level is applied to one input for the AND gate 152. The other input receives a HIGH level from Q2, which turns on the switch 52. In a similar manner, a long dark period is obtained at a HIGH level of the NELLER gate 148, which in this case will occur at count stage FIVE, 191 on line R in FIG. 6. The basic pulse-forming and time-controlling circuit described above when used in the present invention is described in the applicant's US Patent No. 3,596,113 and is hereby incorporated into the present application as a reference.

The NELLER gate 150 between the NELLER gate 148 and the AND gate 154 is advantageously used in the daylight regulator circuit which is indicated in its entirety at 70, with the purpose of switching off the turn signal system during daylight and to start the system at night or at heavily cloudy weather. During the day when sufficient light falls on the photocell 72 to make the minus input of the comparator 162 lower than its plus input, its output will assume a HIGH level bringing the output side of the NOR gate 150 to a LOW level and thereby blocking the AND gate 154. The above process however, will only take place. when the AND gate 164 is activation in that Q, and Q2 are at the same time HIGH level.

As will be seen from fig. 6, this condition occurs only during the last half of each dark period. When the sequence reaches one and a half of the next long dark period, the AND gate 154 will be blocked and the capacitor 68 will discharge, thereby turning on the transistor 137. The capacitor 68 cannot be recharged as the switch 58 remains open until the comparator 162 changes state again . Thus, the clock and time signal line 35 will remain at the HIGH level and the turn signal sequence will stop. When the light level on the photocell 72 decreases sufficiently to bring the voltages on the input side of the comparator 162 to such a change that a LOW is produced. signal level on its output side when the AND gate 164 is activated at HIGH signal levels of and , this action will activate the OR gate 150 to allow the capacitor 68 to charge again. The AND gate 164 is disabled by the LOW level of the multivibrator 101 during the first half of each dark period, which also disables the comparator 162. This process prevents current from the filament of the lamp 24 during blackout from causing tripping of the turn signal system.

Although the invention has been described in detail above with reference to various specified elements, it will be obvious that many modifications can be made without exceeding the scope of the invention. It can e.g. it is thought that the circuits shown can be implemented in LSI in order to thereby reduce scope and costs.

Claims (17)

1. Apparatus for producing a preselected sequence of light flashes and darkened spaces from a lamp (24) comprising: a lamp regulator (22) connected to the lamp for supplying energy to it during a light flashing period, a timing signal generator (34) connected to the lamp's regulator (22) to generate a start signal pulse for initiating a light flashing period and a stop signal pulse for ending the flashing period, equipment (42, 44, 50, 52) for regulating the flashing period and connected to said time signal generator for setting the time between said start signal pulse and said stop signal pulse, said equipment having a control input for a short flashing period and a control input for a long flashing period, equipment (46, 48, 54, 58) for regulating the darkened space connected to said time signal generator (34) for setting the time between said stop signal pulse and said start signal pulse, said equipment having a control input for a short blacked out period and a control input for a long blacked out period , and a counting device (40) with a set of consecutive counting outputs, the number of which is chosen equal to the number of flashes of light in said previously selected sequence, each of said outputs being connected to selected inputs of said control inputs for regulating said light flashing periods and darkened spaces, thereby in advance to determine the duration of light flashes and darkened spaces at each place in said previously selected sequence, and the counting device has its clock input connected to said time signal generator for receiving each of said start signal pulses with the aim of bringing each counting output to have a signal duration equal to the time between its clocking start signal pulse and the next such start signal pulse. 2. Apparatus as specified in claim 1 and which further comprises a device (36) for generating synchronization pulses and which is connected to said lamp regulator and has an output/input terminal (37) for synchronization, the device for generating synchronization pulses being arranged for to be controlled to produce on said output terminal a short first synchronization pulse at the beginning of each flashing period in said sequence. 3. Apparatus as stated in claim 2, characterized in that said synchronizing generator produces a short second synchronizing pulse over said synchronizing output only during the zero count step for said counter. 4. Apparatus as stated in claim 2, characterized in that said lamp regulator is arranged to energize the lamp in response to a first synchronization pulse received from outside via said output/input terminal for synchronization. 5. Apparatus as stated in claim 4, characterized in that the counting device is arranged for resetting to its zero counting stage in response to another synchronization pulse received from the outside via said output/input terminal during a flash of light. 6. Apparatus as stated in claim 1, and where said equipment for regulating the flashing period and darkened space includes: a set of flash ports (42) for short light flashes and connected to the lamp controller and arranged to be activated by the latter when a short light flash is required, a set of dark gates (46) for short darkened space and connected to the lamp controller and arranged to be activated by the latter when a short darkened space is required, a set of flash ports (50) for long flashes of light and connected to the lamp controller and said counting device, and arranged to be activated by the lamp controller and said counting device when a long flash of light is required, a set of dark gates (54) for a long darkened space and connected to the lamp regulator and the counting device, and arranged to be activated by the lamp regulator and said counting device when a long darkened space is required, a set of electronic switching means (44, 48, 52, 58) with switches respectively connected to said short flash ports, said short dark ports, said long flash ports, and said long dark ports, and a timing circuit with series resistors (60, 62, 64, 66) and capacitor (68), where the capacitor is connected to all of said electronic switching means, and wherein said resistors are separate resistance elements connected to each of said electronic switching means, so that activation of one of said ports and an assigned one of said electronic switching means to close and thereby connecting that of said resistors assigned to the closed gate in series with said capacitor to determine a selected long or short duration. 7. Apparatus as specified in claim 6, which further includes: a daylight regulator (70, 72) arranged to respond to incident light from the surroundings to switch off said time signal generator when the incident light is stronger than a pre-selected level, and also to respond to incident light from the surroundings to switch on said counting device when said incident light level decreases below such predetermined level. 8. Apparatus as stated in claim 7, where said daylight regulator further comprises: photocell equipment (72) arranged to receive incident light from the surroundings, and comparator equipment (162) connected to said photocell equipment to compare the output signal from the photocell equipment with a predetermined threshold value. 9. Apparatus as set forth in claim 7, characterized in that the daylight regulator further comprises gate equipment connected to said time signal generator to prevent the comparator equipment from working during lamp dimming. 10. Flashing light system for buoys and the like with a number of mutually separated flashing light units which are; mutually connected via communication connections (39), said turn signal beacon being arranged to produce a pre-selected sequence of light flashes and darkened spaces representing an identification code or the like, while all turn signals flash in synchronism, characterized in that the system includes: a lamp device (24) in each of said turn signal units, equipment (22) in each of said turn signal units to produce flashing periods and dark periods by means of a set of lamp control pulses, said set of pulses determining the pre-selected sequence and energizing the lamp equipment during the flashing periods in said set, a device (37) for producing synchronization pulses in each of said flashing units at the beginning of each flashing period, output means (37) connected to said device for generating synchronizing pulses and arranged to transmit these synchronizing pulses from each of the turn signal units to all the other units, as well synchronizing equipment (40) in each of the turn signal units for resetting the equipment for producing flash and dark periods to the beginning of a pulse set, when a synchronizing pulse is received from another turn signal unit in such unit which is out of synchronism. 11. System as stated in claim 10, characterized in that said synchronization pulse equipment produces a first synchronization pulse at the beginning of each light flash and another synchronization pulse after the first pulse only during the first light flash in said pulse set, said synchronization equipment only reacting to the second synchronization pulse. 12. System as specified in claim 11, which further includes: photosensitive equipment (72) for generating a sequence of blocking control signals in response to receipt of incident daylight, in that said equipment for producing flashing light and dark periods reacts to said control signal by ceasing to produce said lamp control pulses. 13. System as stated in claim 12, characterized in that said equipment for producing flashing light and dark periods is arranged to react to said control signal only when synchronization pulses are not received from other flashing light units in the system. 14. System as set forth in claim 12, characterized in that said photosensitive equipment comprises control means (150) to generate said lamp control pulses in the absence of incident daylight, said control means comprising a blocking device (64) to prevent the generation of said sequence-blocking control signal while darkening said lamp. 15. System as specified in claim 11, characterized in that each of the turn signal units is designed to be operated independently of the other units in the system, so that said units are not affected by failure of said communication lines. 16. Apparatus for producing a preselected sequence of light flashes and darkened spaces from a lamp (24) and comprising: a lamp regulator (22) connected to the lamp for energizing it during a light flashing period, time signal generator (34) connected to the lamp regulator (22) to produce a start signal pulse for initiating a light flashing period and a stop signal pulse for ending the flashing period, equipment (42, 44, 50, 52) for regulating the flashing period and connected to said time signal generator (34) for setting the time between said start signal pulse and said stop signal pulse, said equipment having a set of flashing ports (42) for short flashing period and connected to said lamp regulator and arranged to be activated by this when a short flashing light is required, and equipped with a control input for short flashing period, as well as a set of flashing ports (50) for long flashing period and connected to the lamp regulator and arranged to be activated of this when a long light flash is required, as the flash ports for a long flash period have a control input for such a long period, equipment (46, 48, 54, 58) for regulating darkened spaces and connected to said time signal generator (4) for setting the time between said stop signal pulse and said start signal pulse, the equipment for regulating the dark period having a set of gate (46) for a short dark period and connected to the lamp regulator and arranged to be activated by the latter when a short dark period is required, and said dark gates for a short dark period are equipped with a control input for such a period, as well as a set of darkening gates (54) for a long period of darkness and connected to the lamp regulator to be activated by the latter when a long darkening period is required, said gates for a long darkening period having a control input for such period, a counting device (40) with a set of consecutive counting outputs, the number of which is chosen equal to the number of flashes of light in said previously selected sequence, each of said outputs being connected to selected inputs of said control inputs for regulation of said light flashing period and darkened spaces, thereby in advance to determine the duration of light flashes and darkened spaces at each place in said predetermined sequence, and the counting device has its clock input connected to said time signal generator for receiving each of said start signal pulses with the purpose of bringing each counting output to have a signal duration equal to the time between its clocking start signal pulse and the next start signal pulse of this kind, a set of electronic switching means (44, 48, 52, 58) with switches respectively connected to the outputs of said short-flash ports, said short-darkening ports, as well as the long-pulse ports and said long-darkening ports, a timing circuit with series-connected resistor and capacitor and whose capacitor (68) is connected to all of said electronic switching means, and in which the resistance of the circuit is a separate resistance element (60, 62, 64, 66) connected to each of said electronic switching means, so that activation of one of these ports brings the associated electronic switching means into a closed state, thereby switching off said resistor assigned to said closed port in series with said capacitor to create a selected long or short duration. 17. System of flashing beacons for buoys and the like and with a number of mutually separated flashing light units which are interconnected via communication lines (39), each such flashing beacon producing a predetermined sequence of flashing lights and dark periods which together represent an identification code or the like, all flashing beacons flashing in synchronism, characterized by the system comprising: a lamp device (24) in each of said turn signal units, equipment (22) in each of said turn signal units to produce light flashing and dark periods by means of a set of lamp controller pulses for each sequence of such light flashes and darkened spaces, said set of pulses defining the preselected sequence, and the pulses energizing the lamp device during the flashing periods in each set, equipment (37) for generating synchronizing pulses and arranged to generate a first synchronizing pulse at the beginning of each light flash and a second synchronizing pulse after the first such pulse and occurring only during the first pulse in said pulse set, output devices connected to said generator device for synchronizing pulses for the purpose of transmitting said synchronizing pulses from each of the turn signal units to all other turn signal units, and synchronizing equipment (40) in each of said turn signal units for resetting the relevant unit's equipment for producing light flashing and dark periods until the beginning of a pulse set, when synchronizing pulses are received from another turn signal unit by such a unit that is out of synchronism, said synchronizing equipment being arranged to respond only to said second synchronizing pulse.