JPS60501133A - Synchronized and daylight-controlled flashing devices - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Synchronized and daylight-controlled flashing devices field of invention The present invention relates to a lamp flashing device, and more particularly to a lamp flashing device that flashes a lamp with a specific code sequence. The present invention relates to a device that emits light and synchronizes a large number of lamp blinkers.

Background of the invention Buoys and beacons floating at sea generally indicate channels, obstacles, and other navigational features. In order to It uses an incandescent lamp that flashes periodically with a flash. Many of these devices It is battery-operated, so saving mains power is important. Recently, motors and Transistor-based timing and A control circuit is used. For example, 5eidler U.S. Pat. No. 3,244. , No. 892, No. 3.310.708 and No. 3,596,113. sea bream. In order to obtain a reliable and precisely timed signal, adjust the voltage. There must be. To remove the relay, a transistor switch is used ing. Known regulating and switching transistors generally minimize voltage drops. This is a germanium-type product, which has a high leakage rate, especially at high temperatures. Hey. Using silicon transistors reduces leakage at high temperatures, but reduces voltage drop. The bottom gets bigger.

In many applications, many beacons and buoys need to operate in synchronization. Yes, typically a master flasher controls a set of slave devices. this square If the controller fails, the slave will function improperly. Therefore, main power consumption Any device can synchronize with each other, minimizing costs and Even if the equipment fails, it will not fail and still be able to generate almost all coded signals. There is a need for a flashing control circuit that is flexible and easily programmable.

Summary of the invention The present invention provides a new and improved lamp system that overcomes problems common to known devices. related to control equipment. Voltage regulator and switching circuits are low leakage silicon transistors. transistors with new, thin connections that reduce voltage drops. The current to the lamp is Monitored during flash and closes the lamp selector switch when a lamp failure is detected. energizes the automatic lamp changer.

is a solid-state flash sequence type that uses integrated logic circuits in most parts. A configuration circuit is provided. almost all coat sequences, i.e. long and short flashes and a block can be formed. Sequence forming circuit sequentially flashes and shuts off An electronic counter is used that forms one count for each pair of . 1 set electronically The RC time constant that is switched is controlled by this counter, and each successive set of flashes The desired flash and cut-off times are formed for and cut-off. A given flash-interception consisting of The time constant chosen for the flash-out period is such that the time constant is control the timing signal generator that times the data.

When multiple flashers are to be operated together, the present invention allows for flashing and shutting off. can be synchronized. A synchronization pulse is generated at the beginning of each flash and is sent to other blinkers in the system via other links. All flashers are synchronized If not, the sync pulse resets all other blinkers and synchronizes. Be taken. Conveniently, any blinker can act as a master. and other flashers can work as slaves. Therefore, the master is broken Even if the flasher is turned on, other flashers will not be affected.

A daylight controller is also provided to disable the flash during the day to save mains power. . When the sun sets, this daylight controller starts operating at least one flasher. be done. A synchronized pulse from this first enabled blinker causes other blinks to devices will operate automatically regardless of whether their daylight controller is triggered or not. be done. In the morning, all flashers are activated until the least sensitive daylight controller is activated. all flashers will stop flashing when this less sensitive daylight controller is activated. Melt. Therefore, a very sensitive daylight controller installed in the flasher can quickly detect this point. If an attempt is made to make the device inoperable, the synchronization pulse from the operation is maintained, creating a fail-safe device.

Therefore, the main object of the present invention is a flasher for use in a synchronous flasher system, which , to form the desired sequence of long and short flashes separated by long and short interruptions. It also generates a synchronization pulse to synchronize other externally connected flashers. The objective is to provide a flasher that

Another object of the invention is to use the system in which a large number of flashers are interconnected by communication links. flashers with daylight controllers for and all points until the least sensitive daylight controller renders the flasher inoperable. The device is configured to continue flashing, and the level of ambient light decreases Flashers such that the flasher being operably activated initiates the flashing of all other flashers. The goal is to provide the following.

Yet another object of the invention is to include a silicon transistor switch and regulator. We have developed a flasher that reduces the voltage drop across the regulator when the supply voltage drops below the regulated value. It is to provide.

Still another object of the present invention is to configure a goo13f1f circuit for the first current level. and the single regulator circuit G is connected to switch at the second current level. By providing switches and voltage regulators using silicon transistors. Ru.

Yet another object of the invention is to operate the switching transistor at a preselected low voltage. Switch and adjustment using a Goo13F1F circuit modified to be driven by descent. The goal is to provide equipment.

Yet another object of the invention is to determine when a lamp has failed and to automatically To provide a lamp current sensing circuit for energizing a lamp switching mechanism. .

Yet another object of the invention is to minimize power consumption for the power supply and to extend its lifespan. G) Novel lamp flash sequence using long and low cost integrated logic circuits The purpose is to provide a formation circuit.

Yet another object of the invention is to provide a highly versatile system without the use of mechanical devices, relays or motors. Provides a sequence forming circuit that allows selection of various long and short flash sequences. It is to be.

Yet another object of the invention is to provide a step-by-step counter controlled by timing pulses. The sequence forming circuit used is such that the counter is activated by the first timing pulse. advances to the next count, and the time until the next timing pulse is determined by that count. control based on the required length of flash and interruption, and the next timing) To provide a circuit that generates an pulse and advances the counter to the next count. That is.

These and other objects and advantages of the flashing system of the present invention will be apparent from the detailed description below. It will become clear from the attached drawings.

Brief description of the drawing FIG. 1 is a waveform diagram showing a simple code sequence for the flasher shown in FIG. the law of nature, FIG. 2 is a simple functional block diagram of the flasher of the present invention, and FIG. 3 is a communication link diagram. is a simple functional diagram showing a system of flashers interconnected by FIG. 4 is a circuit diagram showing the voltage regulator and switch portion of the blinker; FIG. 5 is a schematic diagram of a logic circuit forming a series of blinker flashes, and FIG. 6 shows the two cycles generated by the blinkers shown in FIGS. 4 and 5. FIG. 3 is a waveform diagram showing a series of flashes.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 2 is a very simple functional block diagram of the lamp control and synchronization device of the present invention. 1, which shows some of the waveforms that occur during operation of the device described above. The basic operating mode will be explained.

The ramp 24 shown in FIG. It is an incandescent lamp installed on a buoy or something like this. of a particular buoy or structure. run in a specific sequence to form a code for instructing the vessel to display It is necessary to flash the screen 24. Figure 1 illustrates a specific flash cycle. Although shown for the purpose of Please understand that this can occur. Curve B represents a chord consisting of three chord elements. It shows a series of flashes FL forming.

In this case, two short flashes and one long flash represent the Morse code letter U. are doing. The first short flash 10 is, for example, about 3/10 seconds. Then, la The lamp is turned off for a short time as indicated at 12. "Cut off" this off-time EC It is called. This block is followed by another short flash and a short block. long indicated by 16 The flash is considerably longer than the short flash, and in the example shown is about 3 times the length of the short flash. times, or about 1 second. Long interruption following completion of Morse letter U 18, at which point the code letter repeats again. The flash and block ratio is , it should be understood that can be changed as desired. To give one timing example, The short flash is 0.3 seconds on, 0.7 seconds off, and the long flash is 1 second. It is on for 3 seconds and off for 3 seconds.

Referring to FIG. 2, lamp 24 has a lamp system that closes the circuit to one side of the lamp. The control circuit 22 causes the flash to be emitted, ie, turned on. general primary Alternatively, power may be provided by a power source 32, which may be a secondary battery or other type of power source.

To maintain long lamp life, the flash output voltage is controlled by regulator 28. This regulator 28 effectively controls the maximum voltage that can be applied to the lamp 24.

The current flowing through the lamp 24 is monitored by a lamp current sensor 26. below As will be described in detail, when monitoring current according to the present invention, the lamp 24 No series resistance is required in the circuit. From lamp controller 22 appearing on lead 27 This instruction instructs the lamp sensor 26 that the lamp 24 is on. child When the lamp current is not within the normal range of the lamp 24, the U.S. patent 3.308,338 - automatic lamp changer 30 disclosed in US Pat. A control signal is sent to - to replace the unit with a new unit. The regulator 28 further includes: Means are provided for adjusting the operating voltage sent to the electronic flasher control circuit of the present invention.

The following describes how the present invention provides the necessary control of lamp 240. Bell. The power mounter 40 is 10, 12, and 7 in FIG. Used to determine the time for each set of flashes and interruptions such as 16 and 18 . As mentioned above, times IO and 12'L, times 16 and 18 are also quite short. Therefore, counter 40 has various lengths of counting time throughout its cycle. controlled to give In the example shown here, the model is shown as curve B in Figure 1. Only three count times are required to emit the flash representing the rule code U. . Therefore, in one cycle, counter 40 goes from 0 count to 1 count. Then, it advances to count 2, and then outputs count 3 to counter 4. It is automatically reset by connecting to the 0 reset terminal. Therefore, cow The printer repeats operation as shown by curves C, D and E, with short pulses 14 to 0 output. , a short pulse 15 on one output, and a long pulse 20 on the second output.

The control for forming the long time and short time is a set of switches 44.48.5 2 and 58 and their combined resistances 60, 62, 64 and 66. It will be fulfilled. At a certain count, the desired resistor is switched and the key The capacitor 68 (C1) is charged and the flashing and blocking occurs during its output pulse of the power converter 40. The length of the break is controlled by its time constant. In the example shown here.

Resistor 60 (R1) provides counter output pulses 14 and 14, as described in detail below. 15 to give a time constant proportional to the length. The switch 44 is controlled by a flash circuit 42 to form a short flash 10. Required gate control signal is generated by the lamp control circuit 22. Similarly, resistor 62 (R2) is controlled. The controlling switch 48 is controlled by a short cut-off gate 46, which also It is controlled by a lamp control circuit 22. Therefore, the value of resistor R2 is Determine the flash time 12, and for this purpose, the same flash time and cut-off time are required. In this case, R1 and R2 are set to the same value. In the example of For example, a ratio of 3 to 7 is commonly used.

Similarly, switches 52 and 58 control resistors 64 (R3) and 66 (R4). The long flash is controlled by the time constant of the selected resistor and capacitor 68 (C1). A time 16 or a long cut-off time 18 is formed. It gave a long flash and a long block. For this purpose, a set of gates 50 and 54 each having four inputs are used. Therefore , can give 4 long flashes and 4 long blocks in one cycle. can. However, the present invention is not limited to such a number; Additional Kate inputs may also be provided for the target. in the flash cycle The selection of points at which long flashes and long interruptions are required is determined by gates 50 and 54. By connecting the input to the counter output that occurs at the desired point in this cycle It is done. In the example shown here, the third count, which is count 2 of curve E, A long flash 16 and a long block 18 are desired, therefore the gates 50 and 54 are The input is connected to the count 2 output of counter 40. This is a long flash and Since this is the only count in the cycle that requires disconnection, other gate inputs is grounded.

The control for producing long and short outputs from the counter 40 is controlled by the clock timing signal generation. It is provided by using a generator 34. As detailed below, this Lock timing signal generator 34 includes a series of timing signals as shown by curve A in FIG. A timing pulse is generated via lead 35 to lamp control circuit 22. These pulses The time between R1 and R4 is controlled by the selection of resistors R1 to R4. sea bream The timing pulse is the start of each flash or block required and the timing pulse of each flash or block required. It is a short pulse in the center ranging from 1 ms to 10 ms. These types The timing pulse is passed through lead 23 by path 22 to counter 40 in the lamp control diagram. Sent to the clock input to stop the counter at one count immediately after the start of each flash. . A first pulse 11 called a start pulse and a third pulse called a stop pulse If the time between the start pulse and the start pulse 13 is short, the flash lamp control circuit 22 enable gate 42 during the stop pulse and enable gate 46 during the stop pulse. Both of these occur during the → runt O from the callan multi 40.

Therefore, resistors 60 and 62 are switched sequentially. As is obvious, start When gate 42 is enabled by pulse 11, the short time constant of RICl , the clock timing signal generator 34 forms a pair of stop pulses 13. This causes the lamp control circuit 22 to enable the short cut-off gate 46. Ru. Similarly, when the long flash duration start pulse 17 occurs, the counter 40 When stepping so that the output pulse 20 is generated at the two outputs, the pulse 20 causes One input of gates 50 and 54 is enabled. At this time, the lamp control circuit A flash pulse appears from 22 through lead 41 to long flash gate 50, which Gate 50 operates switch 52 to connect resistor R3 to capacitor C1, causing a long flash. form a long time constant for 16. Stop timing pulse 19 is lead 3 5 to form a flash lamp control circuit.

The present invention also provides a daylight control subsystem including a daylight control circuit 70 and a photoself 2. It is also equipped with The purpose of this control is to disable the flash system during daylight hours. and to turn on this system at night. As detailed below, During the day, i.e. when sufficient incident light hits the photoself 2, the clock timing The timing signal generator 34 is prevented from generating timing pulses.

When the system is turned on, all units of the system are at curve B in Figure 1. Preferably, operation begins at the beginning of the indicated cycle. Therefore, −ramp control circuit line 22 generates a short synchronization pulse at the beginning of each flash and during the first flash of each cycle. do. In the example shown here, the pulse 11 shown in curve A and the second timing pattern The synchronization pulse is externally connected from output line 37 for purposes described below. I can put it out. The synchronization pulse also causes the clock timing signal generator 34 to The first flash is reset at the beginning of the cycle via the control circuit 22 and the counter 40. Reserve the sequence to start.

Now, FIG. 3 shows an array of N flashers, each of the type shown in FIG. body is shown. When each photoself 2 is exposed to enough light, all flashers As mentioned above, its operation is prohibited. The purpose of the invention is to It is to turn on all the devices at the same time and synchronize them. In general, all photocells feel It is impossible to make the degrees the same, and even if this were possible, Since each flashing vessel is in a different position, the light entering each cell will usually have the same intensity. No. For purposes of illustration, all blinkers are off, and blinker 2 is turned off as described above. The light incident on the photocell has decreased sufficiently to cause the flasher to start operating. Assume. When this happens, the leads 11 from the lamp controller 22 in FIG. The synchronization signal appearing at 29 is sent to lead 37 via synchronization output 36. in this case , the synchronization pulse passes through link 39 to flasher L, flasher 2, and other flashers in the array. Sent to flasher. Therefore, when each of the other blinkers receives a synchronization pulse, its The clock timing signal generator 34 and counter 4o are reset, and each point override the daylight controller 7o. The daylight controller 70 is a flashlight lamp. Operation is inhibited by a control signal sent from the step control circuit 22 via the lead 71. ing. It should be noted here that each blinker generates its own synchronization signal and all all synchronization signals appear on each output lead 37 simultaneously. Light conditions change For example, when energizing Photoself 2, the least sensitive flasher is the daylight controller. Requires all flashers to continue flashing until finally turned off by 70 It is also an object of the present invention to do so. Here, photoself 2 of flasher 3 is the last unit to receive enough light to render the flasher inoperable. do. At this time, all other flashers are connected to the daylight controller 70 by their photocells. is controlled so that the blinker stops flashing. However, lead from flasher 3 The sync pulse that appears at the sync input of each other blinker via 37 It functions to maintain movement.

However, the flasher 3 is eventually turned off when enough light falls on the photoself 2. Then, the synchronized pulse disappears from the beam part 37 and therefore all flashers turn on at the same time. Funiru. Figure 3 shows the conductive lines 39 between the leads 37 of each flasher. , any form of interconnection may be used, determined by the state of the flasher! I hope you understand that this will happen. For example, for large structures such as oil rigs, A cable connection will be used and a radio link will be used for the buoy. Such mutual contact The connection means are not considered to form part of the invention.

The basic operation of the present invention has been described above, but the specific novel circuit will be described below. will be explained in detail. FIG. 4 shows the current fA regulator and lamp circuit sensor section of the present invention. It is a circuit diagram. This circuit consists of three basic elements: voltage for the electronic circuit; regulator 80, voltage regulator 90 for controlling the voltage applied to the incandescent lamp 24; , a lamp operating a switch consisting of transistors 20-5.202 and 109. A current sensor 26 is provided.

The present invention is mainly used for flashers operated by a power source. do. Variable power supplies have output voltages that vary over the battery life or charging cycles. become To maximize the life of an incandescent lamp 24, adjust the voltage applied to the lamp. It is necessary to make adjustments. Also, in the case of battery operation, the battery voltage may be higher than normal. Minimizes losses in the regulation circuit to maintain proper operation when ramping down to lower values It is necessary to. This uses germanium power transistors to This is accomplished in part by switching and regulating the heat lamp current. main sweets In the case of germanium transistors, the voltage drop between switching transistors is approximately 0. 5 QL can be maintained at 0.6 volts, but these devices have large leakage current. , which increases with temperature. However, in this regulator 90, the main switching and A silicon power transistor 92 was used as the adjustment element. convenient thing In addition, when the battery voltage is low, the silicon transistor switch and regulator Maintains a significantly lower voltage drop across transistor 92 than previously possible We were able to. Transistor 92 is driven by transistor 94; This transistor is then driven by transistor 96. main tran When the register 92 is canted off, 3 The collectors of transistors 94 and 96 are connected to transistor 9 by diode 93. 2 to form a Darlington circuit. transistor 94 and The collector of 96 is connected to the negative side of the power supply via a bypass resistor 95, which The circuit in Figure 4 is considered to be grounded. Differential amplifiers 98 and 99 are connected to a voltage reference zener 97 in the rectifier circuit and the collector of transistor 92 Used to control voltage. When lamp 24 is first turned on, the emitter-base junction of transistor 92, transistors 94 and 96, diode A drive current flows through the node 93 and the load. However, the components of the transistor 92 As the collector voltage increases, diode 93 becomes reverse biased and Therefore, the drive current flows through the bypass resistor 95 to ground. Therefore, the circuit is From a Darlington circuit, a single transistor driven by another transistor The drive current is not part of the load current in this circuit.

When transistor 92 conducts, incandescent lamp filament 24 is initially energized. When the filament is heated, a large current is drawn, and as the filament heats up, the resistance value becomes - thicker. , reducing the required drive and load current.

The resulting collector voltage, and therefore the voltage across the lamp 24, is 7 and the setting of the resistor 201 in the adjustment circuit formed by the transistors 98 and 99. determined by. The current of transistors 94 and 96 flows through bypass resistor 95. , the minimum voltage drop between the emitter and collector of transistor 92 is It is no longer limited by the collector-emitter voltage of register 94" and 96. Input Voltage drops below the desired regulated output voltage for a typical Darlington regulation circuit Then, the minimum voltage drop across transistor 92 is such that the input voltage is at the desired regulated output voltage. Close to the value determined by the voltage drop across transistors 94 and 96 when Make.

When the supply voltage is greater than the desired regulated output voltage, resistors 205 and 10 A voltage divider formed by 3 provides zener 97 with a voltage greater than its zener voltage. Therefore, the base of the differential amplification transistor 98 is It is kept constant at the reference voltage provided by Zener 97. The base of transistor 99 The voltage on the bus is adjusted by a voltage divider formed by resistors -197 and 201 determined from the lamp voltage. The ratio of resistor 197.201 is transistor 92 Only the current that provides the desired maximum output voltage at the collector of transistor 94 and and 96.

The supply voltage to the emitter of switch transistor 92 is adjusted to the desired regulated output voltage. When the voltage at the base of transistor 98 approaches or decreases below the value of is below the breakdown voltage of Zener 97, and voltage divider 205.103 The value is determined by the ratio. The base voltage of transistor 99 is divided by voltage divider 19 It is determined by the ratio of 7.201. The ratio of resistor 205.103 is the switch transistor to form a predetermined low emisocous collector voltage drop across resistor 92. is adjusted to However, this voltage is voltage drop when the voltage is on. Therefore, Zener 97 is non-conducting. When resistor 103 is added to form divider 205.103, transistor 9 2 to the desired minimum voltage drop across transistor 92 at a given load current. The current can be limited to the required to maintain it below.

Transistor 92 switches the load on and off without regulating the load voltage Another configuration of the circuit shown in FIG. 4 requires only 15 In this case, the Zener diode 97 is removed and the switch transistor 92 is to prevent saturation at very low values 96 and 94 over a wide range of supply voltages. . Without resistor 103, the drive current of transistor 92 would be the same as that of resistors 95 and 211. Limited only by value. In such cases, it is necessary to provide sufficient drive for large current loads. Choosing resistor 95 to supply dynamic current would be extremely large for high current loads. A high drive current is generated and energy is wasted. If there is a resistor 103, the drive The dynamic current is selected across transistor 92 for the instantaneous or steady-state value of the load current. The drive current is dynamically adjusted to only the value necessary to maintain the voltage drop, and the drive current is A small fraction of the load current can be maintained for maximum efficiency.

As is clear here, 98.99 is related to the differential width and 94.96 to the drive. A novel voltage divider reduces the drive current even at a given lamp load current. The voltage drop across the switch transistor 92 can be brought close to saturation without making the voltage too large. can be done.

To illustrate the specific operation of the novel regulator 90, the input voltages are 13 volts and 18 volts. volts and that an output of 12 volts is desired. input voltage is in the range of 13 to 18 volts and with resistor 103 removed, first The first step is to adjust resistor 2.01 to give an output voltage of 12 volts. Is Rukoto. The input voltage is then set to a value lower than 12 volts, for example 11 volts. decreases to Then, the resistor 103 is inserted and the light is blinked.

The voltage drop across the bypass resistor 95 will decrease if the lamp filament breaks; This voltage can therefore be used for sensing such disconnections. Therefore, No sensing resistor is required in series with lamp 24, and the power generated by such a resistor is loss is removed. Therefore, the voltage across the bypass resistor 95 caused by the drive current is sensed by comparator 195. If lamp 24 burns out, comparator 1 -95 controls transistor switch 202, which in turn switching transistors 204 and 109 are made conductive and the automatic lamp changer is energized. . This serves to remove the burnt out lamp 24 and insert a new lamp.

A regulator 8 that provides regulated power to the timing circuit and comparator 195 of the present invention. 0 is a simple voltage using transistor 206, zener 208 and resistor 108 It is a regulator.

A preferred embodiment of the electronic flash control circuit and timing circuit of the present invention is illustrated in circuit diagram form. 5, but other circuits that perform the desired function will be apparent to those skilled in the art. . The operation of the circuit shown here can be seen in Figure 6, which shows the waveforms appearing at various points in the circuit. I will refer to and explain.

As discussed above with respect to FIG. A variety of coded signals can be flashed by forming flash cycles up to By selecting the values of capacitor 68 and resistors 60, 62, 64 and 66, The duration of flashes and interruptions can be controlled. 10 using many counters In the case of the circuit, a period of 6'Im (N=6) is selected for illustration purposes, and the counter 50 are connected to form a coded flash sequence shown by curve T in FIG. . The sequences of two dashes, two dots and two dashes are of course , is an arbitrary code for explanation. short intervening spaces between successive code elements The setting is obvious. What should be noted in FIG. 5 is that the counter 40 The component outputs 0 and 1 are connected to two inputs of the 4-person gate 146, While forming two long flashes at the beginning of the code, counter outputs 4 and 5 are Connected to two inputs to form two long flashes at the end of the cord It is.

One human power of the four-man gate 148 is connected to the count output 5 and form a long block at the end of the code. Other inputs should be grounded as described above. It is.

Flip-flops 101 and 102 are important timing elements of the circuit.

As shown in curves G and H of FIG. 6, flip-flops 101 and 102 is the high level or low level output from the b output of the Free Knob-Flo Knob 102. Each time a pulse is issued, the flip-flop 101 has the same high and low levels. are interconnected to produce a pulse at its d output. For example, when , flip-flop 101 receives a high level pulse 171 and then a low level pulse. pulses 172, each pulse being half the width of high level pulse 170. subordinate Therefore, flip-flop 102 changes state twice when flip-flop 101 changes state. Changes the state once every time. Kuro Tsuku Kuimi generally indicated by number 34 The leg signal generator leads a series of timing pulses as shown in curve F. 35 and these pulses are timed by the flip-prop 101. Both are input to a large number of gates and used to control various gates.

For the start sequence of the flash control device, the circuit follows curve F in Figure 6. Assume that the timing lamp is off and the timing lamp is off. This is explained by Counter 40 is at its sixth count. counter 40 completes its sixth count, which appears at output 5 and counter 40: As shown, it increments to its N+1 or 7th count, which is the output 6 and is connected to the recent input of counter 40 via OR gate 132. . This reset pulse to counter 40 causes flip-flop 101 and When both 102 appear from the lycee 34 to the lead 35, all of Noah Gate 110 The input of will be low level and its output will be high level. At this time, or gate 12 6 becomes a high level, and one of the NOR gates 112 and 114 A high level signal is generated at the input. Noah gate 114 is one of the or gates 125. A low level signal is generated at one input of the OR gate 125, and a NOR gate is generated at the other input of the OR gate 125. A low level signal is sent from port 112. Therefore, it occurs at the output of the OR gate 124. The low level signal generated turns off transistor 141.

The collector of transistor 41 is connected to input X in FIG. Lamp switching transistor 92 is controlled via transistors 98 and 99. Tran When resistor 141 conducts, point X becomes low level, cutting off the current to lamp 24. do. Therefore, when OR gate 124 turns off transistor 141, the lamp 19 A high level signal is given to one input of 120 (while the medium power of 110 is 120). Ru. Then, the signal and signal become high level, and the high level signal is applied to the input of the NOR gate 118. give a number. This NOR gate also receives a low level input from lead 35. Therefore, Noah Gate 12.0! , generates a low level output, and transistor 125-! on and set its collector and synchronous output lead 37 to high level.

This forms the tip of the synchronizing pulse 17i shown by curve S in FIG.

Synchronization pulse 178 occurs essentially simultaneously with start timing pulse ]74. Please note that. When the start timing pulse 174 becomes positive (rear end), Flip-flops 101 and 102 are timed and shown by curves G and H. Then, the output of NOR gate 110 becomes low level, and the output of NOR gate 102 becomes low level. bring it to a high level. Therefore, transistor 125 is turned off and leads 37 . but Becomes a low level. Therefore, the synchronization pulse 178 is formed in the lead 37 by the above action. will be accomplished. When transistor 125 turns on, transistor 121 also turns on. As a result, transistor 123 is turned off.

Before the start timing pulse 174, transistor 123 is turned on and the key is turned on. The capacitor 145 is charged. When the first sync pulse 178 occurs, the AND game One input of capacitor 136 is at a high level, and the other input is the charge on capacitor 145. to discharge capacitor 145 to inhibit high level signal 136. selected. This action causes the sync pulses 178 and 180 to be shorted on the red wire 161. Time overlaps prevent lead 161 from remaining at a high level. like this , a lock condition occurs at the reset input of transistor 139. flip - Flops 101 and 102 are activated by short cent pulses 182 (curve J in Figure 6). is set and reset via gate 132 by a short pulse 183; This also applies to Kaunk 40. And gate 13 via lead 161 The short pulse 183 sent to the clock timing signal generator 34 It is also sent to the base of register 139 to reset this generator. and gate 106, both human powers will be at high level and hence the reset pulse will cause the counter to 40 is propagated to reset.

The output of the NOR gate 118 is the timing that occurs in the middle of each flash of the flash sequence. Note the high level during pulse 176. The counter shown in curve M When a zero output is present, timing pulse 176 causes curve S in FIG. A second synchronization pulse 180 is generated. Therefore, this pulse 0, causing the signal on the sync output line 37 to go high.

Inverter 130, whose output is connected to one input of Y node gate 128, during the last count of counter 40 if the flash is a long flash. Inhibits reset pulses that may result from work like that. Synchronous output 37 The second synchronization pulse 180 appearing at is sent to all six other blinkers in the network. , synchronous line 37 via corresponding gates 136.138.106.128 and 132 Reset each counter in other blinkers connected to the .

1 if all flashers in a group are out of sync. Reset all other blinkers except the one doing the last count. Naturally However, when such a blinker reaches the θ count, a sync pulse is generated and restarts. set, thus resynchronizing all other blinkers to that blinker.

From the above explanation of the lamp on-switching sequence, the lamp off-switching Eha, this is a low level Belian car to Noah Gate 114. This is a high level to Or Gate 124. It is clear that it is controlled by - giving an input and turning on transistor 141. It will be clear.

Transistor 141, when conductive, provides a signal to the lamp switch circuit of FIG. Apply a low level input to the X input and turn off the lamp.

NOR gate 112 keeps transistor 141 on until the next on signal occurs. It works as a holding lunch. During the on-pulse, the high voltage from the output of AND gate 104 The level signal centers flip-flops 101 and 102, Ql and Q2 to a low level. During cut-off, transistor 105 conducts and capacitor 10 7 and its output is set to high level by the synchronization signal to AND gate 104. , cents Frifbufurosop 101 and 102. Transistor 105 is turned on. , discharging capacitor 107 and inhibiting AND gate 104 . follow This shortens the cent pulse and keeps the capacitor discharged during the flash period. will not appear again. During synchronization, the counter from the output of AND gate 138 Both the reset and synchronization pulses trigger the clock timing signal generator. register 139 and resets it as described below.

The next timing pulse 176 is indicated by pulses 171 and 170 in FIG. This occurs while 5 and σ7 are both high and bell. Part of Noah Gate 118 If the power source 35 is connected to one person's power, the level will be low. The 0 output of the counter 40 is , the level becomes high as shown by curve M in FIG. The second human power to port 118 is reduced to a low level. Ql and Q2 outputs are at low level. and sends a low level signal from the output of the OR gate 116 to the third human power of the NOAH gate 118. send. Therefore, its output becomes high level, which causes one input of NOR gate 120 to the other input is held at a low level by the Noah gate 110. . The output of NOR gate 120 then goes low, causing transistor 125 to turned on, and as described above, the input to the NOR gate 118 is input to the high level synchronization pulse. goes high, causing the synchronization output line 37 to go low. At Noah Gate 118 Therefore, in order to be able to generate synchronizing pulses, the inverter 122 is connected from the counter 40. It is necessary for the input sent to the Noah gate 118 to be at a low level. It is. This only occurs during the 0 count and is therefore the same during the rest of the cycle. period pulse does not appear. Lead 16 during second sync pulse 180 during 0 count The clock timing signal generator 34 is generated once again. Reset the AND gate 106, AND gate 128 and OR gate 132. via the flip-flop 10] and the reset terminal of the flip-flop 102. light here As is clear, sync pulses 178 and 180 of sync output 37 are interconnected. Appears on all other blinkers. Incoming synchronous pulse cormorant, blinker's own gate 1 36 and 138 to the clock timing signal generator to reset it. 106, sent via 128 and 132 to reset the counter. to This will cause that flasher to synchronize with the sending flasher and all other flashers in the system. The blinkers of the desired simultaneous flash 23 begins to emit light. The curves in FIG. 6 show a series of inhibit pulses. child These negative going pulses are gated by gate 140 during the last half of each flash period. is generated and inhibits gate 138, which causes the flasher to disable for such a period of time. Prevent it from being reset by a sync pulse arriving inside.

The circuit diagram of the clock timing signal generator, designated generally by the numeral 34 in FIG. The operation will be explained with reference to curve F in FIG. timing signal generation The device 34 uses transistors 137 and 139. of transistor 137 The base is fixed to a voltage divider formed by resistor 43 and variable resistor 47. held at the ias voltage. Variable resistor 47 is adjusted to provide the desired bias. be done. Transistor 139 receives start pulse 174 and pulse 17 in FIG. 6 becomes non-conductive during the time between timing pulses, resulting in a high level on lead 35. Generate output.

When transistor 139 conducts, its collector voltage drops and the timing pulse Lead 35 is brought to a low level during the operation. Immediately after the timing pulse, the bidirectional switch One of the channels 52, 58, 44 or 46 is closed by the selected gate circuit and the selected Charging of the capacitor 68 (CI> is started via the resistor set in FIG. 6). Using timing pulse 176 of , switch 52 closes and resistor 64 is is connected to the regulated current of the capacitor 68 to charge the capacitor 68.

When the voltage on capacitor 68 is high enough to overcome the bias at the base of transistor 137, 139, this transistor becomes conductive and connects the base of transistor 139. High level and its collector will be low level as described above. capacitor 6 The charge of 8 is attenuated by diode 149, and diode 147 The output of resistor 64 is connected to prevent recharging of capacitor 68 during the duration of the switching pulse. Works to keep it at a low level. When charge is rapidly removed from capacitor 68, , the collector of transistor 139 is at a low level so that the collector of transistor 139 is at a low level. resistor 137 is canted off and connected to capacitor 68 by switch 52. A capacitor 68 can be recharged via a resistor 68 that has been drained. Curve M in Figure 6 As shown in the figure, the switch 52 is turned on by the 0 count output from the counter 4o. Note that it is held in place and is therefore still conducting.

As mentioned above, the diode 147 is connected to the timing that occurs in the middle of a flash or interruption. Recharging of capacitor 68 is prevented during pulse 176. Andgate 138? The reset pulse sent from the transistor 139 to the base of the transistor 139 9 conducts and generates a timing pulse to start a new timing cycle. It would be obvious to do so.

Bidirectional switches 52, 58, 44 and 48 are each part of a four-part switch 160. are closed by respective AND gates 152, 154, 156 and 158 . During count 2 of counter 4o, a short When a flash is required, the start timing pulse 185 timing amplifiers 101 and 102 to produce a high level signal 186 on Q2. let This high level signal appears at one input of AND gate 156, which 146 (all of its inputs are low level). A high level signal is sent. Therefore, there is a high level signal at the output of AND gate 156. appears and turns on the gate 44 during the time that the 7 is at a high level. stop tie When the timing pulse 187 occurs, the flip-flop 102 is activated. Timing adjustment 5 by step 101 and generates a low level signal at 51 as shown at 189 in FIG. to curve T A short block 18B as shown is then required, which connects one side of the antoget 158. is obtained by the high level signal from Q2 appearing at the input of Q2. and gate 15 The other input of 8 is high due to the output of NOR gate 148. Therefore, Switch 48 closes, connecting resistor 62 and charging capacitor 68.

In this example, since resistors 60 and 62 have the same value, even short flashes will take longer to charge. are the same, therefore transistor 141 will emit light for the same time as flash 184. is controlled to keep the lamp off during shutdown 188. Short control and short cut-off are the same We emphasize that they do not have to be the same time span. For example, resistance 60 is 0.3 seconds resistor 62 forms a short interruption of 0.7 seconds. selected to be completed.

Long flash and long block are controlled by switches 52 and 58, respectively. game The gates 152 and 154 are inverted by the inverting action of the inverter 144 and the NOR gate 150. It remains prohibited during short flashes and interruptions. Like to the place of count 1, When a long flash is required, a count pulse of 190, shown by curve N in Figure 6, is used. to one input of gate 146, producing a low level signal at its output, which The power of one side of the AND gate 152 is set to a high level via the inverter 144.

The other input receives a high level signal from Q2 and turns on switch 52. do. Similarly, a long block is caused by a high level signal appearing at Noah Gate 14.8. , which in this case represents a count of 5 as shown at 191 in curve R of FIG. occurs in The above basic pulse generation/timing circuit applied to the present invention is disclosed in applicant's U.S. Pat. No. 3,596,113, and is incorporated by reference. This is what we will discuss here.

The Noah gate 150 between the Noah gate 148 and the AND gate 154 has a number Used to great advantage in daylight control circuits commonly shown in 70, flashing during daylight hours. At the same time, enough light enters the photoself 2 at night to make the comparator 162 inoperable. When the negative input of is made lower than the positive input, the output becomes high level and no game , and gate 150 to a low level, inhibiting -AND gate 154. However, , the above action is caused by the AND game when Ql and Q2 become high levels at the same time. This occurs only when port 164 is enabled. As is clear from Figure 6, this The condition occurs only during the last half of each interruption. Therefore, if the sequence is long When the second half of the shutdown is reached, the AND gate 154 is disabled and the cap is closed. Passacitor 64 discharges, turning transistor 137 on. Capacitor 68 is recharged I can't get electricity. This is because comparator 162 changes state again. This is because the switch 58 remains open. Therefore, clock timing lead 35 is held at a high level and the flash sequence is stopped. Light incident on photocell 72 However, the voltage decreases enough to change the input voltage of comparator 162 and reduce its output to a low level. Then, AND gate 164. 1 and Q2 are enabled by high levels. This action allows OR gate 150 to charge capacitor 68 when Make it. AND gate 164 performs a flip-flop during the first half of each block. A low level signal appearing on Ql of 101 disables comparator 162. make inoperable. This action causes the filament of the lamp 24 to be removed during dark hours. Do not stop the flasher due to the current flow.

Although the present invention has been described in detail using various specific elements, 27 of the present invention It is clear to those skilled in the art that many changes may be made without departing from the spirit and scope. Dew. For example, the circuit shown here can be implemented in LSI to reduce size and cost. can be done.

Engraving (1 content unchanged) F/63 Mr. Manabu Shiga, Commissioner of the Patent Office 1. Incident indication PCT1038.3100508゜2, title of invention Synchronization and Daylight-controlled flashing device 3, corrector Relationship to the incident: Applicant Mr. Zeidler Robert Elle 4. Agent 5. Date of amendment order: March 19, 1985 6. Subject of correction: Translation of drawings and Document proving authority of representation゛

Claims (1)

[Claims] 1. Forming flashes and interruptions in a preselected sequence from the lamp (24) In the device, Lamp control means (2) connected to the lamp and energizing the lamp during the flash period. 2) and A start timing pulse which is connected to the lamp control means and starts the flash duration. A timing signal that generates a stop timing pulse that ends the flash period and the flash period. signal generating means (34) and the timing signal generating means, Flash to control the time between the timing pulse and the stop timing pulse above a time control means having a short flash control input and a long flash control input; flash duration control means (42, 44, 50, 52), connected to the timing signal generating means, the stop timing pulse and the above timing signal generating means; A cutoff time control means for controlling the time between the start timing pulse and the start timing pulse, Shutdown time control means having short shutoff control inputs and long shutoff control inputs. steps (46, 48, 54, 58); counter means (4o) having a set of sequential count outputs; The number of count outputs is equal to the number of flashes in the preselected sequence above. each of the above count outputs is selected to be connected to the selected input and in the preselected sequence above. to create preselected flash and block durations for each location. The recording flash time and the cutoff time are controlled, and the counter means controls the timing arrangement. input is connected to the timing signal generation means, and each of the start terminals is connected to the timing signal generating means. A start timing pulse that receives a timing pulse and takes its timing. The width is equal to the time between the start timing pulse and the next timing pulse. A device characterized in that each count output is provided with a signal. 2. Connected to the lamp control means and having a synchronous output/input terminal (37) It further comprises synchronization pulse generation means (36), which synchronization pulse generation means A first short synchronization pulse is generated at the above output terminal at the beginning of each flash period during the flash period. 2. A device according to claim 1, wherein the device is controlled to: 3. The synchronization pulse generating means generates the synchronization pulse only during the zero count of the counter. 3. Apparatus according to claim 2, for generating a second short synchronous pulse in the force. 4. The lamp control means receives a first synchronization signal from the outside received at the synchronization output-input terminal. 3. The apparatus of claim 2, wherein said lamp is energized in response to a periodic pulse. 5. The above-mentioned counter means is configured to detect external signals received at the above-mentioned synchronous output/input terminal during flashing. Claim 4 characterized in that the O count is responsive to a second synchronization pulse. equipment. 6. The flash time control means and the cutoff time control means are connected to the lamp control means. connected and actuable by said lamp control means when a short flash is required. a set of short flash gates (42); connected to said lamp control means, said lamp control means being connected to said lamp control means when a short interruption is required; a set of short cut-off gates (46) enabled by steps; connected to said lamp control means and said counter means, where a long flash is required; In particular, the lamp control means and the counter means 30 a set of long flash gates (50) activated by the run uncontrolled means and said counter means when said lamp is connected to said lamp when a long cut-off is required. the control means and the counter means; the short flash gate; the short cut-off gate; It has a switch connected to the long flash gate and the long cutoff gate, respectively. a set of electronic switch means (44, 48, 52, 58) to A series resistor (60, 62) with a capacitance (68) connected to the switch means , 64, 66) and a capacitance timing circuit, the resistors each having a capacitance timing circuit. A separate resistor connected to the electronic switch membrane that activates one of the gates. When enabled, one electronic switch associated with it closes the closed One of the above resistors combined with the gate is connected in series with the above capacitance. , the device according to claim 1, which establishes the selected long time span or short time span. Place. 7. In response to ambient incident light, when this incident light is greater than a preselected level. daylight control means (70, 72) for disabling the timing signal generating means; In general, this daylight control means ensures that the incident light is below the preselected level. Claims wherein said counter means is actuable in response to this incident light when falling. Apparatus according to paragraph 6. 8. The daylight control means includes a photocell means (72) for receiving ambient incident light; connected to said photocell means, and the output from said photocell means is established in advance; and a comparison means (162) for comparing the Apparatus according to paragraph 7. 9. The daylight control means prohibits the operation of the comparison means while the lamp is darkened. gate means (164) connected to the timing signal generating means so as to Apparatus according to claim 7. 10. A plurality of spaced flashers are interconnected by a communication link (39). In systems that flash beacons such as buoys, the beacons have an identification code. A pre-selected sequence of flashes and interruptions representing the The lights will flash in synchronization, and the system will lamp means (24) provided on each said flasher; A flash and cut-off time generator that is installed in the lamp and generates a set of lamp control pulses. means (22), said set defining a preselected sequence and said pulses; energizes said lamp means during the flash period of the Koki group, and further energizes said lamp means at the beginning of each flash period. comprising a synchronization pulse generating means (37) for generating a synchronization pulse for each of the flashers; It is connected to the synchronizing pulse generating means, and the synchronizing pulse is transmitted from each blinker. comprising output means (37) for transmitting each other to all other flashers; and Furthermore, each flasher is provided with a synchronization pulse that is synchronized from another flasher. a set of the flash and σ cutoff time forming means when received by the blinker; A system characterized in that it comprises synchronizing means (40) for starting helicent. 11. The synchronization pulse generating means generates a first synchronization pulse at the start of each flash; After this first sync pulse, a second sync pulse is emitted only during the first flash of the set. claim 10, wherein the synchronization means is responsive only to the second synchronization pulse. The system described in Section. 12. Generates a sequence inhibit control signal in response to daylight incidence2. further comprising a light sensing means (72), wherein the flash and cut-off time forming means are controlled by the control Stop generating the lamp control pulse in response to the signal3. Flash and cutoff time type above means that when the synchronization pulse is not received from any other flasher in the system. 13. The system of claim 12, wherein the system is responsive to said control signal. 14. The light sensing means generates the lamp control pulse when no daylight is incident. control means (1/0) for controlling the screen while the lamp is dark; The claimed invention is equipped with an inhibiting means (164) for preventing generation of an inhibit control signal. The system according to scope item 12. 15. Each of the flashers operates independently of the other flashers in the system. and thereby the flasher is not affected by the failure of said communication link. The system according to paragraph 11. 16. Forming a preselected sequence of flashes and interruptions from the lamp (24) In the device, Lamp control means (2) connected to the lamp and energizing the lamp during the flash period. 2),A, A start timing pulse which is connected to the lamp control means and starts the flash duration. A timing signal that generates a stop timing pulse that ends the flash period and the flash period. signal generating means (34) and the timing signal generating means, Flash to control the time between the timing pulse and the stop timing pulse above and a time control means (42, 44, 50, 52), this flash time control means: a set of short flash gates (42) connected to said lamp control means; These gates can be activated by the lamp control means when a short flash is required. These short flash gates have short flash control inputs and also The light time control means comprises a set of long flash games connected to said lamp control means. 50), these gates are connected to the lamp control hand when a long flash is required. Enabled by the steps, these long flash gates are connected to the long flash control input. further connected to the timing signal generating means, and further connected to the stop terminal. When shutting off to control the time between the timing pulse and the above start timing pulse The cut-off time control means (°46.48.54.58) a short cut-off gate (46) of the IMi connected to the lamp control means; The gate can be activated by the above ramp control means when a short interruption is required. and these short-block gates have short-block control inputs, and The cut-off time control means comprises a set of long cut-off gates ( 54), these gates can be used to control the above-mentioned lamps when long interruptions are required. These long cut-off gates are actuated by a long cut-off control input. have power, It further comprises counter means (40) having a set of sequential count outputs, The number of count outputs is equal to the number of flashes in the preselected sequence. Each of the above count outputs is selected to be the above flash and shut off gate control. connected to the selected one of the inputs and in the preselected sequence above. to create preselected flash and block durations for each location. The recording flash time and the cut-off time are controlled, and the counter means controls the timing control. input is connected to the timing signal generating means, and the start timing is receiving each of the timing pulses and timing the start timing pulse and its timing pulse. Next 34 Count the width equal to the time between the start timing pulse and the timing pulse. Depending on the output, Furthermore, the above-mentioned short flash gate, the above-mentioned short cut-off gate, the above-mentioned long flash gate, and and a set of electronic switches each having a switch connected to the output of the gate of said long cutoff. switch means (44, 48, 52, 58), and Furthermore, a capacitance (6 days) is connected to all the above electronic switch means in series. A resistor-capacitance timing circuit is provided, the resistor being connected to each of the electronic switches. individual resistors (60, 62, 64, 66) connected to the switch means; Enabling one of the gates closes one of the electronic switches associated with it. Similarly, this causes one of the resistors associated with the closed gate to be connected to the gate. connected in series with a capacitance to establish a selected long or short time span. A device characterized by: 17. A block in which a plurality of spaced blinkers are interconnected by a communication link (39). In a system that flashes beacons such as A, each beacon has an identification code. A pre-selected sequence of flashes and interruptions representing the The above system is lamp means (24) provided in each of the flashers; and lamp means (24) provided in each of the flashers; one set of lamp control pulses for each sequence of flashes and breaks. and a means (22) for forming a flash and a cut-off time such that the above-mentioned set is selected in advance. defining a sequence in which said pulses are applied to said lamp means during said set of flash times; energize, Additionally, a first synchronization pulse is generated at the beginning of each flash; following the second synchronization pulse, which occurs only during the first pulse of the set. Equipped with una synchronization/<7 response generation means (37), Further, each of the flashers is connected to this synchronized pulse generating means) and and an output means for transmitting the above synchronized)<Jbs to all other blinkers, and Furthermore, each of the above-mentioned flashers is provided, and from the flasher of the synchronized Norei Ruska I51 When received by an out-of-sync flasher, the self-flash and cut-off time forming hand synchronization means (40) for nocenting a row to the start of a set; , a system responsive only to the second synchronization noggle.