NO753151L - - Google Patents

Abstract

DIGITAL CODES / DECODERS

Description

The present invention relates to digital pulse communication systems and more specifically to a device for signal conversion between one and the other in a digital bit stream and an amplitude variant analog signal, such as speech. Such a device can be referred to as an analog/digital (A/D) or digital/analog (D/A) converter. A more general term that includes A/D and D/A converters is the term codec.

. In general, analogue to digital conversion falls under this

two important classes, namely:

(i) pulse code modulation (PCM) where the analog signal is amplitude sampled at a frequency fs, where the sample is coded into an n-bit binary word, and where data at rate n.fs is generated, and (ii) delta modulation (DM) where the analog signal is approximated by means of a series of positive or negative slopes which are combined to form a reconstruction signal, and where each bit of data transmitted is the polarity of the reconstruction slope at any instant.

In telephone networks, the standard for PCM is the CCITT system, where the input signal is sampled at a frequency of 8 kHz, and where an 8-bit word is generated according to the A-law companding. Such a standard ensures good voice transmission performance, but PCM codecs are generally more complicated and therefore more expensive than delta codecs.

Published literature shows several delta modulation systems

which use companding, and such systems are capable of good speech transmission performance, but the performance for objective trans-J Immission parameters, e.g. gain linearity by difference1i<g>e

input levels, and the level of intermodulation distortion products is below the standard expected of high quality analog to digital conversion for telephony use as specified in e.g. above CCITT standard.

The literature also indicates that for optimal speech performance bor

the speed of companding be syllabic. Syllable companding tends to adjust the reconstruction step size to the average steepness of the input signal averaged over the syllabic decay time constant. A typical system of this kind is given in fig.

5 and is equivalent to a system developed by Phillips and

described in an article by K. T. Hanser and S. J. Zarda,

"The design of digitally delta modulation codecs" Proe. IREE,-July, 1971, pages 286 - 295. In fig. 5, the compand logic 27 detects the steepness overload, i.e. the occurrence of four "ones" or four "zeros" in the shift register 24, and upon occurrence, the current pulse unit 28 supplies a current of magnitude +Ia to the compand control capacitor Cc, and thus the reconstruction step size is increased. If four "ones" or four "zeros" do not occur, Vc (the voltage across Cc) will drop across the resistor Rc. The rate of rise and fall in this system is such that the companding is approximately syllabic.

The previously known system shown in fig. 5, will only give an acceptable level of intermodulation distortion over a limited range of input levels and only at the lower input frequencies, as will appear below with reference to fig. 6 (a) and 6 (b). The gain linearity with input level is only acceptable at high input levels, as mentioned below and shown in fig. 7. The speech transmission quality of this typical, previously known system which is shown in fig. 5, is reasonable with some distortion of transient speech sounds, i.e. sounds like "ta".

As mentioned above, syllabic companding tends to adjust the reconstruction step size to the average steepness of the input signal averaged l'o... over the syllabic decay time constant. Thus, the compand control (reconstruction step size) simply cannot follow non-instantaneous regions of the input signal with large steepness. The operation of this type of companding is shown with the reference number 65 in fig. 8. The f^+ f2~sine type of the input signal 64 has non-instantaneous regions (a) with a large steepness and non-instantaneous regions (b) with a small steepness.

The signal actually has regions of zero steepness at (C), so the application of "instantaneous" large or small steepness is not entirely correct. Instantaneously refers to the steepness at zero crossing.

Syllable companding will adjust to the average step size over several cycles, i.e. an integration time much larger than ^—^ + , and therefore the reconstruction '•12 step size set will be less than optimal to follow the region of the signal that has high steepness, and severe steepness overload occurs as the companding equalizes the regions of the signal that have high and low steepness. In order for a delta modulation system to thus have a low level of intermodulation distortion, the compander must set the reconstruction steepness according to the average of the peak steepnesses or the large steepnesses, hereinafter referred to as "average peak steepness". Thus, the reconstruction step size will increase in region (a) and decrease in region (b) for the signal, i.e. adapt to follow the peak steepness. It has been established from experimental results that the important requirement for low intermodulation distortion is that the reconstruction follows in region (a), because steepness overload is produced by the intermodulation products. A small degree of overfolding in region (b), fig. 8, (caused by a reconstruction signal above optimum) will tend to produce grain noise (approximately white in the speech frequency range), but such noise is acceptable because it does not adversely affect the speech transmission performance or the objective transmission parameters as stated above. Thus, it is not as important to let the step size in region (b) decrease as it is to increase the step size in region (a).

There are earlier delta systems that have true, non-instantaneous

! in

in

companding, i.e. the companding is set off immediately

ice steepness and not average peak steepness as in the present invention. Thus, the step size in such a system will decrease in region (c) in fig. 8, which enables more accurate tracking in the region of high-level signals, but such systems suffer from the disadvantage of poor tracking every time a

input signal that has an instantaneous, large steepness occurs after an input signal that has an instantaneous, small steepness, i.e. when a signal, such as in region (a) in fig. 8, occurs directly after a signal such as in region (b). This poor tracking produces unacceptable intermodulation distortion characteristics. Another problem with such a system is the wide dynamic range required for the step size to follow the instantaneous companding law of

any time, i.e. typically requires a 20 dB larger area than a syllabic type according to the present invention.

The purpose of the present invention is to provide an improved delta modulation codec which is able to provide a good voice transmission performance, and which provides improved, objective transmission parameters compared to previously known syllabic and non-instantaneous, companded delta modulation systems as discussed above.

In order to realize the above-mentioned purpose, the present invention provides companding which tends to adjust the step size to average steepness over a short time (eg - z—f where f, and f9 are the two different frequencies

rl ~ r21 z

which is shown in fig. 8), and not to the immediate steepness of any definition. For input signals such as speech with a peak level to average level ratio of 12 - 15 dB, this type of average peak slope companding will allow more accurate coding of speech sounds with a high transition factor, i.e. sounds like ta, pa, etc. as indicated below with reference to fig. 9, and as shown with the reference number 66 in fig. 8.

Throughout this description, the term "average peak slope companding" is used to mean that the companding adjusts to the average of the regions of the input signal i . in

with great steepness as opposed to syllabic or obvious companding.

"Average peak steepness companding" according to the present invention cannot be achieved by simply increasing the rise and fall rates of typical syllabic companded

delta modulation systems or by reducing the rise rates of typical non-instantaneous companded delta modulation systems.

First, a defined nonlinearity must exist within the encode/decode compand loop to ensure that the "average peak steepness compand" occurs and is established over a large range of analog output levels. The defined non-linearity establishes a relationship between the rise and fall time and the input signal level and thus ensures an "average peak steepness companding" over a wide dynamic range. For special types of input signals (not necessarily speech frequency), an appropriate non-linearity can be chosen to provide optimal compand control.

A known system using a non-linearity in the compound loop is disclosed in US Patent 3,699,566 by Schindler and assigned to IBM Corporation. Further reference to the Schindler system can be found in an article entitled "Delta Modulation" by H. R. Schindler, published in IEEE Spectrum October 1970, page 76. However, the companding step size in Schindler's system indicates that companding approaches instantaneous companding due to the large rise- and the fall rates, 2 dB and 0.2 dB respectively per sampling interval. Therefore will. this system is expected to suffer from the inherent problem of unacceptable intermodulation distortion as noted above.

Without the nonlinearity in the compound control loop, the rise and fall times will increase proportionally to the input signal level. Thus, the control will be optimal with only one input level. The syllabic system discussed earlier has this characteristic. For signal levels above this optimum level, the rise and fall times would be too long, so that serious steepness overloads would occur. For signals below this optimum, the rise/fall times are too short, and unstable coding will occur. Thus is the nonlinearity that is chosen in it

IN

present invention, preferably logarithmic so that j the rise and fall rates are independent of the signal level.

. In order for the invention to be easier to understand, a particular embodiment will now be described in detail with reference to the attached drawings. • ■ Fig. 1 is a block diagram of a delta coder according to the embodiment for converting an analogue signal into a digital bit stream. Fig. 2 is a block diagram of a delta coder according to the embodiment for converting the digital bitstream into an analog signal. Fig. 3 is a circuit diagram of an anti-logarithmic converter and a current pulse amplitude modulator according to the embodiment in fig. 1 and 2. Fig. 4 is a circuit diagram of a compand drum pulse unit in the embodiment in fig. 1 and 2._

Fig. 5 is a typical previously known delta coder.

Fig. 6 (a) and 6 (b) show diagrams of intermodulation distortion against the input signal level for the previously known encoder according to fig. 5, and fig. 6 (b) includes a curve representing a level of 500 Hz and 1000 Hz components of delta modulation with average steepness companding according to

the present invention.

Fig. 7 shows a diagram of gain linearity against the input level in a typical previously known encoder as shown in fig. 5. Fig. 8 shows a diagram comparing syllabic companding with average steepness companding according to the present invention. Fig. 9 is a further diagram showing the reconstruction step size for syllabic companding and average steepness companding according to the present invention.

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j

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Throughout the drawings, like reference numerals indicate like or

In corresponding parts.

From fig. 1, it will be seen that the encoder in this embodiment includes a comparator 20 which has two inputs 21 and 22 respectively.. An analogue input signal at the input 21 is compared with a

feedback on input 22, and the comparator provides an output in the form of a high or a digital "one" when the analog signal exceeds the feedback signal and a low or digital "zero" when the feedback signal exceeds the analog signal. The comparator is clocked at a frequency of 64 kHz and its output 23 feeds a digital bit stream of "ones" and "zeros" depending on the values of the analog input and the feedback signal relative to each other.

; The output 23 of the comparator 20 is connected to the input of a four-bit shift register 24. The output 25 of the shift register feeds a digital bit stream which is sent to line. As the data on output 25 is the same as the data on input 23 except that it is delayed by four clock periods, it is conceivable that the line connection can be made at input 23

for the shift register 24. The clock signal with the frequency 64 kHz for the device is provided on connection 26 to the shift register 24.

The shift register 24 has each stage connected to a compand logic unit 27. The compand logic unit 27 comprises a number of gates and detects the appearance of four "ones" or four "zeros" in the shift register 24. The output of the compand logic unit 27 is connected to a current pulse unit 28. During the period when the compand logic unit 27 detects four "ones" or "zeros" in the shift register, it pulses the current pulse unit 28 to activate the current pulse unit to provide, at its output 29, a constant current of positive polarity during the time it is activated. During the period when the compand logic unit 27 does not detect four "ones" or four "zeros" in the shift register 24, the current pulse unit provides, at its output 29, a constant current with negative polarity.

j Choice of rise and fall rates determines the type of compande-j

ring. By choosing both the rise and fall times long, it is said

! the companding to be syllabic, i.e. the companding equalizes the steepness and sets the step size according to the average steepness for a spoken syllable. If both the rise and fall times are short, the companding is said to be non-instantaneous, dys. the companding varies the companding step size pro-'

proportional to the relevant instantaneous steepness in the input signal. It has been found that, if the rise times are short and the fall times long, the companding will occur so that the step size is set to the average steepness.

An extensive experiment has been carried out during the development of the invention to find the optimal rise and fall speeds. The experiment took into account the subjective speech performance and objective performance (such as intermodulation distortion). "The optimum rate of rise was found to be 0.7 dB per clock pulse, and the rise to fall ratio was 100:1. The optimum is quite broad, and reasonable performance is achieved well beyond this choice of companding parameters. The rate of rise can be reduced to eg 0.25 dB per clock pulse and okes to 3 dB per clock pulse and the rise/fall ratio can be varied from 30:1 to about 500:1 with some degradation in performance It is interesting to note that, as the rate of rise has to be reduced, i.e. the companding tends towards syllabic, the performance deteriorates., and as the rise/f all ratio decreases, i.e. when the companding tends towards instantaneous, the performance will again deteriorate and thus indicates the improvement in performance with average steepness companding in contrast to prior art.

As mentioned above, the range of rise rate and rise in relation to the fall ratio, where the average steepness companding is defined, is as follows: the rise rate in the range 0.25 dB per clock pulse to 3 dB per clock pulse and rise/fall ratio in the range of 30:1 to approx. 500:1. The system will give good performance over this range, and even somewhat outside the range,

but the optimum lies within the range. The actual selection of the optimum depends on the signals for which the system is designed. If the system is for speech only, the optimum will be j different than if the system is for transmission of a sinusoid^,

IN

but will still be within the above-mentioned area. The

jooptimal (rise rate 0.7 dB per clock pulse and 100:1) is the optimum for a system designed to pass speech as well as sinusoidal signals when the clock rate is 64 kHz and the detected sequence is four bits long. If other clock speeds and sequence lengths in the same

order of magnitude is used, the optimum will still lie in the range, but for these other systems there may be certain small parts of the range where the system does not give acceptable results.

In this embodiment, positive current from the current pulse unit 28 causes the rise current to cause the reconstruction or feedback signal to increase in value towards the analog signal, and the negative current from the unit 28 provides the fall current which reduces the magnitude of the change in the feedback signal when this has exceeded it analog signal, as will be explained in what follows. The positive current from the current pulse unit 28 is on the order of 100 times the negative current in this embodiment, but can be trimmed to change the ratio. During the period when the constant current device is activated, the positive output current therefrom charges a compand integrator capacitor 30 to effect a linear build-up of voltage across the capacitor. The value of the capacitor 30 and the positive polarity current is chosen so that during one clock period (15.6 y,s) the voltage build-up across the capacitor is approx. 100 mV each time four "ones" or four "zeros" occur. As explained above, the value of the current can be trimmed, and thus the rate of voltage generation can be changed. During a clock period when the constant current device 28 supplies negative polarity current to the capacitor 30, the capacitor is discharged, and the voltage drop across the capacitor 30 is approx. 1 mV.

The voltage across the capacitor 30 is fed to an antilogarithmic converter 31. The antilogarithmic converter 31 is arranged so that its output 32 is an antilogarithmic current function of the input voltage as shown in equation (3) below. Therefore, for low voltages across the capacitor 30, a change in voltage will cause the output current from the anti-log converter 31 to change to a lesser extent, while for higher voltages across the capacitor, the same voltage change will produce a much larger current change. It will be clear that, when the frequency of four "ones" or "zeros" in the shift register 24 is high, the voltage on the capacitor 30 is high, i.e. the compand voltage is high.

The action of the antilogarithmic converter in the companding feedback loop makes the rate of rise independent of the signal input level. The rise time for a signal to rise from -40 dB to -30 dB is the same as for rising from -10 dB to 0 dB, where the 0 dB point is some random reference. Thus, the rate of rise is expressed as dB per time interval. A system that has a rate of rise (expressed in dB/time interval) constant with input level must have some anti-logarithmic element in the compound feedback circuit. The rise/fall" ratio varies somewhat with the input level due to the time constant formed by the capacitor 30 and the resistor 38 plus the resistor 40. For a ratio between rise and fall current of 100:1, the rise/fall ratio of the reconstruction signal will be e.g. eg 70:1 for high input levels and 130:1 for low input levels.

The output 32 from the antilogarithmic converter is connected

to a current pulse amplitude modulator 33. The modulator 33 supplies an output current which is proportional to the voltage signal from the antilogarithmic converter 31. The current from the modulator 33 is fed to an integration network 34 which converts the current signal into a voltage signal to be fed back to the comparator 20 on the connection 22. The voltage on the connection 22 is the reconstruction or feedback voltage that follows the analog input signal. As previously explained, the output from the comparator 20 depends on whether the analog signal is greater or less than the feedback signal. In addition to the signal from the antilogarithmic converter 31, the modulator 33 receives a digital signal via connection 35 from the first stage of the shift register 24. The digital signal to the modulator 33 is a polarity connection which establishes the polarity of the step change in the feedback signal to the comparator. If e.g. a "zero" appears on compound 35 directly after a "one" has

1

occurred, the polarity of the step change in the feedback signal is reversed, as the feedback signal has exceeded the analog input signal. For a "flat" analog input to the comparator, the bit stream of the shift register 24 will comprise alternate "ones" and "zeros" and the polarity of the step change will be reversed for each successive clock period.

The decoder according to this embodiment is shown in fig. 2, and is essentially the same as the decoder described above except that the comparator 20 is eliminated and a filter 36 is included. The transmitted digital bit stream enters the shift register 24 at the input 25, and each bit is successively clocked into the shift register. The remaining part of the device is identical with the encoder down to the integration network 34. The voltage signal out of the integration network

34 in the decoder is the same as the feedback signal on

connection 22 in the encoder and is therefore a signal that approximates the original analog input signal. The filter 36 serves to equalize the signal from the integration network 34 to give a signal at its output 37 which fairly closely approximates the original, analogue signal. Reference should now be made to fig. 3, which is a combined circuit diagram of the antilogarithmic converter 31 and the current pulse amplitude modulator 33. The voltage across the capacitor 30, hereinafter referred to as V , is applied to the antilogarithmic converter 31 at the connection 29, and is applied via the resistor 38 to the base of the transistor 39. The base of the transistor 39 is connected via a resistor 40 to the base of a further transistor 41.

The two resistors 38 and 40 form a voltage divider network. The transistor 39 is supplied with a constant collector current Ia by means of a feedback network including an operational amplifier 42 and a resistor 43. The current Ia is obtained from a positive power supply voltage 44, which in this case is +5V, and is dependent on the value of a series resistance 45 ( Ia equal to -—5).The base of the transistor 41 is connected to a negative power supply voltage 46, which in this case is -5V.

The operation of the antilogarithmic converter is based on the collector current (Ic) -base emitter voltage (VgE) characteristic

IN

in the forward-biased mode for a transistor as shown at

In the following equation (1):

where

q = the electron charge (Coulombs)

K = Boltzman's constant

T = absolute temperature (<*>K)

I = constant for the transistor,

o

The equation illustrates the logarithmic gear ratio. The emitter voltage on transistor 41 is controlled by the emitter on transistor 39, which emitter has low impedance and is temperature compensated, i.e. the emitter voltages for the two transistors are controlled by V"c in the ratio

where

R^q is the ohmic value of the resistor 40,.

R^g is the ohmic value of the resistor 38, and

VBBs the base-to-base voltage difference between the two transistors.

As I for the transistor 41 is shown as IR from the current pulse amplitude modulator 33, so will

The current I_ is switched in polarity by the current pulse amplitude modulator 33. If the voltage on the polarity connection 35 of the modulator 33 is greater than a reference voltage 47 at the base of a transistor 48, a further transistor 49 will be switched on, and a current IJ.a, . flows from the integration network 34 (Figs. 1 and 2) into the collector of the transistor 49. If the voltage on the polarity connection 35 is less than the reference voltage 47, the transistor 49 will be OFF and the transistor 48 will be ON. Thus, IR flows from the adapted transistors 50 and 51 connected as a current mirror, and a current IR flows from the collector I of the transistor 51 into the integration network 32 on the

IN

bond 52.

Reference should now be made to fig. 4, which shows the circuit diagram of the compound drum pulse unit 28. This unit is equivalent to the modulator 33 and consists essentially of four transistors 53, 54, 55 and 56 connected together as shown. Reference number 62

represents 'a constant current source Ia. The connection 57 goes to the antilogarithmic converter 31 and the capacitor 30,

while the connection 58 is the connection from the compand logic unit 27 and is applied to the base of a transistor 54 via a resistor

59. If the voltage on connection 58 (in the following

called compand control) is greater than the reference voltage 47, the transistor 54 will be ON, and a current Ia flows from the capacitor 30 into the collector of the transistor 54. If

the voltage on the compand controller is less than the reference voltage 47, the transistor 53 is ON and the transistor 54 is OFF.

The voltage across the resistor 60, designated VR, is equal to the product I R, where R is the ohmic value of the resistor 60. A further resistor 61, which is connected to the emitter of the transistor 56, has a value dR, where d is chosen in this case to be equal to 100. The voltage across dR is approximately equal to IaR, and therefore a current of approx. — ' from the collector of transistor 56 into capacitor 30. By adjusting the value of resistor 61, i.e. by changing d, the ratio between the rise step size and the fall step size can be varied, and any ratio within the limits indicated above will give acceptable results even if a ratio of 100:1 with a rate of rise of 0.7 dB per clock pulse provides optimal performance.

The operation of the A/D converter in FIG. 1 can be understood by considering a sinusoidal input to the comparator 20. First, as the sine wave rises, there is no feedback signal, and the first bit from the comparator is a digital "one". The "one" is sent to the shift register 24 and is controlled into the first slot. The digital "ones" in the first slot are sent to the modulator 33 by means of the polarity connection 35. The modulator 33 causes a signal to be fed back

to the comparator 20, and the step size for this feedback signal is very small and depends on the value of the background signal entering the system prior to the sinusoidal input

IN

feeding. During the next clock pulse period, the feedback I voltage is still far below the analog signal, and thus an additional "one" is sent to the shift register, and the original "one" is shifted into the next slot.

The polarity connection 35 outputs the modulator 33 in the same way as before, and a further feedback signal with the same step size as before is added to the previous signal and fed back to the comparator. The operation continues in this manner and the feedback signal increases approximately linearly until four "ones" appear in the shift register 24. Upon detection of four "ones" the logic unit 27 pulses the current pulse unit to cause a constant current to be fed into the capacitor 30 so that to increase the step size

of the signal that is added to the feedback signal. The feedback signal is thus caused to "attack" the analogue with a greater speed than before. However, the signal through the antilogarithmic converter 31 is still at a low level, and therefore the output of the antilogarithmic converter is lower than its input. The feedback signal is still less than the analog signal, and during the next clock period a further "one" is sent from the comparator 20

to the shift register 24. The logic circuit again detects four "ones" in the shift register and pulses constant current to the device to further increase the step size of the signal that is added to the feedback signal. The process continues as each additional "one" enters the shift register 24. However, the input signal to the antilogarithmic converter 31 quickly reaches a value such that the output from it exceeds the input. The rate at which the feedback signal "attacks" the analog signal increases rapidly, and the feedback signal soon exceeds the analog signal. At the first clock pulse after the feedback signal has exceeded the analog signal, the comparator 20 outputs a "zero" into the shift register 24. The logic unit 27 does not detect four consecutive, equal bits, and therefore there is no output to the current pulse unit 28. The current pulse unit 28 therefore supplies a negative polarity current which begins the discharge of the capacitor 30 and reduces the voltage V of the antilogarithmic converter 31. Also

IN

is the polarity connection 35 now a "zero" so that the step change

ji the feedback signal is subtracted from the previous value. The value of the step is less than for the previous clock period due to the smaller charge on the capacitor 30.

The feedback signal will continue to overshoot the analog signal in opposite directions, but each time to a reduced degree until the minimum step size is reached and overshoot is at a minimum.

As indicated above, Fig. 5 a typical previously known delta encoder. In the figure, the output from the pulse amplitude modulator 33 is a current i , and the current i r (= signal PX constant Vc)

is fed to the integrator network 34. The output from the integrator network 34 provides a signal on the connection 22 for comparison with the analog input signal by means of the comparator 20. The output from the comparator 20 is a digital bit stream for the connection 23. The remaining parts of the encoder in fig. . 5 has been discussed in the introduction above. Most parts of the encoders in fig. 5 correspond to the parts in the encoder according to the present invention, and thus corresponding reference numbers have been used.

In the diagrams in fig. 6 (a) and 6 (b), axis 16 represents the input level (dB), and axis 15 represents the level of intermodulation distortion (IMD) measured in (dB). Fig. 6 (a) shows typical levels of 800 Hz products 17 and 1600 Hz products 18 for a coder as shown in fig. 5 for an input signal combining the frequencies 400 Hz and 1200 Hz. In a similar way, fig. 6 (b) typical levels for 500 Hz products 67 and 1000 Hz products 68 for an encoder as shown in FIG. 5 for an input signal combining frequencies of 1500 Hz and 2000 Hz. Also shown in fig. 6 (b) is a curve 69 of the typical level of the 500 Hz and 1000 Hz components of delta modulation using average steepness companding in accordance with the present invention.

Fig. 7 shows a typical decrease in linearity for the gain at low input levels with previously known devices such as that shown in fig. 5. Axis 13 indicates the output level in dB, and

jack 14 represents the input level in (dB).

Fig. 8 shows the operation of both average steepness-syllabic companding used according to the present invention and syllable-wise companding in the previous

known technique for an analog input signal if quadratic

•—mean value voltage (RMS) is constant, but has larger variations in steepness over a single cycle. The syllabic companding, as shown by reference numeral 65, adjusts the step size approximately proportional to the average steepness over the syllabic time constant, and thus the step size is not of sufficient value to follow the high-steepness regions of the low-distortion signal. A sys-

tem with average peak steepness companding as in the above-mentioned embodiment, can change the step size within the signal period and can therefore adjust the step size to follow the instantaneous high regions with minimal distortion.

Fig. 9 shows the reconstruction step size for average steepness companding according to the present invention compared to previously known syllable-wise companding. In the diagram in fig. 9, line 10 indicates the envelope of the input signal, line 11 indicates the reconstruction step size for average steepness companding, and line 12 indicates the reconstruction step size for syllabic companding.

It will be understood from the above that the present invention provides a significant improvement over previously known devices. By setting the compand parameters so that the companding controls the reconstruction step size to mean peak steepness, the overall performance exceeds that of delta modulation systems with syllabic or instantaneous companding.

According to a modification of the above-mentioned embodiment, the companding can be arranged to detect more or fewer than four data bits by changing the number of bits in the shift register 24 and thus the companding logic unit 27. The anti-logarithmic converter must also comprise a resistive device which is in

It is possible to produce a number of binary functions with different steepnesses, which approximate the continuous anti-logarithmic function in the above-mentioned embodiment, but such a modification would unnecessarily complicate the device. Naturally, voltage levels and frequencies can also be varied to suit particular applications of the device. The embodiment described above finds particular application in a digital PABX telephone system.

Claims (11)

1. Companded delta codec for A/D or D/A conversion, characterized in that the analogue signal is approximated by means of a reconstruction signal comprising a series of different positive and negative steepnesses, wherein said codec has detection means for detecting the presence of special sequences of bits in the digital bit stream by said codec, and means which are sensitive to said detection means for providing a companion signal which is dependent on the presence or absence of said special sequences of bits, where said compand signal modulates said reconstruction signal in the manner that provides average steepness companding as indicated above. 2. Companded delta codec for A/D or D/A conversion, characterized in that the analogue signal is approximated by means of a reconstruction signal comprising a series of different positive and negative slopes, wherein said codec has a compand loyfe including detection means for detecting the presence of particular sequences of bits in the digital bit stream by said codec, and means, sensitive to said detection means, for providing a compand signal, which means includes signal generating means for generating a signal that increases in the presence of said special sequences, and decreases in the absence of said special sequences, and a converter for receiving said signal and providing an output signal which is largely an anti-logarithmic function of the received signal, where, the ratio between the rise in said signal and the drop in said {signal is in the range of 30:1 to 500:1, wherein said output signal is said compand signal that modulates said reconstruction signal, which causes the reconstruction signal to change value against the value of the analog signal during each bit period, where the rate of rise of said compand signal is in the range of 0.25 dB per bit period to 3.0 dB per bit period. 3. Codec as stated in claim 2, characterized in that said signal generating means comprise a current pulse unit which provides a current to increase the voltage on a capacitor upon detection of said special sequences and a current to decrease the voltage on said capacitor in the absence of said detection, where the ratio between the current to increase the voltage and the current to decrease the voltage is in the aforementioned range of 30:1 to 500:1. 4. Codec as stated in claim 2, characterized in that the special sequences of bits are four "ones" or four "zeros", and that said codec is operated from a clock signal with a frequency of the order of 64 kHz. 5. Companded delta codec for A/D or D/A conversion, characterized in that the analogue signal is approximated by means of a reconstruction signal comprising a series of different positive and negative steepnesses, wherein said codec has a compand loyfe which includes detection means for detecting the presence of particular sequences of bits in the digital bit stream of said codec, and means which are sensitive to said detection means for providing a compand signal, which means includes signal generating means for generating a signal which increases by the presence of said special sequences and decreases by the absence of said special sequences, and a converter to receive said signal and provide an output signal which is generally an anti-logarithmic function of the received signal, where the ratio between the rise in said signal and the fall in said signal is in the range 50:1 to 200:1, where said output signal is said compand signal which modulates said reconstruction signal, which causes the reconstruction signal to change in value against the value of said analogue signal during each bit period, where the rate of rise in said compand signal is in the range of 0.5 dB per bit period to 1.5 dB per bit period. 6. Codec as stated in claim 5, characterized in that said signal generating means comprise a current pulse unit which provides a current to increase the voltage on a capacitor upon detection of said special sequences and a current to reduce the voltage on said capacitor in the absence of said detection, where the ratio between the current to increase the voltage and the current to decrease the voltage is in the range 50:1 to 200:1. 7. Codec as stated in claim 5, characterized in that the special sequences of bits are four "ones" or four "zeros", and that said codec is operated from a clock signal with a frequency in the order of 64 kHz. 8. Companded delta codec for A/D or D/A conversion, characterized in that the analogue signal is approximated by means of a reconstruction signal comprising a series of different positive and negative slopes, wherein said codec has a compandslbyfe which includes detection means for detecting the presence of particular sequences of bits in the digital bit stream by said codec, and means which are sensitive to said detection means for providing a compand signal, which means includes signal generating means for generating a signal which increases in the presence of said special sequences and decreases in the absence of said special sequences, and a converter for receiving said signal and providing an output signal which is largely an anti-logarithmic function of the received signal, where the ratio between the rise in said signal and the fall in said signal is of the order of magnitude 100:1, where said output signal is said compand signal which modulates said reconstruction signal, and which causes the reconstruction signal tL1 to change in value against the value of said analog signal during each bit period, where the rate of rise in said compand signal is of the order of 0 ,7 dB per bit period. in 9. Codec as set forth in claim 8, characterized in that the special sequences of bits are four "ones" or four "zeros", and that said codec is operated from a clock signal with a frequency of the order of 64 kHz. 10. Codec as stated in claim 9, characterized in that said signal generating means comprise a current pulse unit which provides a current to increase the voltage on a capacitor upon detection of said special sequences, and a current to reduce the voltage on said capacitor in the absence of said detection, where the ratio between the current to increase the voltage and the current to decrease the voltage is of the order of 100:1. 11. Companded delta codec for A/D or D/A conversion," characterized in that the analog signal is approximated by means of a reconstruction signal comprising a series of different positive and negative steepnesses, wherein said codec includes in combination: (a) a four-bit shift register for sequentially receiving each data bit in the digital bit stream by said codec and clocking the bits sequentially through this with a clock frequency of approx. 64 kHz, and (b) a logic unit for determining when four "ones" or four "zeros" appear in said shift register during any clock period, and (c) a current pulse unit for supplying a current to charge a capacitor during each clock period when four "ones" or four "zeros" are detected and supplying a current to discharge said capacitor during each clock period when there is no detection, wherein the ratio between said charging current and said discharge current is approx. 100:1, and (d) an anti-logarithmic converter for receiving the voltage signal developed across the capacitor, and providing an output signal which is an anti-logarithmic function of the received signal, the rate of rise in said output signal being approx. 0.7 dB per clock period, and (e) a pulse amplitude modulator for receiving the output signal from said antilogarithmic converter, and a signal from | . said logic unit to distinguish between whether four I I "ones" or four "zeros" appear in the aforementioned shift register, and (f) an integration network for receiving output from said pulse amplitude modulator and providing said reconstruction signal and either (g) a comparator for comparing said reconstruction signal with the analog signal in the case where said - codec is used for A/D conversion, where said comparator is clocked with said clock frequency and provides a digital bit output during each clock period depending on which of said reconstruction signal or analogue signal is the largest, or (h) a filter network to smooth out sudden changes in said reconstruction signal in the case where said codec is used as a D/A converter.