RU1785078C - Byte-companding adaptive delta-modulator - Google Patents

Abstract

The adaptive delta modulator relates to radio engineering and can be used in radio speech transmission devices and in analog signal recording devices with preliminary analog-to-digital conversion. The purpose of the invention is to reduce the coefficient of non-linear distortion and expand the range of transmitted signals. This is achieved by digitally forming a linear law of increasing the approximation speed in the event of an overload of the delta modulator, and the approximation of the approximation of the law of decay of the approximation velocity mation in the absence of an overload apparatus includes a comparator, the adder, the block integration, a shift register, equivalence element, two OR-NO element, a reversible counter, a trigger, and counter yl integrator.1

Description

The invention relates to radio engineering and can be used in radio and telephone lines, as well as in analog-to-digital conversion devices and devices for digital recording of analog signals.

Single and double integration delta modulators are known without adapting tracking speed to signal level.

Inertia-free delta modulators are known in which adaptation to the signal level is effected by switching resistors included in the integrator using reversible shift registers.

Syllabic delta modulators are also known in which the change in signal tracking speed is carried out by analog control of a current generator

Delta modulators without adaptation to the signal level have the best nonlinear distortion coefficient within their dynamic range, however, the width of their dynamic range (20 26 dB at a clock frequency of 32 64 kHz) provides voice transmission only in accordance with class III GOST 16600-72.

Delta modulators with inertialess companding have an extended dynamic range (40 dB or more) and provide signal transmission in accordance with class II GOST 16600-72, however, they have an increased coefficient of non-linear distortion and unsatisfactorily transmit fricative sounds. In addition, if there are extraneous sounds, especially high-frequency speech quality drops to grade IV

The delta module of the syllable complying complies with the HI class GOST 16600-72, providing a wide dyna of 4 00 SL O H

00

the physical range of the transmitted signals, and a relatively small coefficient of nonlinear distortion. This is due to the fact that within the time intervals commensurate with the constants of the rise and fall times of the sound volume level, it operates in a mode close to the linear delta modulator mode; moreover, the tracking speed depends on the speech level within the syllable . However, the construction of a syllabar compander based on analog control imposes stringent requirements on the coordination of the characteristics of the delta modulator and delta demodulator, including when voltage and ambient temperature change.

Thus, a relative change in the supply voltage by 5% leads to an increase in the coefficient of non-linear distortion from 4% to 15-20%. This limits the applicability of such a torus deltamodulator. in equipment with autonomous or unstable power.

The purpose of the invention is the creation of a delta modulator that introduces small nonlinear distortions into the signal, which is uncritical to the accuracy of matching the delta modulator and the demodulator, and provides voice transmission according to class I GOST 16600-72.

The goal is achieved by using digital methods for processing an approximating feedback signal.

The drawing shows the electrical circuit of the delta modulator. The input signal is fed to the first input of adder 1, the output of which is connected to the inverting input of the comparator 2, the non-inverting input of which is connected to the output of the integrator 3, and the output to the information input of the shift register 4, the clock input of which is connected to the fourth output of the clock generator 5, and the first the output, which is the output of the delta modulator, is connected to the input of the integrator 3, the first output of the main resistor 6 of the approximator integration unit and with the analog inputs of electronic keys 7 ° .7P, the analog outputs are connected to the first terminals of the additional resistors 8 ° .., 8P of the integration unit, the second terminals of which are connected to the second terminal of the main resistor 6, the second input of the adder 1 and the first terminal of the capacitor 9 of the integration unit, the outputs of the first four bits of register 4 are connected to the inputs of the equivalence element 10, the output of which is connected to the input of the counting direction of the reverse counter 11 of the integration speed control circuit and the first input of the first logical

an OR-NOT 12 element, the second input of which is connected to the transfer output of the counter 13 with a variable counting coefficient, and the output is connected to the first input of the second OR-NOT 14 logical element, the second input of which is connected to the transfer output of the counter 11 and the counter ban input of the counter 13, and the output is with the information input of the D-trigger 15, the clock input of which is connected to the first

0 by the output of the clock generator 5, the reset input - with the third output of the clock generator 5, and the output - with the input of the asynchronous load of the counter coefficient of the counter 13 and the clock input of the reverse counter 11,

5, the outputs of which are connected to the control inputs of the electronic keys 7 °, .. 7P, the outputs of the higher bits correspond to the corresponding inputs of the counter setting of the counter 13, the clock input of which is connected to the second output of the clock generator 5.

The principle of operation of the adaptive delta modulator is as follows: to increase the speed with the speech signal

5, tracking to the maximum should occur on an approximately linear law in about 3 ms, and a decrease to the minimum should be approximately exponentially with a time constant of 3 .10

0 ms This algorithm is implemented in the invention digitally.

When an overload appears on the slope, determined by the presence of more than three pulses in the output binary stream

5 of the same polarity, the charge / discharge rate of the integrator of the approximating signal increases by one quantized interval immediately at the moment of determining the presence of an overload B

0 the absence of overload, the charge / discharge speed of the integrator also decreases by one quantized interval, however, the time between the moments of speed reduction already depends on the speed achieved:

5 the smaller it is, the longer it takes until the next decrease. Thus, the increase in the approximation rate occurs according to a linear law, and the decline - according to a law close to

0 exponential.

The scheme works as follows. When an overload occurs (which is characterized by the appearance of a sequence of 4 or more at the output of the delta modulator

5 pulses of the same polarity) and after clocking register 4, at the output of coincidence circuit 10, logical potential 1 appears and the approximation rate counter 11 at the input of the counting direction is prepared to increase the state. If at

In this case, the maximum state of the counter has not been reached, a potential of logical 0 is generated at the output of the transfer of the counter 11, and the signal from the output of the matching circuit 10 through the logic elements 12, 14 goes to the input of the D-trigger 15.

With the arrival of the next phase of the clock 5, the trigger 15 is set to logical 1, clocking the counter 11 and allowing the counting factor to be loaded into the counter 13. At the same time, a new, increased state of the counter 11 is written to the counter 13, and the keys are 7 ° ... 7P switch the resistors 8 ° ... 8P so that the parallel resistance of the connected resistors is reduced by one step, i.e. approximation speed increases by one step. When the third phase of the clock generator 5 arrives, the counter 13 does not change its state, because at its input, the asynchronous load signal from the output of the trigger 15 continues. When the fourth phase of the generator 5 arrives, the trigger 15 is reset and the circuit is prepared for the next operation cycle. If the overload is preserved, then in the next cycle of the generator 5 the process is repeated until the overload disappears or until the counter 11 reaches the limit value. When counter 11 reaches the limit value at its transfer output, the potential of a logical unit appears, and the operation of trigger 15 is blocked through the OR-NOT 14 logic element. Thus, when the overload of the delta modulator appears, the approximation speed increases linearly until it reaches maximum approximation speed or until overload disappears.

If the overload disappears, at the output of coincidence circuit 10, a potential of logical 0 appears, preparing the approximation rate counter 11 to decrease the state. If the counter is in the boundary state, then the logical 0 potential also acts on its transfer output, the operation of trigger 15 is blocked by logic elements 12, 14, and the approximation rate counter does not change its state until the limit state is reached by counter 13. Counter 13 reaches of its limiting state through the number of ticks of the third phase of the generator 5, which depends on the count coefficient recorded in it, while at its transfer output a logical potential 1 appears, coming through the logical elements Options 12, 14 on the data input flip-flop 15. In the transition nearest the second phase clock generator 5, flip-flop 15 switches to a logic 1 state, a timing counter 11 and the velocity approximation coefficient charging a new account with the counter 13. Since a decrease in the counting coefficient code corresponds to an increase in the counting coefficient, the slower the approximation rate, the slower it changes, which ensures a close to exponential law of decreasing the approximation rate.

0 The decay time constant of the approximation speed is determined by the clock frequency of the generator 5 and the counter bit 13. When the minimum speed is reached, the transfer output of the counter 11 appears

5, the potential of a logical unit prohibiting the operation of the counter 13 at its input of the prohibition of the account, as well as the operation of the trigger 15 through the logical element 14.

Silence stabilization chain,

0, which is an integrator 3 with a time constant that is much larger than the maximum constant of the approximation circuit, automatically balances the delta modulator by equalizing on average 5 the number of output pulses of both polarities, which eliminates the appearance of a characteristic tone in approximating signal in the absence of the input signal of the delta modulator.

0 The proposed device is produced in a small batch of i + that provides for 7 bits of the counter 11, 4 bits of the counter 13 and a clock frequency of 64 kHz, the dynamic range of the transmitted signals is not less than 60

5 dB at a frequency of 1 kHz and a useful band of transmitted frequencies of at least 8 kHz. At a clock frequency of 32 kHz, the useful band is reduced to 4 kHz. At these clock frequencies, the delta modulator fully complies with the requirements for voice transmission in accordance with class I GOST 16600-72, including when transmitting fricative sounds and the presence of interfering sound signals. A device manufactured on the basis of CMOS chips saves

5 its qualitative characteristics in the range of supply voltages from 3 to 12 V, including at extreme voltage voltage mismatch delta modulator and delta demodulator.

Claims (1)

0 Claims A syllabic adaptive delta modulator containing a comparator, the first input of which is connected to the output of the adder, the first input of which 5 is the input bus, and the second input is connected to the output of the integration unit, the second input of the comparator is connected to the output of the integrator, and the output is to the information input of the shift register, the first output of which is the output bus and connected to the input of the integration unit, the outputs from the first to the fourth is connected to the corresponding inputs of the level matching unit, the output of which is connected to the input of the approximation rate control unit, a clock generator, the first output of which is connected to the trigger input of the trigger, In that, in order to reduce the coefficient of nonlinear distortion and expand the dynamic range of the transmitted signals, the level matching block is made on the equivalence element, the inputs and output of which are respectively the inputs and the output of the level matching block, the control unit with the approximation box is made on the reverse counter, counter and two elements OR NOT, and the integration unit is made on the capacitor, the main and n additional resistors and n keys, the inputs of which are combined with the first output SIC resistor are input, and integration unit, control inputs connected to respective data outputs PE REQUIRES south counter, older bits which are connected to respective setting inputs of coefficient the counter, the clock input of which is connected to the second output of the clock generator, the asynchronous download input is combined with the clock input of the reverse the counter and is connected to the trigger output, the counter inhibit input is connected to the transfer output of the reverse counter, the input of the direction control of which is the input of the approximation rate control unit and combined with the first input of the first OR-NOT element, the second input of which is connected to the counter transfer output, and output - with the first input of the second OR-NOT element, the second input of which is connected to the transfer output of the reverse counter, and the output is connected to the information input of the trigger, the reset input of which is connected to the third the clock pulse generator, the fourth output of which is connected to the clock input of the shift register, while the key outputs are connected respectively by the first terminals of the additional resistors, the second terminals of which are combined with the second terminal of the main resistor and are the output of the integration unit, which is connected through the capacitor to the zero potential bus .