NO314373B1 - Matrix addressable apparatus with one or more memory devices - Google Patents

Description

The invention relates to a matrix addressable device comprising one or more memory devices with multidirectionally switchable memory cells arranged in a passive, matrix addressable group, where the memory cells comprise a memory medium in the form of a ferroelectric or electret thin film memory material which is capable of being polarized by an applied electric field and shows hysteresis, where at least one memory device comprises two and no more than three electrode devices, where the first electrode device of the at least one memory device which is either the only memory device in the device or the first of two or more memory devices therein, is arranged on an insulating substrate .

From an architectural point of view, the passive matrix design of memories with polymer memory sandwiched between electrode layers is more attractive than the so-called 1T-1C design in the silicon memory architecture according to the prior art, especially because it provides a greater storage density in the lateral direction (4f2 versus 6f2 and greater). , but also because it allows the stacking of successive memory layers, e.g. controlled from common substrate circuit. However, it remains a fact that even a 4f2 design only provides an area fill factor of 25%. With a fill factor of 50-100%, the need for a memory layer would be reduced accordingly, as would production complexity, yield and cost. Moreover, the use of only one or two memory layers will reduce the effect of post-processing of polymer to a corresponding degree and thus affect negative performance effects resulting from such procedures.

The traditional approach is to increase cell density by reducing cell area. The narrower the cell area becomes, the smaller the signals must be (and the signal/noise ratio), and the more sensitive and therefore more complex and space-consuming the detection circuits (dominated by detection amplifiers) will have to be. In reality, it is considered an extreme challenge to form cross matrix systems of any kind with a line spacing smaller than 0.3 µm - 0.4 µm (cell size 0.09 µm<2> - 0.16 µm<2>).

A theme associated with multilayer stacking is planarization. Formation of successive layers on top gradually produces a "wavy" or uneven topography that will present significant problems for lithography control and, consequently, the ability to address and read out from the cells (e.g., detection amplifiers are performed relative to an expected cell area, and if, due to uneven lithography, this varies beyond certain limits, the signals cannot be read out reliably or the difference between "ones" and "zeros" will be difficult to determine).

The architecture also defines how many mesh steps are the necessary minimum, as the fewer there are, the less expensive the production. Reducing the number of stitches has become very important. Currently, a polymer matrix requires, for example, more than 19 more mask steps than competing flash memories for a typically smaller device with 8 memory layers, which means that the costs of processing such a chip doubles compared to current CMOS processes used, for example, for flash memories.

In a polymer cross-dot matrix memory where a vertical switching field is used, the morphology of the spun polymer film largely determines its applicability for memory use. It is a particular challenge to maintain an optimal morphology with respect to ferroelectric memories when the film thickness shrinks to below 100 nm. At such thicknesses, the films are more sensitive than to the solvents used, spinning and heat treatment conditions, the type and effect of contact and barrier layers etc. Increasingly thinner films are desirable to reduce the switching voltage, e.g. should the films be thinner than 30 nm to achieve switching voltages less than 5V. Lower voltage levels are necessary to use progressively denser lithography and achieve compatibility with associated design rules, which also allows for reduced power consumption. Low voltage is also very attractive in polymer memories, as it allows several, ultimately all circuits to be arranged under the passive memory matrix, which in turn reduces the effective cell area by reducing additional area, possibly to zero and making vias, connections, etc. .easier to execute and implement.

Producing such thin films with an acceptable uniformity/morphology and without short circuits is very demanding over large areas (such as a wafer), also

because important ferroelectric properties such as crystallinity tend to weaken with thinner films, while leakage and leakage currents represent a growing problem. This in turn greatly affects the memory properties, e.g. the level of the switchable and remanent polarization (which is of importance

to distinguish between ones and zeros), switching endurance and switching speed. Especially the high temperature performance (for example above 60°C) seems to decrease to an extreme degree.

But even thicker memory films present a number of similar problems, although not as pronounced as those encountered with thinner films. The preferred and established film application technique is spin deposition using a suitable solvent. The choice of solvents, spinning conditions, possible solvent residues, heat treatment conditions relative to the choice of solvent, etc. represent major challenges with regard to achieving the correct combination of parameters, a challenge that is all the greater than in the case of thin films. Solvents are necessary to obtain thin, uniform films on the wafer substrates.

Due to the dependence of the switching voltage on the film thickness (see below), with reduced film smoothness the coercive field will vary accordingly, which will present problems during operation if the variations are greater than the maximum permissible variation in the voltage. On the other hand, the greater the constructive impact, the more complex the circuits needed to handle it will be, with additional costs in terms of area efficiency/production complexity and facility costs.

Probably an even more significant morphological aspect is the fact that the polymer is subjected to a significant post-treatment, e.g. deposition of top electrodes, contact layers, vias and connections etc. in multi-layer memory stacks and this can have a potentially serious negative effect on the performance of the polymer, which is very difficult to control satisfactorily, especially in a commercial manufacturing process.

The use of polymer and the fact that the electrodes lie directly on this material, which has a melting temperature of approx. 150°C, results in problems as far as packaging is concerned. In a typical soldering process, temperatures can reach as high as 210°C (for limited periods), presenting problems for the architecture, as the polymer begins to melt and flow, so that the contact surface between electrodes and polymer can be damaged.

The purpose of the present invention is thus to mitigate the above-mentioned disadvantages and problems with matrix addressable memory devices according to known technology and in particular with polymer memory material and as used in a matrix addressable data storage device.

The purpose of the invention as well as further features and advantages is achieved with a matrix addressable device characterized in that the first electrode arrangement comprises parallel strip-like electrodes of width w and height h separated from each other electrically isolated by a portion of insulating thin film material arranged between the electrodes and covering the side edges to these in a layer of thickness 8, the thickness 8 being a small fraction of the electrode width w, that the electrodes have a large height/width ratio H/W, that the first electrode arrangement comprises a number of parallel recesses in its top surface and which are oriented perpendicular to the longitudinal axis of the electrodes with a width approximately equal to the electrode width w and which extends downwards from the top surface of the electrode to a distance h which is approximately half the height H of the latter, the recesses being mutually separated by a distance approximately equal to the width W of the electrodes, that at least the side walls of the recesses are covered by one thin film of the memory material and that their bottom surface is covered with insulating thin film which can optionally also be formed from the memory material, and that the electrodes of the second electrode set are arranged in the recesses in contact with and on the thin film material of these, whereby the memory material arranged in the recesses forms the memory cell of the memory device, in that a single memory cell in each case is defined in the volume of the memory material arranged between an electrode in the first electrode device and an electrode in the second electrode device at the crossing between them, whereby a memory cell can be polarized and switched in the lateral directions perpendicular to the side walls of the recess and a third direction perpendicular to the bottom surface of the recess, given that the bottom surface is also covered by the memory material.

In an advantageous embodiment of the device according to the present invention, where the at least one memory device comprises a third electrode device, the insulating thin film is arranged over the top surfaces of the electrodes in the first and second electrode device, respectively, the insulating thin film in at least a part covering the top surfaces of the electrodes in the second electrode arrangement are formed by the memory material, the electrodes in the third electrode arrangement are arranged in contact with and on the insulating thin film material in an arrangement similar to that in the first electrode arrangement and oriented in the same direction and perpendicular to the electrodes in the second electrode arrangement , so that an electrode in the third electrode device registers with the corresponding electrode in the first electrode device, whereby each memory cell is defined by a thin film of the memory material covering an electrode in the second electrode device at the crossing of the latter between an electrode in h respectively the first and third electrode devices, so that a memory cell can be polarized and switched in a fourth direction perpendicular to the top surface of an electrode in the second electrode device.

In a variant of this embodiment where two or more memory devices are arranged in a vertical stack, the top surfaces of the electrodes in the third electrode arrangement are covered by an insulating backplane, and each memory device is arranged stacked one above the other separated by the insulating backplanes, whereby the device is implemented as a volumetric data storage device.

Where the device according to the invention is made with two or more memory devices arranged in a vertical stack, the first electrode device and the second electrode device in a memory device are advantageously arranged in recording relationship with the corresponding electrode devices in any other memory device in the stack, each memory device in the stack separated from any adjacent neighboring memory device by the insulating thin film applied over the top surface of the electrodes, the insulating thin film at least in the parts where the electrodes in the second electrode device cross the electrodes in the first electrode device in the adjacent neighboring memory device is formed from the memory material which in these parts can be polarized or switched in a fourth direction perpendicular to the top surface of the electrodes in the second electrode arrangement by applying an electric field between these electrodes and crossing electrodes in the first electrode arrangement in an adjacent nth neighboring memory device, and a memory cell defined in the memory material surrounding an electrode in the second electrode device at the junction between the last and the electrodes in the first electrode device in the respective occurring memory device and an adjacent tail memory device in the stack, whereby the device is implemented as a volumetric data storage device with the first electrode device from the second memory device in the stack of a third electrode device in the underlying neighboring memory device.

In the device according to the invention, the insulating thin film material can be a ferroelectric or electret material, and the memory material can be a polymer or copolymer material. The insulating thin film material and the memory material must be made of the same material, the memory material being particularly preferably a polymer or a copolymer material.

The invention will be better understood from the following description and especially in connection with a discussion of preferred embodiments read in connection with the attached drawing, in which

fig. 1 shows a cross-section of a first electrode device used in a memory device according to the invention,

fig. 2 a ground plan of an electrode arrangement in fig. 1,

fig. 3 a cross-section of a configuration of the first electrode device taken along the line A-A in fig. 2,

fig. 4 a cross-section of the first and a second electrode arrangement in a memory device as used in the apparatus according to the invention,

fig. 5 a cross-section through the memory device used in the apparatus according to the invention before a final step in its manufacture,

fig. 6 a cross-section through the memory device in fig. 5 with arranged memory cells,

fig. 7a a plan view of the memory device in fig. 6 and which shows the arrangements of memory cells therein,

fig. 7b a cross-section through the memory device of fig. 7a, taken along the line a-a,

fig. 8a a plan view of a memory cell in the memory device of fig. 7a and 7b,

fig. 8b a cross-section through the memory cell of fig. 8a, taken along the line C-C,

fig. 9 a cross-section through the memory device in fig. 7a with another embodiment of the memory cells,

fig. 10 a third electrode device in the memory device as used in the device according to the invention,

fig. 1 shows a variant of the memory device used in the device according to the invention,

fig. 1 lb a cross section of the memory device of fig. 1 la, taken along the line A-A,

fig. 12a a preferred embodiment of the device according to the invention in a stacked configuration,

fig. 12b a plan view of a memory cell therein, and

fig. 12c a cross-section taken along the line C-C in the memory cell of fig. 12b.

The apparatus according to the invention will now be explained in detail with a thorough discussion of its individual parts and their execution, as shown in the figures.

Fig. 1 shows a cross-section of an electrode device in the device according to the invention. The electrode arrangement El comprises a number of parallel electrodes el which appear as strip-like in the ground plan of the electrode arrangement in fig. 2. Each electrode or is placed on an insulating substrate 1 and separated only by means of an insulating thin film 2a which prevents ohmic contact between the individual electrodes or. The electrodes el are realized with a height H and a width w, but with a relatively large height/width ratio H/w. This insulating thin film 2a has a thickness 5 which is typically smaller than the electrode width w, and this means that almost the entire area of an electrode device as its footprint appears in fig. 2, is occupied by the electrodes, while the insulating thin film layer or barrier 2a between the electrodes occupies only a small part of this (if a lithography of 0.15 µm or larger is used; finer lithography reduces this difference). An electrode device of this kind can be produced by a method as shown in Norwegian patent application no. 20015509 submitted on 9 November 2001 and which belongs to the inventor of the present application, and consequently the method in question for producing a dense electrode device of this kind shall not be elucidated further detail here, as the above application may be considered incorporated by reference. In this connection, however, it should be noted that the electrode width may correspond to a process-limiting minimum feature f, the size of which will depend on e.g. construction rules such as can be used in a photomicrolithographic patterning process. In any case, this implies that either the electrode width w or the distance d from one of the electrodes to the next in the electrode arrangement El will be subject to a construction rule of this nature, while this need not be the case for the thickness of insulating thin film which can be deposited by processes unrestricted by any conventional rule of construction. It also follows that the real width of e.g. every second electrode el in the electrode arrangement El can then be smaller than the process-limited minimum distance f with a value of 28, i.e. that it is the distance d = w + 28 that is in reality limited by the construction rule.

Regarding the ground plan in fig. 2 shows the electrode arrangement with depressions 3 formed downwards from the top surfaces of the electrodes or therein. These recesses 3, which may have approximately the same width w as the electrodes el, extend perpendicularly to the electrodes el and are separated by the remaining parts of the electrodes el which can correspondingly have a width of approximately w. The depressions 3 extend from the top surface of the electrodes el and downwards towards the substrate over a distance h and have a mainly rectangular cross-section. At the bottom of the depressions, the electrodes e 1 will be connected by a section of these which extends to a height 8h above the substrate 1. It should be understood that while 8h + h = H, the size of h can be chosen as approx. 50% of H. This can best be seen in fig. 3 which shows a cross-section of the electrode device el in fig. 2 taken along the line A-A, in other words seen from the direction indicated by B. Now the electrode el with the depressions 3 is covered by an insulating thin film 4, and another electrode device E2 comprising the electrodes s2 is formed by depositing electrode material in the depressions 3, as shown in the cross section of the electrode device EI shown in fig. 4. The insulating thin film 4 can be any dielectric thin film material, but preferably it could be a ferroelectric or electret thin film material, which will be described in more detail below. After the electrodes e2 of the second electrode device E2 have been arranged in the recesses 3, the insulating thin film 4 is etched away wherever it is not covered by the deposited electrodes e2, and this gives a structure as shown in fig. 5. Empty tracks 3a are now formed in the remaining parts of the depressions 3 between the electrodes el, e2 with the part 4b of insulating thin film on the bottom of the depressions 3. The side walls of the depressions 3 in the electrodes el are now exposed. The slots 3a can then be filled with a memory material, e.g. a ferroelectric or electret polymer material 4a, which will extend along the tracks between the electrodes e1 and e2 as shown in fig. 6. If the insulating thin film material 4 was originally a ferroelectric or electret material, the part 4b shown at the bottom of the depressions 3 below the electrodes e2 will now also be a memory material similar to that shown as 4a in fig. 6. Fig. 7a shows a ground plan of the completed structure as shown in fig. 6. In fig. 7a, B indicates the viewing direction for the cross-section shown in fig. 6. It will now be seen that the electrodes e2 in the second electrode arrangement E2 are oriented perpendicularly to the electrodes el in the first electrode arrangement El. The memory material 4a arranged between the electrodes e1 and e2 at the grooves between them in the recesses 3 now constitutes the memory medium in the memory cells 5 formed in the memory material 4a and optionally 4b at the crossing of an electrode s2 in the second electrode device E2 with an electrode el in the first electrode device El and consequently provides the structure of fig. 7a with the memory material and electrodes e 1, e2 now a passive, matrix-addressable group of memory cells 5 which should in particular be ferroelectric or electret memory cells and even more preferably as realized with the memory material in the form of a polymer or copolymer. Fig. 7b shows a section through fig. 7a taken along the line A-A and it can now be seen how the application of voltage across the electrodes el and e2 so that an electric potential is obtained in between over the memory material 4a and optionally also 4b, means that the memory cells 5 are either polarized or switched in different directions. The batch of memory cells at 4a can e.g. is welded in a lateral direction relative to the extent of the memory device, while the optional part of the memory material 4b at the bottom of the recess 3 can be welded in a direction perpendicular to the plane of the memory device or as indicated in fig. 7b, in a vertical direction. By doing this, three "subcells" can be switched on at the same time, whereby a three times larger signal is obtained, while the area of the subcell at the bottom becomes equal to the overlapping area of the electrodes and the area in the two side walls amounts to 2wh. The latter case therefore introduces an extra dimension compared to vertically switched cells as known in the art, which means that the cell's footprint will be independent of a construction rule used. Fig. 8a and 8b show a memory cell in a memory device in the device according to the invention in more detail, with the switching directions indicated as they may occur and corresponding to the legend given in connection with fig. 8a and 8b. Fig. 8a shows a plan of a single memory cell with the electrodes removed and it will be seen that all memory material in the side walls can be welded in the lateral direction, while the memory material in the bottom can be welded in a vertical direction. This can also be clearly seen in fig. 8b, which shows a cross-section of the memory cell 5 in fig. 8a taken along the line C-C and with an outline of the electrodes el, e2 indicated by dashed lines. This embodiment of a memory cell 5 differs significantly from conventional memory cells in passive matrix addressable memory devices, where the memory cell is arranged in a sandwich between overlying and underlying electrode devices with the respective electrodes oriented mutually orthogonally to define and address a memory cell in e.g. a global layer of the memory material sandwiched between the electrode layers. A conventional sandwich design of this kind only allows a single switching direction, while the memory cells in the device according to the invention will allow at least three switching directions and this in turn should entail a significant advantage for producing more reliable and more densely packed passive matrix addressable devices with a ferroelectric or electret memory material, including an improved signal to noise ratio. A consideration of FIG. 7a shows that the memory device as shown there can be switched in three directions in a total of thirty places for ten definable memory cells.

A fourth switching direction can now be obtained by arranging a third electrode device E3 in the memory device in the apparatus according to the invention. Fig. 4 shows how the top surfaces of the electrodes el, e2 in respective electrode devices El, E2 are coated with an insulating thin film 4, which e.g. can be formed from a ferroelectric or electret memory material, e.g. a polymer or copolymer material. At least on the top surface of the electrodes e2, the insulating thin film must be a memory material, e.g. of the latter kind, and correspond to the lots 4c as shown in fig. 9. Now a third electrode arrangement E3, which in reality is similar to the first electrode arrangement El except that the electrodes e3 have a smaller height/width ratio, can be arranged above the insulating thin film 4 with the electrodes e3 oriented in the same direction as the electrodes el in the electrode arrangement El, so that each electrode e3 in the former registers with the similar corresponding electrode el in the latter. The electrodes e3 in the electrode arrangement E3 can e.g. be arranged on an insulating back plane 1' as shown in fig. 10. A memory device is thus obtained which is somewhat schematically represented in the ground plan in fig. 1 la, which is to be considered in connection with fig. 1 lb showing a cross-section through the plan view of fig. 1 la taken along the line A-A and seen in the direction from B. Each memory cell 5 is defined in the usual way and can, as shown in fig. 1 lb, is now polarized or switched in four directions, as the parts 4c of the memory material in a cell 5 can now be addressed via an electrode e2 in the second electrode device E2 and an orthogonally crossing electrode e3 in the third electrode device E2. In other words, each memory cell can be addressed in four directions at four different places in it. Furthermore, a memory device similar to that shown in fig. 1 la and 1 lb now be used in the apparatus according to the invention to implement the latter as a volumetric data storage apparatus by simply stacking the memory devices shown in fig. 1 la and fig. 11b on top of each other. Each memory device in the stack will naturally be separated by the insulating backplane 1'.

However, a better economic result or embodiment of the apparatus according to the invention can be obtained as a volumetric data storage apparatus with stacked memory devices, with a configuration as shown in fig. 12a. The basic building block here is the memory device as shown in fig. 9 and with insulating thin film 4 arranged on top of this. The thin film 4 can of course be a ferroelectric or electret material and must in any case in parts above the top surfaces of the electrodes s2 be a memory material, e.g. a ferroelectric or electret material, preferably a polymer or copolymer material of this kind. Thus, memory devices like the one in fig. 9 are stacked on top of each other and form a stack Sl, S2, S3 with memory devices of this nature and it will be seen that the electrodes sl in an adjacent memory device now perform the function of the electrodes e3 in the memory device shown in fig. 11b. In other words, the device according to the invention shown in fig. 12a with stacked memory devices allow polarization and switching of the memory cells in four directions, i.e. two lateral directions and two vertical directions and at four separate locations in each memory cell. The apparatus shown in fig. 12a is, in other words, much simpler than the apparatus based on a memory device configured similar to that shown in fig. 11b.

Fig. 12b shows a plan view of a memory cell 5 in the device of fig. 12a with the electrodes removed and the switching directions indicated according to the accompanying legend. Fig. 12c shows a cross-section of the memory cell 5 in fig. 12b taken along the line C-C and clearly shows the switching directions as well as the box-like structure of a memory cell 5 in the apparatus according to the invention. Any memory cell in a memory device in the apparatus according to the invention as shown in fig. 12 will naturally be defined by the memory material which surrounds the electrodes e2 at the crossing between them and respective overlying and underlying electrodes sl which are oriented orthogonally to the aforementioned.

It should also be noted that the ten memory cells which can be obtained in a memory device as shown in fig. 1 la or fig. 12a in each case allows no less than 40 addressing sites can be compared to half this number of cells with a single addressing site for each which can be obtained in a common sandwich structure occupying the same area as e.g. a single memory device in the device such as shown in fig. Ila or 12a. The area filling factor is also doubled from 0.25 to 0.5 and with the further result of a doubled storage density at least a doubled capacitor area which provides a greatly improved signal/noise ratio and detectability. It should also be noted that the recesses that accommodate the electrodes e2 and the memory material can be made much wider than e.g. a process-limited minimum draw f, while the width w of the electrode e2 can be considerably smaller. Consequently, the memory material 4 can be deposited with a correspondingly greater thickness and the same would also apply to the memory cell parts 4b and 4c. The thickness of the memory material in these is of course not limited by another specific construction rule as it can be applied by various methods well known to those skilled in the art and with a thickness as described and which extends from a few nanometers upwards.

It should be noted that the apparatus according to the invention is not limited to the preferred exemplary embodiments shown above. Other variants can be produced within the framework of the invention.

The proposed concept introduces a new cell architecture that allows imprinting

of a field in a lateral direction in relation to the (circuit) substrate (if the construction is hybrid). This can be combined with the printing of vertical fields, potentially at the same time. Multilayer memories can be built with just one single polymer layer and a deposition, optionally, carried out as a final processing step, as neither metal nor anything else must be deposited on the polymer, so that the mentioned problems associated with subsequent processing on polymer are avoided.

A memory matrix based on lateral switching can be produced in a number of ways

ways. A preferred embodiment is the following procedure. A thin insulating layer is deposited on the silicon wafer (for example SiO 2 or a ferroelectric polymer material such as polyvinylidene difluoride or the copolymer polyvinylidene difluoride-trifluoroethylene (PVDF-TrFe)). A first set of (parallel) electrodes is then built in this layer (first mesh step), e.g. with twice the thickness (height) or height/width ratio H/w of a typical

electrode as otherwise used for a cross-point matrix memory of similar size and functionality. An insulating layer is then applied globally. Then the gap between the electrodes will be filled with an electrode material, (the same or a different one, possibly a variety of different ones) to form another set of electrodes. The resulting electrode pattern is termed a "dense electrode pattern", as shown in the above-mentioned Norwegian patent application. These two sets of electrodes will hereafter be called "bottom electrodes". Then a third set of parallel (top) electrodes oriented at 90° to the first two is deposited, by first making openings that extend sufficiently through the bottom electrodes, e.g. with (50%) using a (different) mask. A global insulation material is then applied, e.g. different from that used for the bottom electrodes, e.g. in the form of ferroelectric copolymer (necessary if vertical switching is to be used), followed by a filling in the top electrode with the same or alternative electrode material. Chemo-mechanical polishing (CMP) or another planarization process is then used, e.g. global etching, to get rid of excess electrode/insulator material, so that the insulator material between all three electrode sets is exposed and a complete isolation is thus obtained between each of the electrode sets, the result being a cross-point matrix group where the top surfaces of the bottom electrodes and the top electrodes are located in the same plane. The insulator material is then etched away down to the bottom level of the top electrode and it is filled with memory material, e.g. a ferroelectric polymer, either with traditional spin coating or an alternative method, e.g. dip coating from melt.

The final etching and filling steps can be avoided if the insulator material is a ferroelectric material throughout or only constitutes the top insulator material. The advantage of this is that there are no problems with filling the polymer material in the narrow openings between the electrodes; the disadvantage is that the polymer material will be subject to processing. The polymer material's ability to penetrate the narrow openings between the electrodes can be further improved by using electrostatic or similar attraction methods, and furthermore, because the bottom of the openings will always be an insulating material, the PVD-TrFe film will not have to penetrate all the way down to the bottom of the openings.

By applying voltage to one of the bottom electrodes and the top electrodes, the polymer material on both sides of the top electrode where the corresponding bottom electrode crosses will be welded in the lateral direction. The thickness of the polymer material corresponds to the thickness of the polymer film in the vertical switching architecture. This means that the level of applied voltage required to achieve complete polarization switching is a direct function of the thickness of the polymer material between the electrode openings and thus controlled by the thickness of the applied insulator material, not by the thickness of the spun polymer layer. This ensures a much more uniform thickness than if the polymer was applied in a vertical structure and also that uneven sidewalls on the electrodes do not destroy this uniformity, as the opposite electrode wall will reflect unevenness in the other sidewall.

The fact that both sides of the top electrodes switch simultaneously means that the effective cell area is doubled and that the signal/noise ratio is thus improved by a factor of 1.42. The effective cell area can be further improved by making the top/bottom electrode thicker, as the cell area becomes equal to the cell's length W multiplied by the cell's height h. This fact allows an arbitrarily large cell area regardless of the cell's lateral footprint by introducing a vertical cell dimension. The cell's height and thickness are not critical even when using higher resolution lithography. All this will consequently improve the cell's fatigue resistance during switching.

The storage density of the first electrode structure corresponds to 2f2 or f2. If dense electrodes are used as top electrodes, this will only result in two mesh steps. This is good compared to vertical architecture which would need two (or four) memory layers and 3 (or 6) mask steps to achieve the same.

Once this first "layer" is formed, further layers can be added in various ways. One is simply to deposit polymer film on top of the first structure and then build a new bottom electrode set on top of this. Thus, the top electrode in the first structure will combine with the bottom electrode in the next to form an additional 2f2 (or f2) memory layer (albeit with only one cell area per cell). As this only requires one mesh step, the resulting stack representing a full f2 (or a density of 1/2 f2) would only involve three mesh steps, whereas with the vertical architecture the same density would be required (including all mesh steps except for meshes for vias ) 6 (or 12) stitches (two double or four double layers). By adding a top electrode to the second structure, a density of 2/3 f2 is obtained, a new bottom electrode gives 1/3f2 etc.

If it is limited to the first electrode structure or layer and the insulating material is etched away with subsequent filling of polymer film, there will be no processing on the polymer, which means that a 2f2- (or f2-) structure can be built without the polymer being weakened by a subsequent deposition, which is considered to be highly beneficial in maintaining a morphology that is optimal for memory applications.

Since there is a planarization step between each layer, there will be no loss of lithographic density or film unity when adding successive layers, which also means that apart from possible complications with regard to vias, there is technically no limit to how many layers can be is stacked in this way in contrast to vertical architecture where planarization becomes more and more difficult to achieve with successive layers.

An alternative method for building laterally switchable cells is as follows. First, the parallel bottom electrodes are formed and each electrode provided with finger-like extensions separated by a lithography step extending from the electrode. On these electrodes, another set of electrodes deposited on the same plane, i.e. the same substrate level, is formed by letting these top electrodes "climb" over the bottom electrodes where they cross. The cell is then defined in the area where finger-like extensions are overlapped by the top electrodes, as the distance between them determines the film thickness, i.e. it is the distance between the finger-like extension and the top electrode that must represent the required coercive field. In order to make this sufficiently short (preferably less than 0.06 µm), which is difficult to achieve with lithography, a number of techniques can be used. One is "misalignment" of the top electrode relative to the bottom electrode, for example with a value less than 0.06 µm, as this misalignment/displacement then constitutes the film thickness in a vertical cell structure. Alternatively, a method with dense electrodes and the barrier layer can be used.

Variations of the above designs can be used to achieve a higher cell area density. One would be to arrange the finger-like extensions further apart, e.g. two lithography steps gone, so that switching can be achieved on both sides of the extensions, as there will now be two separate top electrodes surrounding each side of the fingers. It is also possible to use the concept of dense electrodes to form denser top electrodes to achieve a greater increase in cell density.

Claims (8)

1. Matrix addressable device comprising one or more memory devices with multidirectionally switchable memory cells (5) arranged in a passive, matrix addressable group, where the memory cells (5) comprise a memory medium in the form of a ferroelectric or electret thin film memory material which is capable of being polarized by a impressed electric field and shows hysteresis, where at least one memory device comprises two and no more than three electrode devices (E), where the first electrode device (E) of the at least one memory device which is either the only memory device in the device or the first of two or several memory devices therein, are arranged on an insulating substrate (1), and where the device is characterized in that the first electrode device (1) comprises parallel strip-like electrodes (el) with width w and height h separated from each other electrically insulated by a part (2a) of insulating thin film material arranged between the electrodes (el) and which covers the side edges of these in a layer with thickness 8, the thickness 8 being a small fraction of the electrode width w, that the electrodes (sl) have a large height/width ratio H/W, that the first electrode device (El) comprises a series of parallel recesses (3) in its top surface and which is oriented perpendicular to the longitudinal axis of the electrodes (el) with a width approximately equal to the electrode width w and which extends downwards from the top surface of the electrode (el) to a distance h which is approximately half the height H of the latter, the recesses (3) being mutually separated by a distance approximately equal to the width W of the electrodes, that at least the side walls of the recesses (3) are covered by a thin film (4) of the memory material and that their bottom surface is covered with m ed insulating thin film (4b) which can optionally also be formed from the memory material, and that the electrodes (el) of the second electrode set (E2) are arranged in the recesses (3) in contact with and on the thin film material (4a, 4b) of these, whereby the memory material arranged in the recesses (3) forms the memory cell (5) of the memory device, a single memory cell (5) in each case being defined in the volume of the memory material arranged between an electrode (el) in the first electrode arrangement and an electrode (e2) in the second electrode arrangement at the intersection between these, whereby a memory cell (5) can be polarized and switched in the lateral directions perpendicular to the side walls of the recess (3) and a third direction perpendicular to the bottom surface of the recess (3), given that the bottom surface is also covered by the memory material. 2. Apparatus according to claim 1, where the at least one memory device comprises a third electrode device (E3), characterized in that the insulating thin film (4) is arranged over the top surfaces of the electrodes (sl;e2) in the first and second electrode arrangement (E1;E2) respectively, the insulating thin film (4) in at least one part (4c) covering the top surfaces until the electrodes (s2) in the second electrode device (E2) are formed from the memory material, that the electrodes (e3) in the third electrode device (E3) are arranged in contact with and on the insulating thin film material (4) in an arrangement similar to that in the first electrode device (El) and oriented in the same direction and perpendicular to the electrodes (e2) in the second electrode device (E2), so that an electrode (e3) in the third electrode device (E3) registers with the corresponding electrode (sl) in the first electrode device (El), whereby each memory cell (5) is defined by a thin film (4a, 4b, 4c) of the memory material covering an electrode (e2) in the other electrode device (E2) at the junction of the latter between an electrode (e1; e3) in respectively the first and third electrode arrangement (E1;E3), so that a memory cell (5) can be polarized and switched in a fourth direction perpendicular to the top surface of an electrode (s2) in the second electrode arrangement (E2). 3. Apparatus according to claim 2, where two or more memory devices are arranged in a vertical stack, characterized in that the top surfaces of the electrodes (e3) in the third electrode device are covered by an insulating back plane (1), and that each memory device is arranged stacked on top of each other separated by the insulating back planes (1), whereby the device is implemented as a volumetric data storage device. 4. Apparatus according to claim 1, where two or more memory devices are arranged in a vertical stack, characterized in that the first electrode device (El) and the second electrode device (E2) in a memory device are arranged in a recording relationship with respectively the corresponding electrode devices (E1;E2) in any other memory device in the stack, that each memory device in the stack is separated from any adjacent neighboring memory device of the insulating thin film (4) applied over the top surface of the electrodes (el;e2), the insulating thin film (4) at least in the parts (4c) where the electrodes (e2) of the second electrode device (E2) cross the electrodes (el) in the first electrode device (El) in the adjacent neighboring memory device are formed by the memory material which in these parts (4c) can be polarized or welded in a fourth direction perpendicular to the top surface of the electrodes (e2) in the second electrode device (E2) by applying an electric field between these electrodes and crossing electrodes (el) in the first electrode device (El) in an adjacent neighboring memory device ng, and that a memory cell (5) is defined in the memory material that surrounds an electrode (e2) in the second electrode device (E2) at the junction between the latter and the electrodes (el) in the first electrode device in the respective occurring memory device and an adjacent neighboring memory device in the stack, whereby the device is implemented as a volumetric data storage device with the first electrode device (El) from the second memory device in the stack by a third electrode device in the underlying neighboring memory device. 5. Apparatus according to claim 1, characterized in that the insulating thin film material (4) is a ferroelectric or electret material. 6. Apparatus according to claim 1, characterized in that the memory material is a polymer or copolymer material. 7. Apparatus according to claim 1, characterized in that the insulating thin film material (4) and the memory material are the same material. 8. Apparatus according to claim 7, characterized in that the memory material is a polymer or copolymer material.