NO304169B1 - Method and circuit for digital / analog conversion - Google Patents

Abstract

The invention relates to a method and an arrangement for digital/analog conversion in the return branch of an analog/digital modulator loop of an interpolative bandpass A/D converter. The D/A conversion is effected by a biphase interpolation. As a result, delay times up to 1.5 times the loop clock period are tolerated. The overall signal/noise ratio is better than in the case of rectangular interpolation. <IMAGE>

Description

This invention relates to a method and a circuit for digital/analog conversion (D/A conversion) according to the introduction in the subsequent patent claims 1 and 6, in particular for the conversion of bandpass signals.

What are called interpolative A/D converters for such signals find particular application within mobile radio technology.

In German patent application P 39 43 072, an interpolative A/D converter for signal processing of bandpass signals is described. Fig. 1 shows the input part of such an A/D converter, namely the so-called analogue/digital modulation loop. This part of the converter is a control circuit consisting of a coarse quantizing A/D converter, a D/A converter with corresponding resolution, summation term, linear network with transfer function H(p), and coefficient term (aif hi).

The A/D and D/A converter is operated at the clock frequency fa. The special transmission properties of the modulation loop allow the use of 1 b ("one-bit") A/D and D/A converters and overall provide a very good resolution. The immunity to quantization errors at the A/D interface greatly facilitates monolithic integration, in direct contrast to non-interpolative techniques of equivalent resolution.

The working speed that has been achieved so far with such a described circuit structure is determined by the inevitable loop time delay (the loop's group running time). In the following, it will be shown that you will get significant implementation losses with the 1 b D/A conversion if you do not take special connection technical measures, in the extreme case you will actually be able to get instability.

A real D/A converter usually provides a square-shaped interpolation process: the digital signal that appears as a pulse sequence at the input of the D/A converter is interpolated in it into a square shape (fig. 3A). A sequence of square pulses is thus produced. In the case where the D/A conversion is 1 b, depending on the sign of the input pulse, a positive or negative square pulse of duration T will be established, with T indicating the period time for the sampling, clock or sampling frequency. In practice, to avoid pulse transmission, shortened square pulses or targeted rounded pulses will also be used. However, this does not change anything in terms of the loop delay, so that such a circuit structure with square interpolation in the feedback also represents the state of the art in terms of loop delay.

The influence of the loop running time or delay on the signal resolution shall be illustrated in the following by means of an example of a circuit structure with two bandpass integrators. Fig. 2 shows this structure in a preferred version. Compared to the bandpass integrator, this circuit solution is advantageous in that it provides a clearly better signal/noise ratio, and it is also advantageous over circuits that have more than two bandpass integrators in that it becomes more insensitive to major changes in the process parameters during monolithic integration.

For the circuit with square interpolation, fig. 4a the influence of the relative loop delay T (= absolute loop running time in relation to the period time of the sampling) on the signal resolution for the overall circuit for different values of a control parameter a. From fig. 4a, the following conclusion can be drawn: For a=0, the control loop works unstable even with ideal component conditions (T=0). Only after a certain value a>0 and depending on the loop delay is stability achieved. The signal-to-noise ratio achieved at the stabilization limit then clearly decreases with increasing loop delay. For T>0.5, the regulation in the regulation circuit can no longer be stabilized by changing a.

The invention is therefore based on the task of improving the sensitivity of the analogue/digital modulation loop to real loop delays, which is particularly important for high-frequency applications.

The task is solved by the features that appear from the character in the subsequent patent claims 1 and 6, while advantageous embodiments and continuations will appear from the associated subclaims.

The invention will now be described with the help of an embodiment example supported by schematic drawings.

In order to improve the system conditions for the loop delay, it is suggested that the interpolation function for the D/A converter be modified as shown in fig. 3b. In this case, the technique is referred to as two-phase interpolation. The improvements that can thereby be achieved quantitatively can be seen from fig.4b: Delays up to 1.5 times the loop period time will be tolerated, and the signal/noise ratio will also be better than for a square interpolation.

In fig. 5 shows how the two-phase interpolation can be carried out in the most favorable way. In order to prevent further delay times when carrying out the interpolation, the A/D and D/A converters in the analogue/digital modulation loop are combined with each other. A comparator 1 with its differentially processed logic outputs Q and Q serves as 1 b quantization element. A flip-flop 2 of the D type produces an alternating square signal R with period time T = l/fa. In EL LER coupling with the comparator outputs Q and Q with the alternating square signal, the signal pair (J,K) for controlling the actual sample flip-flop 3 finally appears. This flip-flop is of the JK type and is operated in the same way as the first flip-flop of D -type, at the double clock frequency, i.e. 2fa. Table 1 is a true table for the JK rocker, and in the following, this table will be referred to several times.

Between the comparator 1 and the D flip-flop, two OR gates are arranged which work as a common gate depending on the logic level of the alternating square signal with repetition frequency fa. In the half period indicated by R = "low", the gate is opened, i.e. the following applies: J = QogK: =Q. JogK in this case has a different logic level and consequently the truth table Qntl: = Jn applies. The logic level that emerges from the comparator is consequently passed on by the JK flip-flop.

In the next half-period characterized by R = "high", the common gate is closed. Due to the OR connection applies: J : = "high"

and K : = "high".

According to the truth table, this leads to a switch at the output of the JK flip-flop and consequently to producing a sequence which is built up of two-phase pulses. The output signal from the JK flip-flop can therefore be interpreted as the output signal from a 1 b D/A converter with two-phase interpolation.

A continuation of the 1 b signal in the digital part is a connection where a second D flip-flop 4 is included to sample the two-phase signal during the first half-period, with sampling frequency fa. With respect to the branch consisting of the comparator-"JK-flip-flop"-"the second D-flip-flop, the device works as a 1 b A/D-D/A-A/D converter.

Claims (6)

1. Method for digital/analog conversion in the feedback branch of an analog/digital modulator loop in an interpolative bandpass A/D converter, CHARACTERIZED IN THAT the D/A conversion is performed by two-phase interpolation. 2. Method according to claim 1, CHARACTERIZED BY generating comparator signals Q, Q from a comparator (1), generating an alternating square signal R from a first D flip-flop (2), ORing the comparator output signals Q, Q with the alternating square signal R to generate a signal pair J, K for controlling a JK flip-flop (3), producing a two-phase interpolated signal at the output of the JK flip-flop (3), and further processing of the two-phase interpolated signal using a second D flip-flop (4). 3. Method according to claim 2, CHARACTERIZED IN THAT the first D flip-flop (2) is connected as a bistable inverter and is driven at twice the modulator loop's clock frequency fa, i.e. 2fa, and generation of an alternating square signal R with period time T = l/fa from the first D flip-flop (2). 4. Method according to claim 2, CHARACTERIZED IN THAT the JK flip-flop (3) is operated at twice the clock frequency fa, i.e. 2fa. 5. Method according to claim 2, CHARACTERIZED IN THAT the two-phase signal is sampled during the first half-period at the clock frequency fa via the second D flip-flop (4). 6. Circuit for performing digital/analog conversion, in particular by two-phase interpolation, in the feedback branch of an analog/digital modulator loop in an interpolative bandpass A/D converter, and arranged to: generate comparator signals Q, Q from a comparator (1) , perform coupling of the comparator's output signals Q, Q to produce a signal pair J, K for controlling a JK flip-flop (3) and produce a two-phase interpolated signal at the output thereof, and further processing of this signal by means of a second D flip-flop (4), CHARACTERIZED BY the fact that an OR gate is arranged between the comparator (1) and the JK flip-flop (3) which can be controlled by an alternating square signal from a first D- flip-flop (2) , and that the second D flip-flop (4) is connected to the output of the JK flip-flop (3).