NO20051122L - Fremgangsmate for a etablere referansenivaer for avfoling av flerniva minnetilstander - Google Patents
Fremgangsmate for a etablere referansenivaer for avfoling av flerniva minnetilstanderInfo
- Publication number
- NO20051122L NO20051122L NO20051122A NO20051122A NO20051122L NO 20051122 L NO20051122 L NO 20051122L NO 20051122 A NO20051122 A NO 20051122A NO 20051122 A NO20051122 A NO 20051122A NO 20051122 L NO20051122 L NO 20051122L
- Authority
- NO
- Norway
- Prior art keywords
- currents
- streams
- fractional
- procedure
- memory states
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5645—Multilevel memory with current-mirror arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Amplifiers (AREA)
Abstract
Sammendrag For å etablere grensestrømnivåer (IL, IM, IH) for mer enn to minnetilstander vil en krets (figur 2) bli skaffet til veie som bruker referansestrømmer (IR00, IR01, IR10, IR11) som definerer senteret av hver tilstand. Referansestrømmene blir definert ved flere forhåndsprogrammerte referanseminneceller (21) eller ved en enkelt referanseminnecelle (21, "11") sammen med et strømspeil (37) som setter de andre referansestrømmene ved spesifiserte proporsjoner for en første referanse (IR11). Med disse referansestrømmene vil en analog kretsblokk (53) generere fraksjonelle strømmer ved (1-m) og m for referansestrømmene, der m er en spesifisert marginverdi som tilsvarer 50 % for leseoperasjoner og mindre enn 50 % for programverifiseringsoperasjoner. Deretter kombineres (figur 4) fraksjonelle strømmer for tilstøtende tilstander for å produsere grensestrømnivåer. De fraksjonelle strømmene ((1-m)IRi, (m)IRj) kan oppnås med par av strømspeil (73, 74) forspent av avfølingsforsterkere (71, 72) for de forskjellige referansestrømmer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/211,437 US6618297B1 (en) | 2002-08-02 | 2002-08-02 | Method of establishing reference levels for sensing multilevel memory cell states |
PCT/US2003/019592 WO2004013863A1 (en) | 2002-08-02 | 2003-06-18 | Method of establishing reference levels for sensing multilevel memory cell states |
Publications (1)
Publication Number | Publication Date |
---|---|
NO20051122L true NO20051122L (no) | 2005-05-02 |
Family
ID=27788748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO20051122A NO20051122L (no) | 2002-08-02 | 2005-03-02 | Fremgangsmate for a etablere referansenivaer for avfoling av flerniva minnetilstander |
Country Status (10)
Country | Link |
---|---|
US (1) | US6618297B1 (no) |
EP (1) | EP1552528A4 (no) |
JP (1) | JP2005535062A (no) |
KR (1) | KR20050032106A (no) |
CN (1) | CN1672216A (no) |
AU (1) | AU2003256278A1 (no) |
CA (1) | CA2494075A1 (no) |
NO (1) | NO20051122L (no) |
TW (1) | TWI227895B (no) |
WO (1) | WO2004013863A1 (no) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6999345B1 (en) | 2002-11-06 | 2006-02-14 | Halo Lsi, Inc. | Method of sense and program verify without a reference cell for non-volatile semiconductor memory |
EP1699054A1 (en) * | 2005-03-03 | 2006-09-06 | STMicroelectronics S.r.l. | A memory device with a ramp-like voltage biasing structure and reduced number of reference cells |
JP2006294144A (ja) * | 2005-04-12 | 2006-10-26 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP4772363B2 (ja) * | 2005-04-12 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7310255B2 (en) * | 2005-12-29 | 2007-12-18 | Sandisk Corporation | Non-volatile memory with improved program-verify operations |
US7224614B1 (en) * | 2005-12-29 | 2007-05-29 | Sandisk Corporation | Methods for improved program-verify operations in non-volatile memories |
US7948803B2 (en) * | 2006-03-16 | 2011-05-24 | Freescale Semiconductor, Inc. | Non-volatile memory device and a programmable voltage reference for a non-volatile memory device |
US7952937B2 (en) * | 2006-03-16 | 2011-05-31 | Freescale Semiconductor, Inc. | Wordline driver for a non-volatile memory device, a non-volatile memory device and method |
WO2007104337A1 (en) * | 2006-03-16 | 2007-09-20 | Freescale Semiconductor, Inc. | Bitline current generator for a non-volatile memory array and a non-volatile memory array |
KR101498669B1 (ko) * | 2007-12-20 | 2015-03-19 | 삼성전자주식회사 | 반도체 메모리 시스템 및 그것의 액세스 방법 |
US8027187B2 (en) * | 2008-09-12 | 2011-09-27 | Micron Technology, Inc. | Memory sensing devices, methods, and systems |
KR101574208B1 (ko) * | 2009-03-31 | 2015-12-07 | 삼성전자주식회사 | 불휘발성 메모리 장치, 그것을 포함하는 메모리 시스템, 그리고 그것의 동작 방법 |
US7916537B2 (en) * | 2009-06-11 | 2011-03-29 | Seagate Technology Llc | Multilevel cell memory devices having reference point cells |
KR101027696B1 (ko) * | 2009-12-29 | 2011-04-12 | 주식회사 하이닉스반도체 | 전류 센싱 회로 및 그를 이용한 반도체 메모리 장치 |
TWI668698B (zh) * | 2016-01-26 | 2019-08-11 | 聯華電子股份有限公司 | 記憶體電流感測器 |
JP2018195362A (ja) * | 2017-05-17 | 2018-12-06 | セイコーエプソン株式会社 | 不揮発性記憶装置、半導体装置、及び、電子機器 |
CN109935273B (zh) * | 2017-12-19 | 2020-11-10 | 上海磁宇信息科技有限公司 | 一种对mtj电阻进行筛选的电路 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268870A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Flash EEPROM system and intelligent programming and erasing methods therefor |
US6002614A (en) | 1991-02-08 | 1999-12-14 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
DE69523304T2 (de) | 1994-06-02 | 2002-07-11 | Intel Corp | Dynamischer speicher mit einem bis mehreren bits pro zelle |
US6044019A (en) * | 1998-10-23 | 2000-03-28 | Sandisk Corporation | Non-volatile memory with improved sensing and method therefor |
KR100371022B1 (ko) * | 1998-11-26 | 2003-07-16 | 주식회사 하이닉스반도체 | 다중비트 메모리셀의 데이터 센싱장치 |
US6538922B1 (en) * | 2000-09-27 | 2003-03-25 | Sandisk Corporation | Writable tracking cells |
JP2002184190A (ja) * | 2000-12-11 | 2002-06-28 | Toshiba Corp | 不揮発性半導体記憶装置 |
-
2002
- 2002-08-02 US US10/211,437 patent/US6618297B1/en not_active Expired - Fee Related
-
2003
- 2003-06-18 WO PCT/US2003/019592 patent/WO2004013863A1/en active Application Filing
- 2003-06-18 KR KR1020057001918A patent/KR20050032106A/ko not_active Application Discontinuation
- 2003-06-18 JP JP2004526001A patent/JP2005535062A/ja not_active Withdrawn
- 2003-06-18 AU AU2003256278A patent/AU2003256278A1/en not_active Abandoned
- 2003-06-18 EP EP03766821A patent/EP1552528A4/en not_active Withdrawn
- 2003-06-18 CA CA002494075A patent/CA2494075A1/en not_active Abandoned
- 2003-06-18 CN CNA038184605A patent/CN1672216A/zh active Pending
- 2003-07-22 TW TW092119928A patent/TWI227895B/zh not_active IP Right Cessation
-
2005
- 2005-03-02 NO NO20051122A patent/NO20051122L/no not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
TW200403683A (en) | 2004-03-01 |
US6618297B1 (en) | 2003-09-09 |
TWI227895B (en) | 2005-02-11 |
KR20050032106A (ko) | 2005-04-06 |
WO2004013863A1 (en) | 2004-02-12 |
JP2005535062A (ja) | 2005-11-17 |
EP1552528A4 (en) | 2006-08-09 |
EP1552528A1 (en) | 2005-07-13 |
CN1672216A (zh) | 2005-09-21 |
CA2494075A1 (en) | 2004-02-12 |
AU2003256278A1 (en) | 2004-02-23 |
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Legal Events
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FC2A | Withdrawal, rejection or dismissal of laid open patent application |