NO174077B - PROCEDURE AND AUDIO CHANNEL SYSTEM FOR AA OUTSIDE AN ANALOGY SIGNAL RESPONSIBLE FOR A SOUND WAVE FORM FROM A PERSONAL COMPUTER SYSTEM - Google Patents

Description

The invention relates to a method for outputting an analog signal corresponding to an audio waveform from a personal computer system, where the personal computer system includes a processor,

a system memory for storing data and an audio channel connected to a data bus, and an audio channel system for outputting an analog signal corresponding to an audio waveform in a personal computer system, wherein the personal computer system includes a processor,

a system memory for storing data and a data bus connected to the audio channel system.

US-PS 4,034,983 (Dash) discloses a video game computer circuit with audio and potentiometer interfaces. The circuits accordingly comprise an analog representation circuit for receiving input signals for a pair of lever controls, an interface circuit and an audio signal generator circuit for driving a speaker.

US-PS 4,445,187 (Best) shows a video game circuit with an audio dialog. A tape cartridge, unlike a disc, is connected to the circuit. Audio output circuitry is implemented.

US-PS 4 070 710 (Sukonick) shows a control and interface circuit for an input-output device (here a video display) and which uses data bus and address bus architecture.

Other circuits have come along and improved these circuits in one way or another.

An object of the present invention is to provide an input-output control circuit that can be included in a personal computer system and that is compatible with address bus and data bus architecture, as well as direct memory access (DMA) where priority is established for bus access.

Another purpose of the invention is to provide an input-output control circuit whose operating parameters can be changed by and from a system microprocessor and from memory via the bus architecture.

A further purpose of the invention is to package the various input-output port control and interface components according to size and power consumption.

The above-mentioned and other purposes of the present invention are provided with a method characterized by features appearing in claims 1-8 and an audio channel system characterized by features appearing in claims 9-16.

The purposes of this invention are realized in a purpose-built NMOS 48-pin chip which can be connected to the data bus architecture and the address bus architecture in a host computer system that uses direct memory access (DMA) to a very large extent.

Independent control and interface circuits are provided for the right and left audio channels respectively, an information storage medium such as a floppy disk, a communication port (UART) and up to four joystick or potentiometer ports.

Each independent control and interface circuit is fed with data

from a data bus connection according to instructions plas-

based on the data's destination.

A separate interrupt priority control and status circuit is dedicated for communication with a microprocessor in the host computer system. This microprocessor communication circuit is connected to the right and left audio channel circuits, the disk circuit and the UART circuit, respectively.

A separate logic circuit delivers DMA requests from the audio and disk circuits to the host system.

The invention will be better understood by reading the following detailed description of the preferred embodiment in conjunction with the accompanying drawing. Fig. 1 shows a block diagram of the chip for the in-out device circuit.

Fig. 2 shows a block diagram of the UART port control circuit.

Fig. 3 shows a block diagram of the plate gate control circuit.

Fig. 4 shows a detailed block diagram of the audio port control circuit. Fig. 5 shows a detailed block diagram of the potentiometer gate control circuit.

The present invention provides an improved input-output control circuit for use in a microprocessor-based personal computer system utilizing direct memory access (DMA) and incorporating address and data bus architecture. The invention provides control signal generation and interfaces for audio, disk, UART (Universal Asynchronous Receiver/Transmitter) control ports with the use of smaller chips and faster processing than is available in other input-output controllers. Queuing and priority access improve the bus architecture's performance cycle. The architecture reduces the wiring between and on the chips and thereby reduces noise interference.

Fig. 1 shows the circuits for the present input-output controller implemented on a single chip. An 8-bit wide register address (RGA) bus 11 provides an input to the chip through a first buffer 13. The buffer 13 places addresses on a continuation of the address bus 15. This continuation address bus 15 supplies 8-bit addresses to a register address decoder 17. The register address decoder 17 could be implemented on another circuit chip, but it is desirable to implement the register address decoder 17 on the same chip in order to cut down on the wiring and the noise recording on the line. The data is received in the chip through a 16-bit wide data bus 19. A buffer register 21 in the chip sends/receives the data and connects the bus 19 with a continuation data bus 23.

The invention is designed to work with a variety of 16-bit/32-bit microprocessor systems, including a personal computer system that uses a Motorola 68000 microprocessor as its CPU. The system shown in two concurrent applications, entitled "Video Game and Personal Computer", serial no. 756,910, filed July 19, 1985 and "Display Generator Circuitry for Personal Computer System",

applied for on 18 July 1986, serial no. 886796, is such a system. Reference must be made to these applications.

The chip includes interrupt status registers 25 connected to receive external interrupt input lines 25a, such as would be provided by other I/O devices in the system. The interrupt status registers 25 are connected to receive and send data to the data bus 23. The status registers 25 feed interrupt control and priority logic 27 which outputs interrupt code signals which are routed from the chip to the 68000 microprocessor.

A number of data registers 29, 31 are connected to receive data from the data bus 23. The data registers 29 are connected to control circuits for the left audio channel, while the data registers 31 are connected to the control circuit for the right audio channel. Each of the data registers 29, 31 transmits its data to a series of audio control counters and registers 33 and 35, which in turn each drive a single one of the digital-to-analog (D/A) converters 37, 39, of which there are four in total of. The D/A converters 37 are connected to the output port 41 for the left audio channel, while the D/A converters 39 are connected to the output port 43 for the right audio channel. Each of the audio control counter and register circuits 33 and 35 generate interrupt signals on lines 24, which are connected in the interrupt status registers 25. The D/A converter circuits 37 and 39 are constructed according to the prior art. Each of the audio control counter and register circuits 33,

35 also provides a direct memory access request via respective lines 45, 47 to a DMA request logic multiplexer (serializer) circuit 49. This DMA request logic circuit 49 provides an external DMA request signal on line 51 for direct memory access to system memory for additional data - or instruction words. Lines 45, 47 carry operating time strobe decoding signals

as DMA access requests on the DMA request logic circuit 49.

While the left and right audio channel circuits are each represented as a single channel in FIG. 1, they in reality comprise two channels which are each mixed at the gate, as will be further discussed below.

The plate controller comprises data registers 53 connected to receive data and also feed data to the data bus 23. The data registers 53 transfer data with a plate control logic circuit 55. The plate control logic 55 is connected to a precompensator circuit 57 to

send signals to a disc port 61 via a connection line 59. Information received in the disc port 61 is transmitted via the line 63

to a data separator circuit 65, which in turn is connected to the disk control logic 55. DMA access request lines 67 connect the disk control logic circuit 55 to the DMA request logic circuit 49. The disk control logic 55 also has interrupt signal lines 24 connected to the interrupt status registers 25.

The UART port 69 receives data via a line 71 from a transmit buffer circuit 73. The UART port 69 provides data to a receive buffer circuit 77

via the line 75. The transmit buffer 73 and the receive buffer 77 are connected by a UART control logic circuit 79. The UART control logic circuit 79

has interrupt signal connections 24 with the interrupt status registers 25. The UART control logic circuit 79 also receives data from and sends data to the data registers 81. The data registers 81 provide two-way access with the data bus 23.

Four control (potentiometer) gates 83 a, b, c, d are connected via lines 85, 87, 89 and 91 to a bidirectional buffer and latch circuit 93. The buffer and latch circuit 93 is operated under the control of the potentiometer control and counter circuit 95, which is connected to the data bus 23 through data registers 97. The data registers 97 transfer data with the data bus 23.

The register address decoder 17 receives via the address bus 15 addresses generated by the microprocessor or by a register address encoder on an address generator chip. As a function of the received address, the decoder 17 provides an exclusive receive open signal on one of the lines 99 to one of the registers 25, 29, 31, 53, 81 or 97 to cause the register to receive (load) or transmit (unload) data from or to the data bus 23, and thereby controls which register is connected to the data bus 23 at a given time.

The UART control circuitry (Fig. 2) operating in conjunction with port 69 transfers serial data via line 71 from transmit buffer 73 to port 69, and transfers data in serial form received at port 69 to receive buffer 77 via line 75. Each buffer 73,77 is operated to load or unload information under the control of clock pulses. The control register 81 and the data send buffer register 73 receive parallel data from the data bus 23, while the receive buffer register 77 sends parallel data to the bus 23.

The control logic 79 comprises a first down counter 101 which forms first clock time pulses on line 103 and which is used to control the transfer of information into and out of the receive buffer register 77. Another down counter 105 is loaded from the control logic 79, which drives the send buffer register 73 on another and different time from the receive buffer register 77. The control circuit 79 may be implemented as a general logic arithmetic unit and is driven by an input on line 109 from the system clock of the host computer system. Control logic circuit 79 also supplies interrupt signals on line 24.

The UART port 63 is a universal receive and transmit port of the type commonly known in the industry as an "RS232" port. A system control signal puts the circuit in either "read mode", i.e. receive, or "write mode", i.e. transmit. The UART port 69 circuit usually does not time-share receive and transmit functions. The circuit alternatively controls the receive function or the transmit function, which is intermittent, as the data rate is considerably lower than the system processing rate.

The plate port 61 supplies serial data transferred from the precompensator circuit 57 (Fig. 3) via line 59. Serial data is input from the plate port 61 via line 63 to the data separator circuit 65. The system clock on line 109 is applied to the plate control logic circuit

55 to control its operation as well as the pre-compensator circuit 57 and the data separator circuit 65. The data separator circuit 65 feeds a sense pulse on the line 111 to an input data shift register 113 to control the transfer of data through the data shift register 113.

Data is fed serially via line 115 from data separator 65 to data register 113. Data register 113 then transfers data to data bus 23 in parallel format through a first-in, first-out buffer 120 which is three 16-bit registers deep. The FIFO buffer 120 is controlled by an enable signal line 99. A location register 116 is loaded from the data bus 23 under the control of an enable line 99. This register 116 is 16 bits wide and holds a comparison value which is input to the comparator 114 to be compared with the value in the data register 113. The output of the comparator 114 is a sync signal on line 112 to the control logic 55 to provide the word count control signal output on line 121.

Another data shift register 117 receives data on the data bus 23 in 16-bit parallel transfers through a three 16-bit register deep FIFO buffer 122 which is controlled by an enable signal 99. A down counter 119 loaded from the control register 53 provides a control instruction to the disk control logic circuit 55 which in turn supplies a control function via line 121 to data shift registers 117 to control the word count transfer of information through data shift register 113, shift register 117 and FIFO buffers 120, 122. Shift register 117 supplies serial data on line 123 to precompensator circuit 57. A precompensator circuit decodes the differences between successive bits of data as "zeros" or "ones" and introduces a phase shift to compensate for bit migration on the magnetic medium caused by the differences between magnetic attraction and repulsion of "zeros" and "ones". The pre-compensator circuit 57 provides a delay or acceleration of 0, 140 ns, 280 ns or 1560 ns to individual pulses delivered to the disc port 61 to compensate for site migration on the disc media. The register 117 receives sense pulses on the line 111 from the separator 65 which controls the transfer rate of the register 117.

The control register 53 receives data from the data bus 2 3 in 16-bit parallel transfers and in the same way transfers the information to the disk control logic circuit 55 under the control of an activation signal on line 99 from the register address decoder 17. The disk control logic circuit 55 supplies, as previously discussed, two interrupt status signals on the lines 24 to the interrupt status registers 25 and three DMA request signals on lines 67 to DMA request logic circuit 49.

The pre-compensator 57, the shift register 117 and the buffer 122 are used when information is written on a disk through the gate 61. The data separator 65, the data shift register 113 and the buffer 120 are used when information is read from a disk. Mente pulses on the lines 111, generated by the separator 65, are used during both the read and write operations.

The data separator circuit 65 operates in a complementary manner to the pre-compensator circuit 57 discussed above. This data separator sets up electronic inspection times for data received as a function of the ideal data rate. An inspection time period is called a "window", as it is the time during which the circuit "looks" for a data bit that can be expected to be entered. Due to irregularities in the disk drives and data transmission and magnetic migration, i.e. "bit migration" on floppy disks, the data separator circuit is required to follow input data by shifting the window to compensate for frequency and phase errors in the arrival time of the data. A data input (separator) circuit is shown in US-PS No. 4,780,844 entitled "Data Input Circuit with Digital Phase locked loop", to which reference should be made.

The audio control circuits (Fig. 4) are duplicated to generate left-side audio signals to port 41 and right-side audio signals to port 43. The audio circuit on each side is made with two channels, an A-channel and a B-channel, which contain identical circuits.

The A channel for the left audio port 41 comprises three sound control registers, register 126a for signal period, register 126b for duration and register 126c for volume. The "period" data register 126a, the "length" data register 126b and the "volume" data register 126c each receive data from the data bus 23 under the control of individual enable lines 99 and transfer data to the "period", "length" and "volume" control counters 127a, 127b and 127c. Period data contained in register 126a is tone frequency data, i.e. the frequency of the generated sound ("tone"). Length data contained in register 126b is the duration of the tone. Volume data is the amplitude of the "tone". This data is fed to control counters 127a, b, c which supply signals via the lines 130a, b, c to the control logic 129. The load signal lines 132a, b, c control the loading of data to one of the control counters 127a, b, c. The count signal lines 134a, b,

c controls the serial reading of data in each control counter 127a, b, c.

The control logic 129 has an output control line 140 to the audio data register 125. This audio data register stores the data that defines the character of the music. For example, the system may be programmed to produce a small "c". The data defining this tone is contained in register 125. This register is then controlled by logic 129 to modify the period, length and volume of the tone.

The control logic circuit 129 receives the output 130a from the "period" control counter 127a, the output 130b from the "length" control counter 127b, and the output 130c from the "volume" control counter 127c, and provides load control signals on lines 132a, 132b, 132c and count control signals on lines 134a, 134b, 134c to the respective counters 127a, 127b, 127c. The control logic 129 provides an interrupt output on line 24 to the status registers 25, and a DMA request output on line 45 to the DMA request logic multiplexer 49 (parallel-to-serial). The operation of the control logic 129 is clocked by system clock signals on line 109. The control logic circuit 129 can be implemented as a general logic arithmetic unit or by an instruction decoder logic circuit. The control logic 129 can also be implemented with a logic matrix network implemented in NOG gates.

The buffer register 29 is loaded with data from data bus 23 under the control of an activation line 99. The buffer register 29 outputs data to an audio data register 125 under the control of line 140 from the control logic 129. The information in the audio data register 125 is then delivered to a digital/analog converter 139. The control logic provides a control line 135 to this D/A converter 139. The analog output of the D/A converter 139 is the left audio channel A signal and connected to the left audio port 41. These circuits are duplicated to form the left audio channel circuit 141. The output of the B- channel circuit 141 is similarly connected to port 41 so that the two audio signals are mixed.

Duplicated circuits 143, 145 are used for the right audio A and B channels respectively. The output lines from these circuits 143,

145 is likewise formed by a common connection to the right audio port 43. Each of the circuits 141, 143, 145 has DMA request output lines 45 and interrupt signal lines 24 as outputs.

The control (potentiometer) gate control circuits 93, 95 and 97 of Fig. 1 with their connections 85, 87, 89 and 91 to the potentiometer gates 83a, 83b, 83c and 83d can be implemented as shown in Fig. 5. Each of the four potentiometer ports 83a, 83b, 83c and 83d are identified by dash-dotted lines. The two-way lines 85, 87, 89 and 91 comprise the pairs 85a-85b, 87a-87b, 89a-89b and 91a-91b, as shown in fig. 5. Lines 85a, 87a, 89a and 91a are signal level lines connected to ternary drivers 149a, b, c, d. Lines 85b, 87b, 89b and 91b are connected to a +5V DC voltage reference. A joystick circuit is shown in the potentiometer gate block 83a, 83b, 83c and 83d. Each control lever circuit comprises a variable 470 kohm resistor 147a, 147b, 147c and 147d and 47 micro-farad capacitors 151a, 151b, 151c and 151d connected to ground. The resistor and capacitor provide an RC time constant that is adjustable with the adjustment of the variable resistor.

A control register 154 is loaded from data bus 23 under the control of an enable signal on line 99. This control register feeds two different control bits on lines 161 to each of the four dedicated ternary drivers for potentiometer gates 83a, 83b, 83c and 83d. Bits No. 15 and 14 from control register 154 are output via lines 161a to first ternary driver circuit 149a. Bits Nos. 13 and 12 from register 154 are output via lines 161b to another ternary driver circuit 149b, bits Nos. 11 and 10 from register 154 are output via lines 161c to a third ternary driver 149c, and bits Nos. 9 and 8 from register 154 is output via lines 161d to a fourth ternary driver circuit 149d. Each ternary driver circuit is a differential line driver with ternary outputs. Such circuits have for several years been supplied by a number of manufacturers, including Texas Instruments, Inc. These drivers can provide +5V DC, 0V DC and an intermediate voltage output.

A control counter circuit 157 is clocked by the horizontal sync pulse to the system video on line 156, which provides the line scan sample rate for the video display of the control counter 157. Bit No. 0 from control register 154 is output as reset control 163 for counter 157. Control register 154 instructs each of the ternary drivers 149a, 149b, 149c and 149d to switch their state to 0V to drive down the signal on their respective potentiometer gates 83a, 83b, 83c and 83d and when to switch their state to allow the signal level to start rising. The RC time constant of the individual joystick will determine the rise time.

Individual control switches 158a, 158b, 159c and 158d monitor each of the lines 85a, 87a, 89a and 91a, respectively. When a preset level is sensed, each control switch supplies a control signal 150a, 150b, 150c and 150d to the latch registers 153a, b, c, d. The output of the control counter 157 is simultaneously fed as data to the latch registers 153a, 153b, 153c and 153d, which are assigned to each of the potentiometer gates 83a, 83b, 83c and 83d.

When a control signal 150 is received by a latch register 153, the respective register is loaded with the instantaneous value in the control counter 157. In this way, the analog position of each joystick's variable resistance 147a, 147b, 147c and 147d can be determined and digitized into a (digital ) value stored in registers 153a, 153b,

153c and 153d. The position of a joystick is translated into a signal value that operates the control switch 2158. A control switch

158 then sets a latch register 153 to enable the value contained in the free-running control counter 157 for transfer to the latch register. In this way, the analog position of each joystick is translated into a digital value that can be loaded into the data bus 23.

Claims (16)

1. Method of outputting an analog signal corresponding to an audio waveform from a personal computer system, wherein the personal computer system includes a processor, a system memory for storing data and an audio channel connected to a data bus, wherein the method is characterized in that the audio channel performs the following steps: storing audio period data in a period register connected to the data bus in response to a first opening signal, storing the audio period data as a period count in a period counter connected to the period register in response to a period load signal from a control circuit connected to the period counter, to change the period count in the period counter in response to a period count control signal from the control circuit, to provide an audio data control signal from the control circuit to an audio data register at a frequency determined by the period count, to store audio length data in a length register connected to the data bus in response to another opening signal, to store the audio length data as a length count in the length counter connected to the length register and to the control circuit in response to a length load signal from the control circuit, to change the length count in the length counter in response to a length count control signal from the control circuit, to obtaining either an interrupt request or direct memory access request (DMA request) from the control circuit to place audio data stored in the system memory on the data bus, the audio data corresponding to the audio waveform, storing the audio data corresponding to the audio waveform in the audio data register in response to the audio data control signal, converting the audio data corresponding to the audio waveform to an analog signal in a D/A converter connected to the audio data register, and outputting the analog signal corresponding to the audio waveform from the D/A converter to an audio port. 2. Method according to claim 1, characterized in that it comprises storing audio volume data in a volume register connected to the data bus and the control circuit in response to a third opening signal, and obtaining a converter control signal from the control circuit to the D/A converter in response to the audio volume data to control the amplitude of the analog signal. 3. Method according to claim 2, where the personal computer system includes a number of audio channels connected to a data bus, characterized in that the method comprises to output a series of analog signals corresponding to a series of audio waveforms from a series of D/A converters, to the audio port. 4. Method according to claim 3, where the audio channels include a first audio channel and a second audio channel, characterized in that the method comprises issuing a first analog signal corresponding to a first audio waveform from the first audio channel, to a first audio port, and output another analog signal corresponding to another audio waveform from the other audio channel, to another audio port. 5. Method according to claim 3, characterized in that it includes mixing the analogue signals for delivery to the audio port. 6. Method according to claim 1, where the personal computer system includes a number of audio channels connected to a data bus, characterized in that the method comprises outputting a number of analog signals corresponding to a number of audio waveforms from a number of D/A converters, to the audio port. 7. Method according to claim 6, where the audio channel includes a first audio channel and a second audio channel, characterized in that the method includes outputting a first analog signal corresponding to a first audio waveform from the first audio channel to a first audio port, and outputting another analog signal corresponding to another audio waveform from the other audio channel to another audio port. 8. Method according to claim 6, characterized in that it comprises mixing the analogue signals for delivery to the audio port. 9. Audio channel system for outputting an analog signal corresponding to an audio waveform in a personal computer system, wherein the personal computer system includes a processor, a system memory for storing data and a data bus connected to the audio channel system, characterized in that the audio channel system comprises: a period data storage device (126a) connected to the data bus to store audio period data in response to a first opening signal, a period counter device (127a) connected to the period data storage device (126a) to store a period count, a device connected to the period counter device ( 127a) and adapted to respond to a clock signal and the period count to change the period count by providing a period load signal and a period count control signal to the period counter device (127a), an audio data control device (129) coupled to the period counter device (127a) to provide an audio data control signal at a frequency determined by the period count, a length data storage device (126b) connected to the data bus to store audio length data in response to another opening signal, a length counter device (127b) connected to the length data storage device (126b) to store a length count, a device connected to the length counter device (127b) and adapted to respond to a clock signal and the length count to change the length count and provide a length load signal and a length count control signal to the length counter device (127b), either an interrupt request device or direct memory access request device (DMA device) coupled to the period counter device (127a) and the length counter device (127b) to obtain an interrupt request to place audio data stored in the system memory on the data bus by means of the processor, the audio data corresponding to the audio waveform, an audio data storage device (125) connected to the audio data control device (129) to store audio data corresponding to the other audio waveform in response to the audio data control signal, a D/A converter device (139) coupled to the audio data storage device (125) for converting audio data corresponding to another waveform into an analog signal, and a device for outputting analog signals corresponding to the audio wave -form from the D/A converter device, to an audio port. 10. Audio channel system according to claim 9, characterized in that it comprises: a volume data storage device (126c) connected to the data bus to store audio volume data in response to a third opening signal, and a volume control device (127c) connected to the volume data storage device (126c) to provide a converter control signal to the D/A converter device (139) to control the amplitude of the analog signal. 11. Audio channel system according to claim 10, characterized in that it comprises a number of audio channels to output a number of analogue signals corresponding to a number of sound waveforms to the audio port. 12. Audio channel system according to claim 11, characterized in that it comprises a first audio channel for outputting a first analog signal corresponding to the first audio waveform, to a first audio port, and another audio channel for outputting another analog signal corresponding to another audio waveform , to another audio port. 13. Audio channel system according to claim 11, characterized in that it comprises a device for mixing the analogue signals for delivery to the audio port. 14. Audio channel system according to claim 9, characterized in that it comprises a number of audio channels to output a number of analogue signals corresponding to a number of sound waveforms, to the audio port. 15. Audio channel system according to claim 14, characterized in that it comprises a first audio channel for outputting a first analog signal corresponding to a first audio waveform, to a first audio port, and another audio channel for outputting another analog signal corresponding to another audio waveform , to another audio port. 16. Audio channel system according to claim 14, characterized in that it comprises a device for mixing the analogue signals for delivery to the audio port.