NL8203050A - SYSTEM FOR RECORDING AND / OR DISPLAYING ANALOGUE SIGNALS IN DIGITAL FORM. - Google Patents

Description

i. j - 1 - t

System for recording and / or reproducing digitized analog signals.

The invention relates to a system for recording and / or reproducing analog signals brought into digital voim.

For the purpose of hi-fi sound recording 5, many attempts have already been made to record a digitalized audio signal. A particular solution involves the sampling of the audio signal at a frequency of 47.25 kHz and the quantization of the sampled value into a digital code and the organization of the data bits of the PCM signal into a series of frame- signals each containing digital words for synchronization, information and error detection and correction. The frame signal is usually converted into an NRZ (non-back-to-zero) signal with 'rr: minimum time' 'space between pulses typically' 325 nanoseconds, 15 and with a frequency spectrum from zero to 6, 14 MHz, while it is frequency modulated prior to registration.

On the other hand, attempts have also been made to use groove-less record plates, such as capacitance detection plates and laser beam plates, in which tracking signals were recorded on guide tracks parallel to information tracks. In this case, the main concern is that no interference occurs between the tracking signals and the information signals. Furthermore, since the NRZ signal assumes "1" bits to regenerate clock pulses, the recorded signal must sufficiently contain a clock component to prevent display or reception. The system becomes synchronized.

To meet these requirements, a known solution involves the MEM-EM method in which the signal 30 is first subjected to "modified frequency modulation" 8203050 * *.

- 2 - and then to frequency modulation. Although the MEM-EM method satisfies compliance with the requirement to crater regenerate the kldk, the MEM-EM signal has a wide frequency band and in particular disturbs its energy at the low end of the frequency spectrum the tracking signals.

The object of the invention is therefore to provide a digital recording and / or reproducing system in which the recorded signal contains a sufficient degree of clock components, to provide insurance against the loss of clock pulses and to increase the bandwidth. . The invention is particularly advantageous for groove-free registration in plates.

According to the invention, an analog signal / either an audio signal or a video signal with respect to a still picture is sampled and quantized into a digital signal. The digital signal is organized into a redes frame signals containing all digital words in terms of information and frame synchronization. The recording system of the invention includes a means for generating a digital warp word with a fcwasi random bit pattern for each of the frame signals at the termination of the fine sync word, and for the liver and a modulo-2. addition of the warp word to the info word to give each frame signal a random character. After the twisting process, the signal is presented to a frequency modulator and recorded in a recording medium.

Preferably, the quasi-random bit pattern is a pulse train of a maximum long sequence - since it has equal chances for the occurrence of "1" and "0" bits. The data bits that are rotated with the maximum long sequence is less likely to generate a sequence of O'Lbits.

8203050 Λ. * '- 3 ->

The energy of the twisted, frequency-modulated NRZ signal is mainly in a frequency range in the middle of the spectrum, so that the tracking signals are made distinguishable from the information signal.

5 ;; The invention also provides a digital display system for reproducing the twisted data. The display system includes a frequency demodulator to derode the frequency signal from that frequency. the recording medium has been detected to recover the randomly acquired frame signal. Clock pulses are regenerated from the recovered frame signal.

The frame sync word is detected from the recovered frame signal and checked against the regenerated clock pulse to detect phase equality between them. A data rectifier is provided to generate a digital rectifier word of the same bit pattern as the warp word for each of the recovered frame signals. The rectifier is arranged to be started in response to the detected phase equality in order to start generating the rectifier word in order to effect a modulo-2 addition of the rectifier word to the information word with v-the random character. in order to derive the original information word.

The invention would now be described in details with reference to the accompanying drawing, in which:

Pig. 1 is a schematic representation of a block diagram of the digital recording system according to the invention? FIG. 2 is a representation of the format of a frame signal;

Fig. 3 is a representation of lifting details of the data shifter preferred in FIG. 1;

Fig. 4 represents a time sequence diagram connected to the data shifter; 8203050 τ * δ - 4 -

Fig. 5 is a graph of the energy distribution of the twisted, frequency-modulated NRZ signal compared to a frequency-modulated NRZ-MEM signal; FIG. 6 shows a diagram of a digital display system according to the invention;

Fig. 7 is a representation of a time / sequence diagram connected to the display system of FIG. 6; FIG. 8 is a representation of a first embodiment of the data rectifier of FIG. 6;

Fig. 9 depicts a time sequence diagram associated with the rectifier;

Fig. 10 is a representation of a second exemplary embodiment of the rectifier;

Fig. 11 is a time sequence / diagram associated with the exemplary embodiment of FIG. 10; and

Fig. 12 is a representation of a 20 variant of the corrector.

Fig. 1 shows a digital recording system as an exemplary embodiment of the invention. For purposes of description, the system is arranged to record audio signals in four channels along a spiral track on a groove-free capacitance plate with tracking signals of different frequencies along adjacent conductor tracks of a partially spiral configuration which intervals of 360 ° by a track-led switching signal is divided. The audio signals input to clerms 1 to 4 were applied to PCM encoders 5-8 in which each signal is sampled at 47.25 kHz and squared to a 16-bit stream and fed to a known time division / multiplexer 9. The multiplexer includes a 23-bit CRCC (cyclic redundancy 8203050 ir-5 * control code) generator and 16-bit P and Q parity generators for bit error detection and correction, as well as a 1-bit address generator. Between these redundant bits, the time division multiplexed data was shifted and fed to a frame synthesizer 10 in which the input data was further interleaved with a 10-bit frame sync code supplied from a sync generator 11, and divided into blocks or "frames" of 130 bits each as shown in FIG. The P and Q parity bits were generated in a known manner by Madulo-2 addition of data words in a channel. The cyclic redundancy check code is a remainder that is also obtained by dividing each data and parity λλ r * word by a generator polynoam x + xD + x4 + x + 1 known by itself. The signal from the time division multiplexer 159 is an NRZ signal which is transmitted at a rate of 6.14 Mb / s.

According to the invention, a data shifter 12 is connected to / output from the frame synthesizer 10 which gives the data parity words an accidental character, 20 or "twists" according to a generator polynoan 7 4 x + x + 1 As shown in Figure 3, the data shifter 12 includes a pulse generator for quasi-random pulses or a pulse generator 20 for maximum length sequences formed by a first group of cascaded 25 D flip-flops 20 to 20 ^, a second group of cascaded D flip-flops 20 ^ through 20 ^ and an EX - CF port 21 connected between the first group of flip-flops and the second. -stage shift register in which m satisfies a formula N £ 2111-1 (where N is a number of 30 bits of each frame less the number of frame sync bits, i.e. 120 bits) Of the flip-flops of the first group, the D input leads are connected to the Q output of the previous flip-flop s, with the exception of flip-flop 20 ^, the D input terminal of which is connected to the output 35 of the flip-flop 20 ^ of the second group. From the EX-OR gate 8203050

a

- 6 - 21, one input is connected to the Q output of the flip-flop 20 ^, and the other input is connected to the output of the flip-flop 20 ·. The output of the EX-OR gate 21 is connected to the D input of the flip-flop 20, which in turn applies its output signal to the D input of the flip-flop 20g, to the output of which the D input of the flip-flop 20 ^ is connected. From the flip-flops 20 to 20, the clock input is jointly connected to a clock generator 12a and the preset inputs are jointly connected to a timing circuit 12b that generates a timing signal in response to a frame sync generated by the sync generator 11. The data fader 12 further includes an EX-OR gate 22, one input of which is connected to the output of the frame synthesizer 10 and another input of which is connected to the output of the flip-15 flop 20 ?.

The shape of the timing signal generated by the timing circuit 12b is shown at 41 in Fig. 4. This timing signal pulls the flip-flops 20 ^ to 20 ^ to a logic "1" state. Following this bias action, flip-flops 20 ^ to 20 ^ are clocked simultaneously and periodically in response to clock pulses 42 supplied from clock 12a, so as to generate a quasi-random code word with a sequence of maximum length, as indicated at 43 in Fig. 4 and in accordance with the above-mentioned generator polynoora. The quasi 'random codeword thus generated is modulo-2 emblazoned into EX-QF pool 22 with the data and parity words of each frame, indicated at 44 in Fig. 4, so that the data and parity words are rotated , or in other words, get a random character. The result of the Modulo-2 addition is indicated at 45 and is obtained at an output terminal 23. Since the quasi: - random codeword has an approximately equal chance of a "1" as of a "0" occurring. has a very small chance of a sequence of "0" bits occurring in the stream of twisted data 35 *> 8203050 - 7 - This makes a display system less dependent on the content of the received NRZ signal when regeneration of clock pulses.

The output signal of the data 5 rotator 12 is applied to a frequency modulator 13 and applied to a mixer 14 in which it is combined with a switch-off signal fp3 applied to a terminal 15. The mixing stage 14 of the combined signal is applied to a known recording device 16. The device 16 modulates the strength of a laser beam with the input signal and directs the modulated beam qp the surface of a light-sensitive layer which is applied to a revolving master recording plate 19 can form a series of small wells therein along a spiral track. From input 15 clerans 17 and 18, tracking signals fpl and fp2 of the different frequencies were applied to the recording device 16. These tracking signals were both used to modulate the strength of an associated laser beam to form guides / tracks in addition to the information. track.

As shown in Fig. 5, the tracking signals fp1 and fp2 and the turn-on signal fp3 thus recorded in the plate 19 are in a frequency range between 100 kHz and 1 MHz. Krone A in Fig. 5 is a representation of the energy distribution of a conventional frequency modulated MPM-NRZ signal. The map B shows the energy distribution of the frequency-modulated, twisted NRZ signal according to the invention. Ddca: Comparison between the two crests shows that the energy of the frequency-modulated, twisted NRZ signal is concentrated in the center of the frequency spectrum and thus that the signal to noise ratio of the track control signals fpl, fp2 and fp3 is improved.

After the description of the recording system, there now follows a description of a display system according to the invention, with reference to Fig. 6. The 8203050 - 8 display system comprises a detector 25 with a capacity detection needle resting on several tracks of a record carrier to record 24 cm information signals and tracking signals in a manner known per se. The detected information signal is presented to a frequency demodulator 26 and hence to a level detector 27 in which the signal level of the demodulated signal is accurately defined for recovering the twisted data. A flank detector 28 is connected to the output of detector 27 cm in response to IQ to generate a narrow pulse 52 of each of the leading and trailing edges of the twisted pulses 51 shown in FIG.

The pulses 52 are applied from the edge detector 28 to a tank circuit 29 cm to generate a sinusoidal signal 53 which is then applied to a phase-locked loop 25 (PEL) 30 which allows for small frequency deviations and dropped pulses to be offset and the sine-shaped signal is converted into clock pulses as indicated at 54. The digital pulses 51 from the detector 27 are also applied to the D input of a flip-flop 31, the clock input of which is supplied with pulses from the PEL 30. The D input is thus coupled to the binary level of the input pulses 51 in response to the clock pulses 54, generating pulses as indicated at 55 in Fig. 7.

The output of the D flip-flop 31 is connected to a data rectifier 32. A sync detection and protection circuit 33 is connected to the data rectifier 32 and an error detection and correction circuit 34 is connected to the sync detection and protection circuit to detect 33 cm errors in the data words of each frame signal using the cyclic redundancy check code and to correct such detected errors using the P and Q parity words, everything in a known manner.

An example of the rectifier 32 is shown in FIG. 8. The rectifier 32 of FIG. 8 is of 8203050-9 - a feedback-controlled type and includes a generator 70 for quasi-accidental pulses of the same construction as the generator 20 being heated. used in twisting the recorded data. The pulse generator 70 includes a first group 5 of cascaded D-flip-flops 70 to 704, and a second group of cascaded D-flip -flops 705 to 70 ^, as well as an EX-OR gate 134, one input of which is excluded at the output of the flip-flop 70 ^ and a second input at the output of flip-flop 70 ^ am at the D input of 10 flip-flop 70 ^ to provide an output signal. This generator generates a pulse train with a sequence of maximum 7 4 length according to the generator polynomial X + X + 1, as in the twister 12, and supplies its output signal via an AND gate 135 to an input of an EX-OR gate 130 to which the signal 15 from the D flip-flop 31 is presented.

The sync detection and protection circuit 33 includes a sync detector 131 and a sync protection circuit 132. The sync detector 131 consists of a shift register 139 which is clocked by the output of the phase locked loop 20 PIIi 30 and an AND gate. 140 connected to the flip-flop stages of the shift register 139 so that when a frame sync codeword "1010111000" is input to the shift register 139, the AND gate 140 provides a coincidence output. The data recorded in the shift register 139 is clocked in serial form to a shift register 136 which is coupled in parallel with a data register 137.

The sync protection circuit 132 counts a counter 141 arranged to be reset in response to the sync pulse from the AND gate counting 140 cm clock pulses from the phase locked loop (PEL) 30. When counting a 120th pulse, the counter 141 provides a reset pulse for a flip-flop 144, and when counting a 130th pulse, the counter 141 supplies a pulse to an AND gate 142 to which the sync pulse from the AND- port 140 is also offered.

8203050 I '- 10 -

The output of AND gate 142 is connected on the one hand to the adjusting input of flip-flop 144 and on the other hand to an 8-bit shift register 145 whose internal stages are connected to a GF gate 147. The output of flip-flop 144 is on-5 connected to the preset inputs of the flip-flops 70 ^ to ΊΟη, and the output of the OR gate 147 is connected to the s. AND gate 135. With reference to the signal shapes shown in FIG. 9, operation of the rectifier 32 will now be described. In Fig. 9, at 81, the shape of an input-10 signal for the rectifier 32 is indicated. On receipt of a 10-bit frame sync, a pulse 82 is generated at the output of AND gate 140 and sets the counter 141 back. The counter 141 begins to count clock pulses that occur after the detection of the 10-bit sync code, and since the frame contains 130 bits, the counter 141 supplies an output pulse 83 at the end of each frame to a latch input of the data register 137 and at the same time at the reset input of flip-flop 144.

The counter 141 further supplies an output pulse 84 to the AND gate 142 upon counting a 130th clock pulse which equals about 20 with the end of each frame sync code. If the sync code occurs at the correct time, AND gate 142 supplies a coexistence output signal to shift register 145 and flip-flop 144 so that the latter is in a reset state during the period of frame sync and in a set state for the remainder of the frame period, as indicated at 85 in FIG. 9.

Thus, flip-flops 701 through 70y were reset during the sync period and cleared for the remainder of the frame period to generate a straighten code.

30 The straighten code contains the same bit pattern as the twist code bit pattern, and each bit of the straighten code is generated in response to the clock pulses delivered from the phase-locked loop (ELL) 30.

The coincidence output from 8203050-11 - AND gate 142 is shifted into 8-bit shift register 145 in response to each frame clock signal obtained from the output of counter 141 at the 130th count. If frame synchronization is determined for at least 1 frame interval, the shift register 145 is filled with 1 bit and the QF gate 147 supplies an output to the AND gate 135. At the same time, the flip-flop 144 is pulled into the adjusting state to reset the timing of the quasic random pulse generator 70. The straighten code is thus passed through AND gate 135 to EX-OR gate 130 in which it is calibrated by modulo-2 addition with the twisted data. The rectified data bits were clocked out from the shift register 136 to an external utilization circuit not shown and also parallel to the data register 137. The data recorded in the register 137 were transferred to the error detection and correction circuit 33 to describe error detection and correction as described above.

When the device 20 is turned on or failure occurs which can continue for at least an 8-frame interval, the system will become out of sync and phase out the clock timing from the output pulse of the sync detector 131 and enter. the AND gate 142 phase inequality qp..The shift register 145 is emptied and an output logic or block signal representing a logic "0" is presented to the AND gate 135. The rectify code also goes out of phase with respect to the input data applied to the EX-OR gate 130, and is blocked in response to the blocking signal applied to the AND gate 135. The blocking signal at the AND gate 135 applies a logic "0" to the EX-OR gate 130 cm to allow the input data to pass therethrough. When a phase-equality occurs in AND gate 142, flip-flop 144 is reset thereby correcting pulse generator 70 8203050 - 12 cm and AND gate 135 cm is cleared to pass the correction code to the EX-OR gate 130 cm to resume straightening.

A second exemplary embodiment of the data rectifier is shown in FIG. 10 in which the output of EX-QF gate 139 is connected to the shift register 136 to obtain a forward operation seen from the power supply and in which the same reference characters are provided. · Uses to indicate parts which are indicated by 10 parts as shown in fig. 8. The sync protection circuit 232 includes a counter 241 which provides an output with each count of 130 clock pulses to an AND gate 142 to which the sync detection signal 82 from the AND gate 140 is applied. The co-incidence output of AND gate 142 is applied to an 8-bit shift register 245 whose counter / stages are connected to an AND gate 247 instead of the OR gate 147. A counter 248 and a flip-flop 244 are provided. Counter 248 is reset in response to an output from the AND gate to count 247 cm clock pulses from the PEL 30 cm to generate a first pulse when counting a 130th clock pulse corresponding to the start of the data word to set the flip-flop 244, and a second pulse to count a 120th clock pulse corresponding to the end of the frame, to reset the flip-flop 244 by 25 cm. The output of the flip-flop 244 is applied to the preset terminals of the flip-flops 70 to 70y. The output of the flip-flop 10η is directly connected to the EX-OR gate 130. The data register 137 is reset in response to the output signal from the counter 248 at the 120th count.

The operation of the exemplary embodiment of FIG. 10 will now be explained with reference to FIG. The system may be out of sync for a period of time t 1 to t 2 immediately after connection.

9 to 13 to the power supply, so that the sync detection pulses 82 are out of phase with respect to pulses 103 from the counter 248 corresponding to the beginning of each data word, as shown in FIG. 11. Therefore, the correction code word is .1.03 from phase 5 with respect to the coincidence pulse 100 during that interval.

In contrast, counter 241 is reset by sync detection pulse 82, and phase equation occurs in AND gate 242 in response to each frame sync signal, thus generating a pulse 100. In response to a pulse 100-1 from 10 poort gate 242 at time t2, the shift register 252 is completely filled with "1" and the AND gate 247 generates a reset pulse 101-1 cm to reset the counter 248 so that the pulses 102 go into phase with the pulses 100 and then the straighten codeword is generated in phase with just the correct timing.

Assuming that a failure occurs during a period t3 to t4, the pulses 100 cease to exist during this interval. In contrast, phase-locked loop PEL 30 continues in its locked state and counter 248 still generates pulses 103 in the correct timing, although reset pulses 101 are present. At time tt, which is after eight frames from time t4, shift register 145 is filled and counter 248 is reset to the correct time.

FIG. 12 is a variant of the rectifier of FIG. 10. Briefly, the rectifier of FIG. 12 is a combination of the embodiments of FIGS. 8 and 10 so that it includes an OR gate 147a connected to the counter stages of the shift register 30 to provide an output signal when the shift register 245 is emptied. The output from the OR gate 147a is applied to an input of an AND gate 135a to which the output of the flip-flop 70j is applied. Thus, the patented features of Figures 8 and 10 8203050 → 14 are obtained. If the out-of-sync state lasts for a period of eight frames, OR gate 147a blocks AND gate 135a to suspend rectification.

Straightening will be resumed in response to an output from OR gate 147a when the synchronization has lasted at least one frame time.

Other variants within the scope of the invention are apparent to those skilled in the art.

8203050

Claims (14)

1. Digital recording system, comprising a means for sampling an analog signal and Ret quantizing the sampled signal into a digital signal, a means for dividing the digital signal into a sequence of frame signals each of which are digital information words and a frame synchronizing word, a frequency raodulator for frequency modulating the frame signal, and a means for recording the frequency-modulated frame signals in a recording medium, characterized by a means (12) for generating a digital warp word consisting of a quasi-random bit pattern for each of the frame signals at the frame sync word completion, and providing a modulo-2 addition of the warp word at the information word to each frame signal to give a random character before frequency modulating the frame signal. 2. A system according to claim 1, 20 having the boulder mark, that the recorder comprises a circuit for recording tracking signals in the lower frequency region of the spectrum of the recorded signal. 3. A system according to claim 1, characterized in that the warp generating means cravat a generator of quasi-random pulses, as well as an EX-OR gate for providing a modulo-2 addition of the output signal. of this pulse generator and the information word. 30 System according to claim 3, with the characteristic 8203050 - 16, that the pulse generator is a pulse generator for drawing sequences of maximum length. System according to claim 4, characterized in that the pulse generator for drawing sequences of maximum length cravates a first group of cascaded flip-flops (20 ^ - 20 ^), a second group of cascade-switched flip-flops (20 ^ -20 ^), and an EX-OR gate (21), of which a first input is connected to the output of the first group of flip-flops, and a second input is connected to the output of the second group of flip-flops, the flip-flops of the first and second groups having a clock input connected to a source of clock pulses, and a preset input for releasing the flip-flop in response to the frame- synchronization-free. 6. A digital display system for reproducing the random frame signals recorded by the system of claim 1, comprising a means for detecting the recorded frame signals from the recording medium, a frequency derode fan for the frequency - de-modulating the detected frame signal to recover the accidental frame signal, means for deriving clock pulses from the recovered frame signal, and means for detecting the frame synchronization word from the recovered frame signal, characterized by a means (131, 132) for detecting phase equality between the detected synchronization word and the clock pulses, and a means (70, 130) arranged to start in response to the detected phase equality to generate a digital straighten wDord consisting of the same guia random bit pattern as the warp gword for each of the recovered frame signals, and providing a modulo-2 to -35 count of the rectifier word at the information word with the 8203050 - 27 - "· · # tt accidental character in order to return the original information word to win. System according to claim 6, 5, characterized in that the phase-equality detecting means includes a counter (141) arranged to be reset in response to the detected pharyngeal synchronization word, and serving for counting from the derived clock pulses to generate a counter output signal when a predetermined count is reached, a first coincidence gate (142) for detecting a phase equality between the output signal of the counter and the detected frame synchronization word and generating therefrom a first coincidence output signal, a shift register (145) arranged to be 15 cm filled with the first coincidence output signal, and a second coincidence port (147) connected to the stages of a shift register (145) to a second coincidence output signal and that the means (70) for generating the set-up 20 is arranged to be started ht in response to the first coincidence output signal, and to be blocked in response to the second coincidence output signal. System according to claim 7. Characterized in that the second coincidence gate is an OR gate (147). . A system according to claim 7, characterized in that the rectifier word generating device cravat generates a generator (70) for generating pulses qp in a quasi-random manner, responsive to the first coincidence output signal bit pattern of a sequence of maximum length, generate a third coincidence -..... 35 .. port (135) with inputs connected to respond t * - 18 - qp the bit pattern and on the second coincidence output signal, and an EX-QF gate (130) for supplying a modulo-2 addition of the output signal of the third coincidence gate (135) and the recovered twisted information word 5 to obtain the original information derive word. System according to claim 6, characterized in that the phase-equality detecting means comprises a counter (241) arranged to be reset in a response qp to the detected frame synchronization word, and counting the derivative. clock pulses to generate a first counter output signal when a predetermined count is reached, a first coincidence word (142): for detecting a phase-equality between the first counter output signal and the detected frame synchronization word and generating a first coincidence therefrom output signal, a shift register (245) arranged to be filled with the first coincidence output signal, a second coincidence port 20 (247) connected to the stages of the shift register (245) to generate a second coincidence output signal, and a second counter (248) arranged to be reset in response to the second coincidence output signal to count the derived clock pulses to generate a second counter output signal when the predetermined count is reached, and the means (70) for the generation of the right word is arranged to be started in cm response qp the second counter output signal. 30 System according to claim 10, characterized in that the second coincidence gate is an AND gate. 8203050 ί> - 19 - System according to claim 10, characterized in that the rectifier word generating means comprises a pulse random pulse generator (70, FIG. 10) responsive to the second coincidence output signal to generate a bit pattern of a maximum length sequence, and an EX-OR gate (130) for providing a modulo-2 addition of the bit pattern and the recovered twisted information word to derive the original information word. 10 System according to claim 6, characterized in that the phase-equality detecting means comprises a counter (241) arranged to be reset in response to the detected frame-15 synchronization word, and serving to counting the derived clock pulses to generate a first counter output signal when a predetermined count is reached, a first coincidence gate (242) for detecting a phase equality between the first counter output signal and the detecting the frame sync word and generating therefrom a first coincidence output signal, a shift register (245) arranged to be filled with the first coincidence output signal, a second coincidence port (247) connected to the stages of the shift register to generate a second-coincidence output signal when all stages of the shift register are filled with "1" bits, a third coincidence port (147a) which is connected to the stages of the shift register to generate a third coincidence output signal when all stages of the shift register are filled with "0" bits, and a second counter (248) arranged to be reset in response to the second coincidence output signal and serves to count the derived clock pulses to generate a second counter output signal when the predetermined count is reached, and the means 8203050 - 20 - (70). the rectify word generation is arranged to be started in response to the second counter output signal and to be stopped in response to the third coincidence output signal. 5 System according to claim 13, having the characteristic character that the organ represents. generating the rectify word cravat a pulse-random pulse generator (70), which generator responds to the first coincidence output signal to generate a bit pattern of a maximum length sequence, a fourth coincidence port (135a) with inputs connected to respond to the bit pattern and to the third coincidence output signal, and an EX-QF port (130) for the liver and a modulo-2 addition of the output signal from the fourth coincidence port and deriving the recovered twisted information word from the original information word. System according to claim 9, 12 or 14, characterized in that the pulse generator for quasi-random pulses comprises a first group of cascaded flip-flops (70 ^ -70 ^), a second group of cascade switched flip-flops (705 - 70 ^), and an EX-QF port (134) of which a first input is connected to the output of the first group of flip-flops and a second input is connected to the output of the second group of flip-flops, each of the flip-flops of the first and second groups having a clock input connected to the clock pulse diverting means (28-30) and a preset input for initiating clock pulses the pulse generator (70) for generating pulses of a quasi-random nature in response to an input signal applied thereto. 8203050