CA1201201A - System for recording scrambled digital signals and playback system therefor - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE:

A digital signal is organized into a sequence of frames each comprising digital words containing data information and frame synchronization information. A digital scrambling word having a predetermined bit pattern is generated by a data scrambler for each frame signal at the termination of a frame sync word. The scrambling word is modulo-2 summed with the data information word to randomize each frame signal to the exclusion of the frame sync word.
The randomized signal and a replica of the data information word are frequency modulated and the so modulated signal is recorded on a recording medium. Upon reproduction, the recorded signal is frequency demodulated to recover the scrambled frame from which clock pulses are regenerated and the frame sync word is detected. A data de-scrambler gene-rates a digital de-scrambling word when there is a phase match between the detected frame sync word and the clock signal. The de-scrambling word is modulo-2 summed with the scrambled information word to recover a replica of the original digital signal.

Description

The present invention relates to digital recordipg and/or playback systems for recording digitized analog signals, and in particular to such a systlem in which the digitized signal is scrambled prior to recording in order Jo reduce the bandwidth of the digitized signal, the recorded signal being de-scrambled upon reproduction to recover the original signal.
For high fidelity sound recording many attempts have currently been made to record digitized audio signals.
One current approach involves sampling the audio signal at a rate of 47.25 kHz and guantizing the sampled value into a digital code and organizing the data bits of the PCM signal into a sequence of frame signals each comprising digital words of synchronization, information and error detection and correction. The frame signal is usually converted to a non-return-to-zero signal having a minimum interpu]se spacing which is typically 325 nanoseconds and a frequency spectrum from zero to 6.14; the frame signal is frequency modulated prior to recording.
On the other hand, attempts have also been made to use grooveless recording discs such as capacitance detection discs and laser beam discs in which tracking signals are recorded on guide tracks parallel to information tracks. In this case the primary concern is that no inter ference should occur between the tracking and information signals. Furthermore, since the NRz signal relies on 1 bits for regenerating clock pulses, the recorded signal needs to have a sufficient amount of clock component to prevent playback or receiving systems from losing synchroni-zation.
To meet these requirements, one prior art solution involves the MFM-FM method in which the signal is first subject to modified frequency modulation and then to frequency modulation. Although the MFM-FM method is satisfactory to meet clock regeneration requirement, the I;'' '`

MFM-F~ signal has a wise frequency bandwidth and in particular its energy in the lower frequency end of the spectrum interferes with the tracking signals.
Therefore, an object of the present invention is to provide a digital recording and/or playback system in which the recorded signal contains a sufficient amount of clock components to ensure against the loss of clock pulses without increasing the bandwidth. The invention is particularly advantageous for grooveless disc recording.
More particularly, according to the invenkion, there is provided an apparatus for recording a data frame signal and a frame sync signal on a recording medium, comprising means responsive to the data frame signal and the frame sync signal for deriving a serial bit stream in which the data frame signal is scrambled and the frame sync signal is unscrambled, and means for frequency modulating said serial bit stream containing the scrambled data frame signal and the unscrambled frame sync signal.
In accordance with the present invention, there is also provided a digital recording system comprising:
means for sampling an analog signal and quantiæing the sampled signal into a digital signal;
means for formatting said digital signal into a sequence of frame signals each comprising digital words of data information and frame synchronization information;
means for generating a digital scrambling word of a pseudo-random bit pattern for each of said frame signals at the termination of said frame synchronization word and providing a modulo-2 summation of said scrambling word with said data information word to randomize the information words of each frame signal without randomizing the frame synchronization information of each frame signal;
and a frequency modulator for frequency modulating said randomized frame signal and a replica of the frame synchronization information.

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The present invention also proposes a digital playback system responsive to a frequency-modulated digital signal transduced from a recording medium, the signal including a sequence of frames including a scrambled information word and an unscrambled frame synchronization word, comprising:
a frequency demodulator for frequency demodulating said frequency-modulated digital signal to recover the scrambled information word and the unscrambled f10 synchronization word;
means for deriving clock pulses from the demodulated signal;
means for detecting said unscrambled frame synchro-nization word in said demodulated signal;
means for detecting a phase match between said detected synchronizati.on word and a specified number of said clock pulses; and means arranged to be initialized in response to said detected phase match for generating a digital de-scrambling word having a predetermined pseudo-random bit pattern for each of the frames and providing a modulo-2 summation of said de-scrambling word with the scrambled information word to recover an information word.
The subject invention further relates to an apparatus for decoding a frequ~ncy-modulated signal recorded on a recording medium, the recorded signal including scrambled data information recorded in frames and unscrambled frame synchronization information !
comprising:
means for transducing the frequency-modulated signal to derive a transduced serial signal that is a replica of the recorded frequency-modulated scrambled data information and unscrambled frame synchronization information;
means for frequency demoduIating the transduced frequency-modulated signal to derive a serial bit stream including the scrambled data information and the unscrambled frame synchronization information; and means responsive to the serial bit stream for producing a serial binary stream including a replica of the unscrambled frame synchronization information in the derived serial bit stream and an unscrambled replica of the scrambled data information in the derived serial bit stream.
Still further in accordance with the present invention, there is provided an apparatus for decoding a frequency-modulated signal recorded on a recording medium, the recorded signal including scrambled data information recorded in frames and unscrambled frame synchronization information, comprising:
means for transducing the frequency-modulated signal to derive a transduced serial signal that is a replica of the recorded frequency-modulated scrambled data information and unscrambled frame synchronization information;
means for frequency demodulating the transduced frequency-modulated signal to derive a serial bit stream including the scrambled data information and the unscrambled frame synchronization information;
means synchronized with transistions of the serial bit stream for deriving a wave having a constant frequency that is phase controlled in response to the times of occurrence of said transitions;
a pseudo-random sequence generator for deriving a coded siynal corresponding to a coded signal which scrambled the data information recorded on the medium, said generator being connected to be clocked by the constant frequency wave;
combining meanis having a first input terminal responsive to the serial bit stream and a second input terminal;

means for enabling the pseudo-random sequence generator and supplying the coded signal derived thereby to the second terminal of the combining means while the scrambled data information of the serial bit stream is being applied to the combining means, and means for causing the second terminal to be supplied with a constant signal while the unscrambled frame synchronization information is being applied to the combining means said combining means comprising means to derive a replica of the unscrambled frame synchronization information in the demodulated signal while the constant signal is applied to the second terminal and an unscrambled replica of the recorded data information in -the demodulated signal while the coded signal derived by the pseudo-random sequence generator is applied to the second terminal.
The objects, advantages and other features of the present invention will become more apparent upon reading of the following non restrictive description of preferred embodiments thereof, given for the purpose of exemplification only with reference to the accompanying drawings, in which:
Fig. l is a schematic illustration of a block diagram of the digital recording system of the invention;
Fig. 2 is an illustration of the organization of a frame signal;
Fig. 3 is an illustration of the detail of the data scrambler of Fig. l;
Fig. 4 is an illustration of a timing diagram associated with the data scrambler;
Fig. 5 is a graphic illustration of the enexgy distribution of the scrambled, frequency modulated NRz signal in comparison with a frequency modulated NR~-MFM
signal, Fig. 6 is a schematic illustration of a digital playback system of the invention;
Fig. 7 is an illustration of a timing diagram '~`'~ 'Gd associated with the playback system of Fig. 6;
Fig. is an illustration of a first embodiment of the data de-scrambler of Fig. 6;
Fig. 9 is an illustration of a timing diagram associated with the de-scrambler;
Fig. 10 is an illustration of a second embodiment of the de-scrambler;
Fig. 11 which is disposed on the same sheet of formal drawings as Figure 9 is a timing diagram associated with the embodiment of Fig. 10; and Fig. 12 is an illustration of a modification of the de-scrambler.
Referring now to Fig. 1, a digital recording system embodying the present invention is illustrated. For purposes of disclosure, the system is adapted to record four channel audio signals along a spiral track on a grooveless capacitance disc with tracking signals of different frequencies along adjacent guide tracks of part-spiral configuration divided at 360-degree intervals by a guide track switching signal. The input audio signals at terminals 1 to 4 are applied to PCM encoders 5-8 where each signal is sampled at 47.25 kHz and quantized into a stream of 16-bit codes and fed to a known time division multiplexer 9. The multiplexer includes a 23-bit CRCC
(cyclic redundancy check code generator and a 16-bit P
and Q parity generators for detection and correction of bit errors and a l-bit address generator. These redundant bits are interleaved with the time-division multiplexed data and fed to a frame synthesizer 10 where the input data are further interleaved with a 10-bit frame sync code supplied from a sync generator 11 and organized into blocks or frames of 130 bits each as illustrated in Fig. 2. The P and Q parity bits are generated in a well known manner by Modulo-2 summation of channel data words. The cyclic redudancy check code is a residue which is also obtained by a division of each data and parity word by a generator I

polynomial x 3 + x + x x 1 as known in the art. The signal from the time division multiplexer 9 is a non-retur~-to zero signal which i5 transmitted at a rclte of 6.14 Mb/s.
According to the invention, a data scrambler 12 is connected to the output of the frame synthesizer lO which randomizes or ~tscrambles the data and parity words accord-ing to a generator polynomial x + x + l. As illustrated in Fig. 3, the data scrambler 12 comprises a 7 6a ,.". ., i 1 pseudo-random pulse generator, or maximum length sequence

2 pulse generator 20 formed by a first group of cascaded D

3 flip-flops 20l to 204~ a second group of cascaded D

4 flip-flops 205 to 207 and an Exclusive-OR gate 21 connected between the first and second groups of flip flops. These 6 flip-flops constitute an m-stage shift register, where m 7 satisfies a formula N < 2m _ 1 (where N is a number of bits 8 of each frame minus the number of frame sync bits, i.e. 120 9 bits). the flip-flops of the first group have D input terminals coupled to the Q output of preceding ones with 11 the exception of flip-flop 20l of which the D input 12 terminal is coupled to the output of the flip-flop 207 of l3 the second group. The Exclusive-OR gate 21 has one input 14 coupled to the Q output of flip-flop 204 and the other input coupled to the output of flip-flop 207 The output 16 of E~clusive-OR gate 21 is applied to the D input of 17 flip-flop 205 which in turns applies its output to the D
18 input of flip-flop 206 to the output of which the D input 19 of flip-flop 207 is connected. The flip-flops 20l to 207 have their clock inputs connected together to a clock 21 generator 12a and their preset inputs connected together to 22 a timing circuit 12b which generates a timing signal in 23 response to a frame sync generated by the sync generator 24 ll. The data scrambler 12 further includes an Exclusive-OR
gaste 22 having one input coupled to the output of the 3æ~

1 frame synthesizer 10 and another input coupled to the 2 output of flip-flop 207.
3 The waveform of the timing signal aenerated by the 4 timing circuit 12b is shown at 41 in Fig. 4. This timing signal triggers the flip-flops 201 to 207 lnto a logical 6 "1" state. Following this presetting action, the 7 flip-flops 201 to 207 are clocked simultaneously at 8 periodic intervals in response to clock pulses 42 supplied g from the clock source 12a to generate a pseudo-random code of a maximum length sequence as shown at 43 in Fig. 4 11 according to the generator polynominal mentioned above.
12 The pseudo-random code khus generated is modulo-2 summecl in 13 the Exclusive-OR gate 22 with the data and parity words of 14 each frame shown at 44, Fig. 4, so that the data and parity words are scrambled, or randomized. The result of the 16 modulo-2 summation is shown at 45 which is obtained at an 17 output terminal 23. Since the pseudo-random code has an 18 approximately equal probability of occurrences of "1" and 19 "0", the scrambled data stream has a very small probability of occurrences of "0"-bit sequence. This renders a 21 playback system less dependent on the contents of the 22 received NRZ signal when regenerating clock pulses.
23 The output of the data scrambler 12 is fed to a 24 frequency modulator 13 and applied to a mixer 14 in which it is combined with a switching signal fp3 applied to a 1 terminal 15. The combined signal from the mixer 14 is 2 coupled to a known recording apparatus 16. The apparatus 3 16 modulates the intensity of a laser beam with the input 4 signal and focuses the modulated beam onto the surface of a light-sensitive layer coated on a spinning master disc 6 record 19 to form a series of minute pits along h spiral 7 track. From input terminals 17 and 18 tracking signals 8 fpl and fp2 of different frequencies are supplied to the 9 recording apparatus 16. These tracking signals are each used to modulate the intensity of an associated laser beam 11 to form guide tracks adjacent to the information track.
12 As illustrated in Fig. 5, the tracking signals fpl 13 and fp2 and switching signal fp3 thus recorded in the disc 14 19 are in a range of frequencies from 100 kHz to 1 MHz. A
curve A in Fig. 5 is a representation of the energy 16 distribution of a conventional frequency modulated MFM NRZ
17 signal. Curve s is a representation of the energy distribution of the 18 frequency modulated, scrambled NRZ signal according to the 19 invention. A comparison of curves A and B reveals ZO that the energy of the frequency-modulated, scrambled NRZ
21 signal is concentrated on the center frequency range of the 22 spectrum and therefore the signal-to-noise ratio of the 23 tracking control sigDals fpl, fp2 and fp3 is improved.
24 After description of the recording system now follows a description of a playback system according to the _ g _ b ~g~

invention with reference to Fig. 6. The playback system comprises a detector 25 including a capacitance detection stylus which rests on several tracks of a record 24 to pick up information signals and tracking signals in a manner known in the art. The detected information signal is applied to a frequency demodulator 26 and thence to a level detector 27 in which the signal level of the demodulated signal is sharply defined to recover the scrambled data. An edge detector 28 is connected to the output of detector 27 to generate a narrow pulse 52 in response to each of the leading and trailing edges of the scrambled pulses 51 shown in Fig.
7. The pulses 52 derived from the edge detector 28 are applied to a tank circuit 29 to generate a sinusoidal signal 53 which is then applied to a phase-locked loop 30 which compensates for jitter and drop-outs in the signal derived by thestylus 25, demodulator 26 and detector 27; the sinusoidal signal generated by tank circuit 29 is converted by the loop 30 to clock pu~.ses as shown at 54. The digital pulses 51 of the detector 27 are also applied to the D input of a flip-flop 31 having a clock input responsive to pulses from the phase-locked loop 30. Therefore/ the D input of flip-flop 31 is latched to the binary level of the input pulses 51 in response to the clock pulses 54, so the flip-flop output is a pulse train 55, Fig. 7.
The output of the D flip-flop 31 is applied to a data de-scrambler 32. A sync detection and protection circuit 33 is coupled to the data de-scrambler 32. An .~
I

1 error detection and correction circuit 34 is connected to 2 the sync detection and protection circuit 33 to detect 3 errors in the data words of each frame signal using the 4 cyclic redundancy check code and correct such detected errors using P and Q parity words in a well known manner.
6 One example of the de-scrambler 32 is shown in 7 Fig. 8. The de-scrambler 32 of Fig. 8 is a feedback ~~
8 controlled system which comprises a pseudo-random pulse 9 generator 70 of the same construction as the pseudo-random pulse generator 20 used in scrambling the recorded data.
11 The psuedo-random pulse generator 70 comprises a fixst 12 group oE cascaded D flip-flops 701 to 704 and a second 3 group of cascaded D flip-flops 705 to 707 and an 14 Exclusive-OR gate 134 having one input coupled to the output of flip-flop 70~ and another input coupled to the 16 output of flip-flop 707 ; gate 134 has an output to the ~7 D input of flip-flop 705 Generator 70 generates a pulse 18 train having a maximum length sequence according to the 19 generator polynomial X7 + X4 -I 1 as in the scrambler 12 and supplies its output via an AND gate 135 to an input of an 21 Exclusive-OR gate 130 to which the signal from the D
22 flip-flop 31 is applied.
23 The sync detection and guard circuit 33 comprises 24 a sync detector 131 and a sync yuard circuit 132. The sync detector 131 is formed by a shift register 139 clocked by I' ;~z~

the output of the phase-locked loop 30 and an AND gate 140 coupled to the flip-flop stages of the shift register 139 so that when a frame sync code 1010111000 is loaded into the shift register 139 the AND gate 140 provides a coincidence output. The signal from the phase locked loop 30 causes data stored in toe shift register 139 to be clocked out in serial form to a shift regiqter 136 which is coupled in parallel form to a data register 137.
The sync guard circuit 132 includes a counter 141 which reset in response to the sync pulse from AND gate 140 to start counting clock pulses from the phase-locked loop 30. When the counter 141 counts 120 and 130 pulses, it respectively supplies a reset pulse to a flip-flop 144 and a pulse to an AND gate 142 to which the sync pulse from AND gate 140 is also applied. The output of AND gate 142 is coupled on the one hand to the set input of the flip-flop 144 and on the other hand to a.n 8-bit shift register 145 whose internal stages are coupled to an OR
gate 147. The output of flip-flop 144 is connected to the 20 preset inputs of flip-flops 701 to 707 and the output of OR gate 147 is coupled to the AND gate 135.
The operation of the de-scrambler 32 will now be described with reference to waveforms sho~m in Fig. 9.
Illustrated at 81 in Fig. 9 is the waveform of an input to the de-scrambler 32. Upon receipt of a 10-bit frame sync, ;

.
, . ., ~,~

1 pulse 82 is generated from AND gate 140 and resets the 2 counter 141. The counter 141 starts counting clock pulses 3 that occur subsequent to the detection of the 10-bit sync 4 code and since the frame contains 130 bits, the counter 141 provides an output pulse 83 at the end of each frame to a 6 latch input of the data register 137 and at the same time 7 to the reset input of flip-flop 144. The counter 141 also 8 provides an output pulse 84 to the AND gate 142 at the 9 count of a 130th clock which corresponds to the end of each frame sync code. If the sync code occurs at correct 11 timing, the AND gate 142 feeds a coincidence output to the 12 shift register 145 and to the flip-flop 144, so that the 13 latter is in a reset condition during the period of frame 14 sync and in a set condition during the remainder of the free period as shown by wave-form 85 in Fig.9.'~efore, the 16 flip-flops 701 to 707 are disabled during the sync period 17 and enabled during the remainder of frame period to 18 generate a de-scrambling code. The de-scrambling code 19 comprises the same bit pattern as the scrambling code bit pattern and each bit of the de-scrambling code is generated 21 in response to the clock pulses supplied from phase~locked 22 loop 30-23 The coincidence output from the AND gate 142 is 24 shifted in the 8-bit shift register 145 in response to each frame clock which is obtained from the 130th count output .

1 of the counter 141. If frame sychronization is established 2 for at least one frame interval, the shift register 145 is 3 loaded with one bit and OR gate 147 provides an output to 4 AND gate 135. it the same time the flip-flop 144 is triggered into a set condition to reset the timing of the 6 pseudo-random pulse generator 70. The de-scrambling code 7 is thus passed through the AND gate 135 to the Exclusive-OR
gate 130 where it is combined by modulo-2 addition with the 9 scrambled data. The de-scrambled data bits are clockPd out in vial fashion from the shift register 136 to an external utilization 11 circuit, not shown, and also in parallel to the data 12 register 137. The data latched in register 137 are 13 transferred to the error detection and correction circuit 14 34 to provide error detection and correction as described above.
16 During starting periods of the apparatus or in 17 the presence of a drop-out which may continue for at least 18 an 8-frame interval, the system will go out of sync and the 19 clock timing i5 out of phase with respect to the output pulse 82 of the sync detector 131 and mismatch 21 occurs in the AND gate 142. The shift register 145 is 22 emptied and a logical "0" output, or disabling signal is 23 applied to the AND gate 135. The de-scrambl~ing code also 24 is out of phase with respect to the input data applied to AND gate 130; the derivation of the de-scrambling code is disabled in response to ye .

disabling signal applied to E~clusive-O~ gate 135. The disabling signal on AND gate 135 applies a logical 0 to the Exclusive-OR gate 130 to allow the input data to be passed therethrough. When a-match occurs in the AND gate 142, the flip-flop 144 and hence the pseudo-random pulse generator 70 is reset to correct timing and the END gate 135 is enabled to pass the de-scrambling code to the Exclusive-OR gate 130 to reswme the de-scrambling operation.
A second embodiment of the data de-scrambler is illustrated in Fig. 10 in which the output of Exclusive-OR
gate 139 is coupled to the shift register 136 to provide feedforward operation and in which the same numerals are used to designate parts corresponding to those in Fig. 8.
The sync guard c.ircuit, designated 232, includes a counter 241 which provi.des an output for every count of 130 clock pulses to AND gate 142 to which the sync detection signal 82 from AND gate 140 is applied. The coincidence output of AND gate 242 is fed to an 8-bit shift register 245 whose counter stages are coupled to an AND gate 247 ! instead of to the OR gate 147 as in the embodiment of FigO 8. A counter 248 and a flip-flop 244 are provided. The counter 248 is reset in response to an output from the AND gate 247 to count clock pulses from the phase-locked loop 30 to generate a first pulse at the count of a 130th clock which corres-ponds to the start of the data _ _..

.

1 word to set the flip-flop 244 and a second pulse at the 2 count of a 120th clock which corresponds to the end of the 3 frame to reset the flip-flop 2~4. The output of the 4 flip-flop 244 is connected to the preset terminals of the - flip-flops 701 to 707. The output of the flip-flop 707 is 6 directly connected to the Exclusive-O~ gate 130. The data 7 register 137 is reset in response to the 120th count output 8 from the counter 248.
9 The operation of the embodiment of Fig. 10 is best described with reference to Fig. 11. The system may be 11 out of sync for a certain per.iod tl to t2 immediately after the 12 initial energization, so that the sync detection pulses 82 are 13 out of phase with respect to pulses 103 from counter 248 14 which correspond to the start of each data word as shown in Fig. 11. Therefore, the de-scrambling code 103 is out of 16 phase with respect to the coincidence pulse 100 during that 17 interval. On the other hand, the counter 241 is reset by 18 the sync detection pulse 82 and there occurs a match in the 19 AND gate 242 in response to each frame sync, thus generating a pulse 100. In response to a pulse 100-1 from 21 AND gate 242 at time t2, the shift register 245 is filled with 22 all binary 1 values and AND ace 247 generates a reset pulse 23 101-1 to reset the counter 248, so that the pulses 102 24 become in phase with the pulses 100 and thereafter the de-scrambling code is generated in phase with correct ~J~

1 timing.
2 Assuming that a drop-out occurs during a period t3 3 to t4 and the pulses 100 cease to exist during this 4 interval. On the other hand, the phase-locked loop 30 continues due to its locked condition and the counter 248 6 is still generating pulses 103 in correct timing although 7 the reset pulses 101 are not present At time ~5 which is 8 after eight frames from time t4, the shift register 145 is 9 filled and the counter 248 is reset to the correct timing.
Fig. 12 is a modification of the de-scrambler of 11 Fig. 10. Briefly, the de-scrambler of Fig. 12 is a 12 combination of the embodiments of Figs. 8 and 10, so that 13 it includes an OR gate 147a coupled to the counter stages 14 of shift register 245 to provide an output when the shift register 245 is emptied. The output from the OR gate 147a 16 is coupled to an input of an AND gate 135a to which the 17 output of flip-flop 707 is applied. Thus, combined 18 features of Figs. 8 and 10 are provided. If an out-of-sync 19 condition lasts for a period of eight frames, the OR gate 147a disables the AND gate 135a to suspend de-scrambling 21 operation. De-scrambling operation will be resumed in 22 response to an output from OR gate 147a when 23 synchronization lasts at least for a period of one frame.
24 Modifications of the present invention are apparent to those skilled in the art without departing from I, 1 the scope of the invention.

'I 1

Claims (25)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Apparatus for recording a data frame signal and a frame sync signal on a recording medium, comprising means responsive to the data frame signal and the frame sync signal for deriving a serial bit stream in which the data frame signal is scrambled and the frame sync signal is unscrambled, and means for frequency modulating said serial bit stream containing the scrambled data frame signal and the unscrambled frame sync signal.

2. A digital recording system comprising:
means for sampling an analog signal and quantizing the sampled signal into a digital signal;
means for formatting said digital signal into a sequence of frame signals each comprising digital words of data information and frame synchronization information;
means for generating a digital scrambling word of a pseudo-random bit pattern for each of said frame signals at the termination of said frame synchronization word and providing a modulo-2 summation of said scrambling word with said data information word to randomize the information words of each frame signal without randomizing the frame synchronization information of each frame signal;
and a frequency modulator for frequency modulating said randomized frame signal and a replica of the frame synchronization information.

3. A digital recording system as claimed in claim 2, further comprising means for recording (a) said fre-quency modulated randomized frame signal and the replica of the frame synchronization information of each frame signal in a recording medium and (b) tracking signals having a lower frequency range in the spectrum of the recorded frequency modulated signal.

4. A digital recording system as claimed in claim 2, wherein said scrambling word generating means comprises a pseudo-random pulse generator and an Exclusive-OR gate for deriving a modulo-2 summation of an output of the pseudo-random pulse generator and said data informa-tion word.

5. A digital recording system as claimed in claim 4, wherein said pseudo-random pulse generator comprises a maximal length sequence pulse generator.

6. A digital recording system as claimed in claim 5, wherein said maximal length sequence pulse generator comprises a first group of cascaded flip-flops, a second group of cascaded flip-flops, and an Exclusive-OR gate having a first input connected to an output of said second group of flip-flops, each of the flip-flops of said first and second groups having a clock input connected to respond to a source of clock pulses and a preset input for enabling the flip-flops in response to derivation of said frame synchronization word.

7. A digital playback system responsive to a frequency-modulated digital signal transduced from a recording medium, the signal including a sequence of frames including a scrambled information word and an unscrambled frame synchronization word, comprising:
a frequency demodulator for frequency demodu-lating said frequency-modulated digital signal to recover the scrambled information word and the unscrambled frame synchronization word;
means for deriving clock pulses from the demodulated signal;
means for detecting said unscrambled frame synchronization word in said demodulated signal;
means for detecting a phase match between said detected synchronization word and a specified number of said clock pulses; and means arranged to be initialized in response to said detected phase match for generating a digital de-scrambling word having a predetermined pseudo-random bit pattern for each of the frames and providing a modulo-2 summation of said de-scrambling word with the scrambled information word to recover an information word.

8. A digital playback system as claimed in claim 7, wherein said phase match detecting means comprises:
a counter arranged to be reset in response to said detected frame synchronization word for counting said derived clock pulses to generate a counter output in response to a predetermined count being reached;
a first coincidence gate for detecting a phase match between said counter output and the detected frame synchronization word and generating therefrom a first coincidence output;
a shift register having a plurality of stages and arranged to be loaded with said first coincidence output; and a second coincidence gate coupled to the stages of said shift register to generate a second coincidence output, said de-scrambling word generating means being arranged to be initialized in response to said first coincidence output and arranged to be disabled in response to said second coincidence output.

9. digital playback system as claimed in claim 8, wherein said second coincidence gate is an OR gate.

10. A digital playback system as claimed in claim 8, wherein said de-scrambling word generating means comprises a pseudo-random pulse generator responsive to said first coincidence output to generate a bit pattern of a maximum length sequence, a third coincidence gate having inputs connected to be responsive to said bit pattern and to said second coincidence output, and an Exclusive-OR gate for providing a modulo-2 summation of an output of the third coincidence gate and said recovered scrambled information word to derive the original information word.

11. A digital playback system as claimed in claim 7, wherein said phase match detecting means comprises:
a counter arranged to be reset in response to said detected frame synchronization word for counting said derived clock pulses to generate a first counter output when a predetermined count is reached;
a first coincidence gate for detecting a phase match between said first counter output and the detected frame synchronization word and generating therefrom a first coincidence output;
a shift register having a plurality of stages and arranged to be loaded with said first coincidence output;
a second coincidence gate coupled to the stages of said shift register to generate a second coincidence output;
a second counter arranged to be reset in response to said second coincidence output for counting said derived clock pulses to generate a second counter output when said predetermined count is reached;
said de-scrambling word generating means being arranged to be initialized in response to said second counter output.

12. A digital playback system as claimed in claim 11, wherein said second coincidence gate is an AND
gate.

13. A digital playback system as claimed in claim 11, wherein said de-scrambling word generating means comprises a pseudo-random pulse generator responsive to said second coincidence output to generate a bit pattern of a maximum length sequence, and an Exclusive-OR gate for providing a modulo-2 summation of said bit pattern and said recovered scrambled information word to derive the original information word.

14. A digital playback system as claimed in claim 7, wherein said phase match detecting means comprises:
a counter arranged to be reset in response to said detected frame synchronization word for counting said derived clock pulses to generate a first counter output when a predetermined count is reached;
a first coincidence gate for detecting a phase match between said first counter output and the detected frame synchronization word and generating therefrom a first coincidence output;
a shift register having a plurality of stages and arranged to be loaded with said first coincidence output;
a second coincidence gate coupled to the stages of said shift register to generate a second coincidence output when all the stages of said shift register are loaded with <<1>> bits;
a third coincidence gate coupled to the stages of said shift register to generate a third coincidence output when all the stages of said shift register are loaded with <<0>> bits; and a second counter arranged to be reset in response to said second coincidence output for counting said derived clock pulses to generate a second counter output when said predetermined count is reached;
said de-scrambling word generating means being arranged to be initialized in response to said second counter output and arranged to be disabled in response to said third coincidence output.

15. A digital playback system as claimed in claim 14, wherein said de-scrambling word generating means comprises a pseudo-random pulse generator responsive to said first coincidence output to generate a bit pattern of a maximum length sequence, a fourth coincidence gate having inputs connected to be responsive to said bit pattern and to said third coincidence output, and an Exclusive-OR gate for providing a modulo-2 summation of an output of the fourth coincidence gate and said recovered scrambled information word to derive the original information word.

16. A digital playback system as claimed in claim 10, 13, or 15, wherein said pseudo-random pulse generator comprises a first group of cascaded flip-flops, a second group of cascaded flip-flops, and an Exclusive-OR gate having a first input connected to an output of said first group of flip-flops and a second input connected to an output of said second group of flip-flops, each of the flip-flops of said first and second groups having a clock input connected to said clock pulse deriving means and a preset input for initializing the pseudo-random pulse generator in response to an input signal applied thereto.

17. A digital playback system as claimed in claim 15, wherein said pseudo-random pulse generator comprises means for generating said bit pattern according to a generator polynomial.

18. A digital playback system as claimed in claim 7, wherein said demodulated signal comprises binary digits having leading and trailing edges, and wherein said clock pulse deriving means comprises means for generating a pulse in response to the leading and trailing edges of the binary digits of the demodulated signal, a tank circuit receptive of said edge responsive pulse for generating a sinusoidal wave signal, and a phase-locked loop coupled to said tank circuit.

19. A digital playback system as claimed in claim 18, further comprising a D flip-flop having a D input terminal connected to be responsive to the binary digits of the demodulated signal and a clock input connected to be responsive to an output signal from said phase-locked loop.

20. Apparatus for decoding a frequency-modulated signal recorded on a recording medium, the recorded signal including scrambled data information recorded in frames and unscrambled frame synchronization information, comprising:
means for transducing the frequency-modulated signal to derive a transduced serial signal that is a replica of the recorded frequency-modulated scrambled data information and unscrambled frame synchronization information;
means for frequency demodulating the transduced frequency-modulated signal to derive a serial bit stream including the scrambled data information and the unscrambled frame synchronization information; and means responsive to the serial bit stream for producing a serial binary stream including a replica of the unscrambled frame synchronization information in the derived serial bit stream and an unscrambled replica of the scrambled data information in the derived serial bit stream.

21. Apparatus for decoding a frequency-modulated signal recorded on a recording medium, the recorded signal including scrambled data information recorded in frames and unscrambled frame synchronization information, comprising:
means for transducing the frequency-modulated signal to derive a transduced serial signal that is a replica of the recorded frequency-modulated scrambled data informa-tion and unscrambled frame synchronization information;
means for frequency demodulating the transduced frequency-modulated signal to derive a serial bit stream including the scrambled data information and the unscrambled frame synchronization information;

means synchronized with transitions of the serial bit stream for deriving a wave having a constant frequency that is phase controlled in response to the times of occurrence of said transitions;
a pseudo-random sequence generator for deriving a coded signal corresponding to a coded signal which scrambled the data information recorded on the medium, said generator being connected to be clocked by the constant frequency wave;
combining means having a first input terminal responsive to the serial bit stream and a second input terminal;
means for enabling the pseudo-random sequence generator and supplying the coded signal derived thereby to the second terminal of the combining means while the scrambled data information of the serial bit stream is being applied to the combining means; and means for causing the second terminal to be supplied with a constant signal while the unscrambled frame synchronization information is being applied to the combining means, said combining means comprising means to derive a replica of the unscrambled frame synchronization information in the demodulated signal while the constant signal is applied to the second terminal and an unscrambled replica of the recorded data information in the demodulated signal while the coded signal derived by the pseudo-random sequence generator is applied to the second terminal.

22. An apparatus as claimed in claim 21, wherein the means for deriving the constant frequency wave includes a tank circuit that is excited into an oscillating state in response to the transitions of the serial bit stream.

23. An apparatus as claimed in claim 21, further comprising means for synchronizing the coded signal derived by the pseudo-random sequence generator with the serial bit stream.

24. An apparatus as claimed in claim 23, wherein the synchronizing means includes:
means for detecting the presence of the unscrambled frame synchronization information in the serial bit stream, the pseudo-random sequence generator being effectively activated to supply the second terminal of the combining means with the coded signal derived thereby in response to the detecting means indicating the presence of the unscrambled synchronization information in the serial bit stream.

25. An apparatus as claimed in claim 24, wherein the synchronizing means includes means for presetting the pseudo-random sequence generator in response to the unscrambled frame synchronization information being detected.