KR840001359A - Scrambled digital signal recording and playback device - Google Patents

Abstract

No content

Description

Scrambled digital signal recording and playback device

As this is a public information case, the full text was not included.

1 is a block diagram of a digital recording apparatus of the present invention. 6 is a system diagram of the digital regeneration device of the present invention. 9 is a timing diagram associated with the de-scrambler.

Claims (19)

A digital recording apparatus, comprising: means for sampling an analog signal and quantizing the sample signal into a digital signal, and means for forming the digital signal into a series of frame signals including digital information of information and frame synchronization, respectively; Means for generating a digital scrambling word of a pseudo-random bit pattern for each frame signal at the terminal of the frame sync word and performing modular-2 summation of the scrambling word with the information word to randomize each frame signal. And a frequency modulator for frequency modulating the randomized frame signal, and means for recording the frequency-modulated randomized frame signal on a recording medium. A digital recording apparatus according to claim 1, wherein said recording means includes means for recording a tracking signal in a lower frequency region of the recorded signal spectrum. A digital recording apparatus according to claim 1, wherein the scrambling generator generating means comprises a pseudo-random pulse generator and an exclusive-OR gate to perform modulo-2 summation of the output of the pseudo-random pulse generator and the information word. An apparatus for recording and reproducing a scrambled digital signal. 4. A digital recording apparatus according to claim 3, wherein said pseudo-random pulse generator comprises a sequential pulse generator of maximum length. 5. The digital recording apparatus according to claim 4, wherein the sequential pulse generator of maximum length is used to output the first group of dependent flip flops, the second group of connected flip flops, and the first group of flip flops. An exclusive-OR gate having a second input connected to a connected first input and an output of the second group of flip-flops, each of the first and second groups of flip-flops connected to a clock pulse source And a preset input for operating a flip-flop in response to the input clock input and the frame synchronizing word. A digital reproducing apparatus for reproducing a randomized frame signal recorded by the system according to claim 1, comprising: means for detecting a frame signal recorded from the recording medium and the detection to recover a randomized frame signal. A frequency demodulator for frequency demodulating the recovered frame signal, means for extracting a clock pulse from the recovered signal, means for detecting the frame sync word from the recovered frame signal, the detected sync word and the clock Means for detecting phase-matching between pulses and a digital de-scrambler having the same pseudo-random bit pattern as the scrambling word for each recovered frame signal and randomizing the de-scrambler to recover the original information word. The response to the detected phase match is performed to perform modulo-2 summation with the information word. And a means arranged to begin with. Scrambled digital signal recording and reproducing apparatus. A digital reproducing apparatus according to claim 6, wherein the frequency matching means is arranged to be reset in response to the detected frame synchronizer to generate a counter output when the drawn clock pulse is counted and reaches a predetermined coefficient. A first matching gate for detecting a frequency match between the counter output and the detected synchronous word and generating a first matching output therefrom, a shift register arranged to be loaded as the first matching output, and a shift register A second matching gate coupled to the stages to generate a second matching output, wherein a fraudulent de-scrambler generating means is arranged to initiate a response to the first matching output and at the same time non-responsive to the second matching output. And a scrambled digital signal recording and reproducing apparatus arranged to be operated. 8. The digital reproducing apparatus according to claim 7, wherein the second matching gate OR gate is a scrambled digital signal recording and reproducing apparatus. 8. The digital reproducing apparatus according to claim 7, wherein the pseudo-random pulse generator and the third matching gate are configured to respond to the first matching output such that the descrambling generator generating means generates a bit pattern of a sequential pulse of maximum length. A third matching gate having an input connected in response to a bit pattern and the second matching output, and modulo-2 summation of the output of the third matching gate and the recovered randomized information word to perform the original information word. And recording and reproducing the scrambled digital signal. A digital reproducing apparatus according to claim 6, wherein the phase matching detecting means resets in response to the detected frame synchronizing word to count the derived clock pulse to generate a first counter output when the phase matching detecting means reaches a predetermined coefficient. A counter arranged to load, a first matching gate for detecting a phase match between the first counter output and the detected frame synchronizing word and generating a first matching output therefrom, and a shift register arranged to be loaded on the first matching output And a second matching gate coupled to the stages of the shift register to generate a second matching output; and counting the pulled clock pulse to generate a second counter output when the predetermined counter is reached. And a second counter arranged to be reset in response to an output, wherein said descrambling generator generating means responds to said second counter output. The recording and reproducing apparatus of the scrambled digital signals, characterized in that arranged to start. 11. The digital reproducing apparatus according to claim 10, wherein the second matching gate is an AND gate. A digital reproducing apparatus according to claim 10, wherein the descrambling word generating means generates a sequential bit pattern of maximum length in response to the second matching output, and the original information word is attracted. And an exclusive-OR gate for performing modulo-2 summation of said bit pattern and said recovered randomized information word to produce a scrambled digital signal. A digital reproducing apparatus according to claim 6, wherein the phase matching detecting means resets in response to the detected frame synchronizing gear to generate a first counter output when the drawn clock pulse is counted to reach a predetermined coefficient. A counter arranged to be loaded, a first matching gate for detecting a phase match between the first counter output and the detected frame synchronization gear and generating a first matching output therefrom, and a shift register arranged to be loaded on the first matching gate A second match gate coupled to the stages of the shift register to generate a second matched output when all stages of the shift register are loaded with " 1 " bits, and all stages of the shift register coupled to the stages of the shift register. A third matching gate which generates a thirteenth matching output when loaded with this " 0 " bit, and counts the derived clock pulses to And a second counter arranged to reset in response to the second matching output to generate the second counter output when a positive coefficient is reached, wherein the descrambling generator generating means responds to the second counter output. And is arranged to be deactivated in response to the third matched output. 14. The digital reproducing apparatus according to claim 13, wherein the descrambling generator generating means generates a sequential bit pattern of maximum length in response to the first matched output, the bit pattern and the third pattern; An exclusive-OR gate that modulo-2 sums the fourth matching gate having an input connected in response to the coincidence output and the output of the fourth coincidence gate and the recovered randomized information word to derive the original information word; Apparatus for recording and reproducing a scrambled digital signal comprising a. A digital reproducing apparatus according to claim 9, 12 or 14, wherein the pseudo-random pulse generator comprises a first group of cascaded flip flops, a second group of cascaded flip flops, and the first group of flip flops. An exclusive-OR gate having a first input connected to an output of the flop and a second input connected to an output of the second group of flip flops, wherein each of the first and second groups of flip flops includes the clock; Recording and reproducing a scrambled digital signal having a clock input connected to the pulse outlet means and a preset input for starting the operation of the pseudo-random pulse generator in response to an input signal applied to the pseudo-random pulse generator. Device. 15. The apparatus for recording and reproducing a scrambled digital signal according to claim 14, wherein the pseudo-random pulse generator is arranged to generate the bit pattern according to the polynomial of the generator. A digital reproducing system according to claim 6, wherein said clock pulse outlet means generates a sine wave signal by receiving a pulse in accordance with a rising and falling edge of a binary digit of a demodulated signal, and said interval response pulse. A scrambled digital signal recording and reproducing apparatus, comprising: a tank circuit and a phase locked loop coupled to the tank circuit. 18. A digital reproducing apparatus according to claim 17, comprising a D flip flop having an input terminal connected in response to a binary digit of a demodulated signal and a clock input connected in response to the phase locked loop and an output signal. An apparatus for recording and reproducing a scrambled digital signal. ※ Note: The disclosure is based on the initial application.