NL8002344A - MULTIPROCESSOR SYSTEM WITH COMMON DATA / ADDRESS BUS. - Google Patents

Description

r I> PHN 9730 1 N.V. PHILIPS »BULB FACTORIES IN EINDHOVEN. Multiprocessor system with common data / address bus.

BACKGROUND OF THE INVENTION.

The invention relates to a calculator system, comprising a number of first processors which are interconnected by: a. A data bus for each time transporting a multi-bit data word in parallel between a first processor and at least one further arrangement of the calculator system; b. a control bus containing a number of parallel-connected control lines; each processor being provided with first means for supplying its multi-bit priority number to a multi-bit arbitration bus interconnecting the processors before the realization of a data transport of its choice, and the arbitration bus being provided with second means for, in the event of a plurality of priority numbers received together, by means of a logical function forming a logic function of the bits thereof, to determine the highest priority number therefrom and to apply a permission signal to the associated processor to the exclusion of further processors. Such a system is a multiprocessor system. The further device can be a second processor, a memory, an input / output device. The data transport can be directed from or to the requesting processor. The processors can be built very simply, for instance as a microprocessor, or be larger. The processors may be functionally equivalent, but need not be: "central" processors (CPUs), input-output processors, and special purpose processors, for example, function generators such as multipliers, may be present together. 30 The priority numbers are now tested against each other in order to be able to allocate the data bus. San the processor with the highest priority: for example, the data bus can in principle be assigned to a rapidly changing sequence of (first) processors.

800 2 3 44 * * (PHN 9730 2

A calculator system according to the preamble is known from US patent specification 3710351. This gives a separate data bus of 4 bits wide and an arbitration bus of 4 bits wide connected in parallel therewith. The bits of the priority number are applied together to an arrangement of blocking gates. The blocking gates have their output connected to the bitline of the arbitration bus which has a corresponding significance, and a blocking input is connected to the bitline of the next higher signifier, if any. The bit lines each form a wired OR function. Thus, if a "higher" priority number from another processor is produced on the arbitration bus, it blocks the production of further bits from a "lower" priority number. When the situation has settled, the arbitration bus carries the highest priority number that is currently active and the data bus is released for information transport from the processor with the highest priority number that is currently relevant.

SUMMARY OF THE INVENTION.

If it is not known in the above system which priority numbers can occur, it is necessary to wait each time until, for each successive bit line, all transit times of the signals along the arbitration bus have expired. This can take a long time, which can mean a considerable management burden (overhead) with rapidly changing "rulers" (masters) of the data bus line. It is an object of the invention to realize a reduction of said management load, because in many cases it can already be determined on the basis of one or a few high-priority priority bits which processor is the "new" ruler of the data bus. The invention achieves the object because it has the characteristic that each processor contains: - c. detection means for a start signal to then supply its priority number to the arbitration bus at a data transport desired by that processor, and a cycle tracking element with a series of a number of positions, which is indicated by said start signal in the first position of 8 00 2 3 44 * ► PHN 9730 3 said series and is placed in a next position of the series by a progress signal; d. a comparison element, in each case under control of a position of the cycle tracking element, in each case comparing the self-priority number 5 entirely with the priority number formed by said logic function on said arbitration bus, and in the case of equality forming a "winner" signal; under control of a position "p" of said series of positions of the cycle tracking element, in each case, comparing the bit in the significance level p-the bit from the top of its own priority number with the corresponding bit formed on the arbitration bus, and in the absence of said "winner" signal in case of equality to form said "progress" signal, but in case of inequality said first means can be deactivated; f. a second detector to detect any "winner" signal generated in said calculator system by another processor and then deactivate said first means; 20 g. third means for realizing the desired data transport under the control of its own "winner" signal and forming said start signal at the end thereof, for supplying to all the first processors of the calculator system.

In many cases the winning processor of the arbitration will already be known after a few positions of the cycle-tracking element. It should be noted that in this connection the significance of the bits of the priority number is determined by the order in which they are compared as pth bit in the arbitration in question. Under other circumstances, for example in the next arbitration, the level of significance may be different again.

It is advantageous if the data bus operates as an arbitration bus from said start signal to said "winner" signal. This results in a limitation in the number of lines required, and the possibility to use more processors for the same number of lines. The referenced known system can then contain 256 instead of 16 processors, while the throughput capacity is also 800 2 3 44

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PHN 9730 4 before the data has almost doubled. On the other hand, in the case of separate data and arbitration buses, in principle, transport and arbitration may overlap in time, but not in the embodiment shown in the cited US Patent 5 3 710 351.

It is favorable if for a priority number of n bits (pl ...... pn), where pl is most significant, the priority numbers are chosen from the set: (pl ... .pi, pi + l ... ..pj, pj + 1 ...... pn), with 10 i ^ 0, j ^ i + 1, y ^ n in which the bits (pl ..... pi) can have any value, the bits pi + 1 ..... pj) all the lowest bit value and the bits. pj + 1 ....... pn) all have the highest bit value, i having the same value for all processors and j 15 having a selectable value, so that the set has at most a number P = 21. (n + li) contains elements to be used, and that the number of positions of said series is at least equal to (i + 1). Thus, in a very small number of positions of the cycle control 23, the new bus ruler is known as the number of processors is not too large. With (n + 1) processors it can always be known in position "1", with 2n processors always in position "2". In the above, under the "highest" bit value, it is assumed to mask another bit value on the particular line of the arbitration bus. With an OR function thereon a "1" is the highest value, so with an AND function the "0" is the highest value.

BRIEF DESCRIPTION OF THE FIGURES The invention is explained in more detail with reference to some figures. First, the known technique will be further discussed. The general course of events in an arbitration operation is then explained. Then an advantageous choice of the priority numbers is given. Finally, a preferred embodiment is discussed, in particular on the basis of a number of time and state diagrams.

Fig. 1 shows the subsequent phases of an information exchange; 800 2 3 44 <* PHN 9730 5

Fig. 2 shows a device according to the known art;

Fig. 3 gives an example of the course of arbitration (global); FIG. 4 illustrates an advantageous selection of the priority numbers;

Fig. 5 gives the number of possible priority numbers in different situations;

Fig. 6 indicates the connection of the processors to arbitration and control bus;

Fig. 7 is a flow chart of an elementary part of the arbitration;

Fig. 8 shows a time diagram of a three-wire toothing (handshake) system; FIG. 9a-9f show six time diagrams of parts of an arbitration operation;

Fig. 10a-10f give six state diagrams regarding the different processors.

ENVIRONMENT OF THE INVENTION.

FIG. 1 illustrates the subsequent parts of an information exchange between a processor and a further device, via the common database. The arbitration takes place in time interval 54; thereby answering the question, which processor gets the message about the data bus. The selection takes place in the time interval 56. The processor that has access to the data bus (ruler) selects one or more further devices for exchanging information. The actual information transport takes place in time interval 58; the "master" processor may be both transmitting and receiving. In the time interval 60, further activities take place which concern the information transfer, for example sending back an acknowledgment signal. Time intervals 58 and 60 can thus alternate in each case. In the time interval 62 the release takes place: the reservation of the further device (s) is ended and the master processor gives a signal that the information transport has ended. In the time interval 800 23 44 PHN 9730 6 64 nothing happens; it is in place so that further processors can detect the aforementioned release, so that a new arbitration phase can then be started. The above assumes that all operations 5 are successful. On the other hand, it is also possible, for example, that the device to be selected is not available, for example: the operations that take place in the time intervals 58, 60, 62 are then canceled: only the release signal for the other processors is still formed.

10 THE KNOWN ESTABLISHMENT

Functionally, the invention mainly relates to the events in the interval 54 of FIG. 1. In this connection, FIG. 2 shows for recapitulation a part of the device known from US Pat. No. 3,710,351, namely a single processor with the arbitration bus of 4 bits wide (20). Element 22 generates on its four outputs the priority number of the respective processor. The most significant bit is applied directly to the arbitration bus, the remaining bits via gates 24, 26, 28. There are seven 20 AND gates (24, 26, 28, 30, 32, 34, 36), of which certain inverting inputs are identified by a circle. Furthermore, there are three NON-0F (N0R) ports 38, 40, 42. If the processor in question has a "1" as the most significant priority bit, it is applied to line 44, 25 and hence to port 30, which is its second inverting input is blocked. Therefore, gate 24 on its inverting input receives a "0", so that it becomes permeable to the next-bearing-significant bit of element 22. If the most-significant address bit of the respective processor is a "0", and there is no if another processor generates a "1" for line 44, gate (AND gate) 33 receives a "0" on its inverting input, but also an "o" on its non-inverting input, so that its output remains "0". This too is applied to the inverting input of gate 24, which then also remains permeable to the next-lower significant bit of the priority number. In the latter case, if another processor generates a "1" on line 44 as the most significant bit of the priority number 800 2 3 44 1 t * PHN 9730 7, then gate 30 u / el gives a logic "1" which thereby blocks AND gate 24. This "1" is also applied to the NOR gates 38 and 40 which thereby issue a "0" to block gates 26 and 28, respectively. Finally, port 42 issues a "0" at terminal 52, which means that the processor in question cannot function as the ruler of the data bus (not shown here).

Likewise, it is possible, for example, that the processor in question has a "0" as the least significant bit of the priority number, while a logic "1" nevertheless appears on line 50. Then gate 42 on line 52 gives a logic "0". However, this is not decisive because it is possible that the processor in question has, for example, the priority number "0010", and the (one) other active processor has the priority number "0001". Then the signal must first come to rest on line 44; this is applied to line 46 via ports 30 and 24 when the signal comes to rest on it goes through ports 32, 38 and 20 26 to line 48. When the signal comes to rest on it, gate 34 is blocked from entering just like ports 30 and 32. "0" so that gate 40 receives 3 logic "0" signals. The generated "1" goes to port 28, but is stopped there. Likewise, in the port corresponding to port 28 in the other processor, the "1" is now blocked, bringing line 50 to potential "0". Only then does gate 36 issue a logic "0", whereby gate 42 on terminal 52 issues a logic "1" so that this processor can act as ruler on the data bus. The last 30 part still assumes that the processors are synchronous. It is clear that a lot of time can pass before the arbitration is completed. In addition, if the processors are out of sync, always wait for the slowest one.

35 THE ARBITRATION ACCORDING TO THE INVENTION.

Fig. 3 gives an example of an arbitration case according to the invention. The arbitration bus is eight bits wide and there are 5 processors A ..... E that 800 23 44 PHN 9730 8

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want to have access to the data bus. Column 70 gives the five priority numbers of the processors. In contrast to Fig. 2, the conductors of the arbitration bus form the bitwise AND function and thus the bit value "0" then indicates a higher priority than the bit value "1".

The sixth line gives the information that the arbitration bus carries. The arbitration occurs in an order of odd and even phases controlled by the corresponding positions of an undeclared cycle control.

10 Under the control of a start signal, the transmission of the priority number is started in each processor. In phase 1 (first odd phase), each processor's own priority number (column 70) is compared with the number formed on the arbitration bus. This comparison does not yield any agreement in this example. That is why all processors switch to phase 2 (first even phase).

In phase 2 (column 72) in each processor the most significant bit of the priority number is compared

2Q

with the corresponding bit formed on the arbitration bus.

For processors A, C and D there is agreement and nothing happens. There is a difference for processors B and E, so it is clear that these processors certainly do not generate the highest priority number on the arbitration box. Therefore, under the control of the "difference" signal thus generated, these processors no longer supply their priority number to the arbitration bus. This is realized by a so-called "tri-state" (three-state output buffer), which has one position in which the output is closed with high impedance.

Another solution is to apply a pseudo-priority number of only "1" bits to the arbitration bus. The inactive state of processors B and D is further indicated by crosses. These processors can now go into a waiting state. On the other hand, it is possible that they will carry out a further task, for instance because they contain several executable processes and a new process is activated. The present invention does not relate to the latter. The processors in which 800 2 3 44 7 PHN 9730 9 does detect an agreement are transferred to phase 3 (next odd phase).

The same takes place in phase 3 (column 74) as in phase 1. Again, the comparison nowhere yields any agreement, so that processors A, C, D switch to phase 4.

The same takes place in phase 4 as in phase 2, but now the second most significant bit of the priority number is included in the equation (column 76). For processors A and C there is a match and these are switched to phase 5. For processor D, there is a difference, and this processor no longer supplies its arbitrary bus with its priority number.

In phase 5 (column 78) the same takes place as in phase 1, 3, in which the information on the arbitration bus has changed due to the inactivity of processor D. For processor A, a difference is now detected in the comparison, and this processor should therefore be switched to phase 6 to compare the third most significant 20 bit of the priority number with the corresponding bit on the arbitration bus. This would again provide an agreement. Continuing in this way, a difference would only occur in phase 8 (when comparing the fourth most significant bit of the priority number), making processor A inactive. In the present case, however, phase 5 detects in processor C that the arbitration bus has generated the same number as its own priority number (arrow 80). This agreement signals that processor C is the "winner" of the arbitration in question. The "winner" signal is sent to all processors still active in the arbitration (in this case only processor A). Thus, the latter, like earlier processors B, D, E, is set to the inactive state. Processor C can then proceed to the operations to be performed in interval 56 of Fig. 1. In the exemplary embodiment to be discussed later, the phases 1/2, 3/4, etc., will be performed together in each case.

800 2 3 44 PHN 9730 10 THE CHOICE OF PRIORITY NUMBERS.

In the arbitration according to Fig. 3, the decision was made only in phase 5 '. Fig. 4 gives the choice of priority numbers to be able to effect this decision at an early stage 5. An arbitration bus with a width of four bits has been output. The first column gives the five possible priority numbers to always force a decision in phase 1. Here the "0" and "1" value can be interchanged. The priority number 10 "0000" is therefore related to the highest priority, the number "1111" to the lowest, when the arbitration bus again generates the AND function. It is possible to omit elements in certain processors. the processor with priority number "0000" without comparison immediately declares itself as "winner": the comparing means can therefore be dispensed with. The processor with priority number "0001" only has to compare the fourth, least significant bit, the processor with priority number "0111" need to perform d ^, comparison only for the last three bits 20 In many practical cases, however, all processors will always contain all the elements to arrive at a modular system: especially when the arbitration elements are realized in a single integrated circuit per processor this weighs heavily In a non-modular system, there are more possibilities to be able to win a winner here already in phase 1 with five different priority numbers jzen. For example, the fifth column gives five priority numbers. The. line 90 processor immediately designates itself as "winner". The processor of line 88 only detects whether the most significant 30 bit on the arbitration bus matches its own most significant bit: if so, it designates itself as the "winner". Line 86's processor does the same for the two most significant bits, line 84 for three, and line 82 for all four bits.

In a similar manner as the first column, the second column of fig. 4 gives the possible priority numbers whereby a decision is made at the latest in phase 3. The most significant bit here is arbitrarily 0 or 1, while for 800 2 3 44 / »((PHN 9730 11 the other three bits only the patterns 000, 001, 011, 111 are allowable. These are a total of 8 different priority numbers .

The third column of fig. 4 gives all possible 5 priority numbers, the decision being made at the latest in phase 5. The two most significant bits can be chosen arbitrarily as 0.1, while for the other two bits only patterns 00, 01, 11 are permissible. This yields a total of 12 different priority numbers.

10 The fourth column gives all possible priority numbers, whereby the decision is made at the latest in phase 7.

These are all 16 options.

It has been found that at n bits (here n = 4) in the priority numbers, where the decision must fall at the latest in the phase (2i + 1), a total of 9 = 21 (n + 1-i) different priority numbers are possible.

Fig. 5 gives a table of these numbers. The first column gives the number of bits of the priority numbers. In connection with the above, the top row gives the value of i. The figure shows the number of permissible priority numbers for the two parameters. For n = 5 and 32 priority numbers, the 9th phase provides the decision, to advance this time more and more priority bits are needed; finally 31 pieces to be able to decide in phase 1.

DESCRIPTION OF A PREFERRED EMBODIMENT.

Fig. 6 gives a preferred embodiment as a block diagram. The system contains an 8-bit data bus 124. This line 30 is also used as an arbitration bus. Furthermore, there is a control bus of 5 lines 126, 128, 130, 132, 134 (A, B, ΙΊ, X, Y). The A line is used by the current ruler of the data bus to indicate that a new arbitration can be initiated. The processor that has detected itself as "winner" uses line B to signal it to all other processors. The control lines Μ, X, Y are used to implement a three-wire synchronization gear (handshake). The M-line is controlled by the current ruler of the data bus at 800 23 44 PHN 9730 12. In case this ruler acts as a data transmitter, a signal indicates that the data on the data bus is valid. The X line and the Y line each form a "wired-AND" function 5 of the signals formed thereon by the processors. A logic "1" thus formed is used to start a subsequent basic synchronization operation (handshake).

Such a three-wire synchronization per se is described, inter alia, in the older Dutch Patent Application 7901156 (PHN 9351) of the same applicant.

The arrangement shown contains two processors. For the sake of simplicity, passive peripherals are not shown, as are possible further processors. Each processor includes elements 120 and 122, respectively, which perform the actual arbitration. Each processor further comprises a data processing device 121, 123 and 121 respectively, which is connected to the data bus 124 via lines 117 and 119, respectively. In addition, lines 113/117 and 115/119 can be common physical connections per processor. The data processing devices 121, 123 can be of conventional construction. The elements 120, 122 further include an incoming request line 136 and 140, respectively, for a request signal to be allowed to use data bus 124, and an acknowledge line 138 and 142, respectively, to signal that said request is initially permissible , and thus the system can transition to phase 56 in FIG. 1. In another embodiment, elements 120/121 and 122/123 can each be realized in a single device.

FIG. 7 shows a flow chart of performing an arbitration operation. Execution begins in block 150; this is the "start" operation. In block 152 the state variables are initialized in each processor: this is because the state of these variables is random when the supply voltage is switched on. This "cold start" is also effected under the control of a global "reset" signal that can be applied to all processors together. The system may also enter the loop 800 2 3 44 PHN 9730 13 if the current data bus "master" issues a start signal (warm start, block 151).

In block 154, the input variables are detected, i.e. the bits of the priority number present on the data / arbitration bus; these bits are stored locally in a read / write memory or register. In this way, they are only stored once when traversing the loop of this figure. In block 156, the logical functions of the different state variables described below are formed by combinatorial function formation. In block 158, the updated values of these state variables are stored in a read / write memory or a register. In block 160, the signals to be issued by the processor are updated. If the respective processor is "loser", it withdraws its priority number from the arbitration bus. If the respective processor is "winner", it signals this to all other processors. In particular, phases 2, 4 ... are thus implemented, while a functionally corresponding phase "0" is also implemented. In block 160 it is detected whether the processor in question will subsequently function as "ruler" of the data bus: this block therefore contains the aforementioned phases 1, 3 ..... In connection with the above, it is also noted that the result of the operation in block 160 does not depend on what the other processors in block 158 do, so that said phase "0" may come before "but functionally" after "block 160 in time". In block 162 it is detected whether any (other) processor has recognized itself as the "ruler" of the bus. If so (Y), the arbitration is terminated and the system can proceed to the next intervals (56 and further in Fig. 1) of a data transfer operation, by a stop action (164). If no "ruler" is recognized, the system goes back to block 154 to go through the loop again.

FIG. 8 is a time diagram of a three-wire toothing (handshake) system, using lines Μ, X and Y of FIG. 6. Line M is controlled by the "ruler" of the bus alone? the control 800 2 3 44 PHN 9730 14 of the X, Y, lines is done by all other communicating processors together; in some cases this may also concern only a single processor. Each time a cycle is initiated by a .signal.

/. transition on line M. With a falling edge on line M, all other processors give a positive signal edge on line Y. The capillary relationship is indicated by an arrow. After the switch-on phenomena have died out, line Y then carries a high signal. Dashed lines indicate that some of the other processors are responding earlier. Due to the fact that line Y of all signals generated on it also forms the logical AND function, this only becomes noticeable as a potential change of the line when the latter responds. When the "ruler" processor detects the transition on line Y, it itself emits an ascending edge on line M.

All other processors respond to this with a signal edge on line X, and also with a descending signal edge on line Y. All other processors always ensure that they only deliver a high voltage on at most one of the two lines X, Y. The intervals with an O.K. Arrow 20 are characterized in that the state of the data or arbitration bus is then defined: all other processors have their output information on the bus, respectively, and recorded the information thereof.

Such a three-wire synchronization gear has become known per se because of its application in the IEEE 488 Standard bus. For the sake of simplicity, the finite steepness of signal transitions has been neglected above.

After the foregoing, figs. 9a-9f six time diagrams concerning signals in an arbitration operation.

Figs. 10a-10f show six state diagrams regarding the different processors participating in such an arbitration operation.

First, FIG. 9f the interaction between the actual arbitration module (eg element 120 in Fig. 6) and the downstream data processing device (eg element 121). The first line gives the request signal on line 136, the second line the permission signal on line 138. The request signal goes high 800 2 3 44 PHN 9730 15 to start the arbitration phase (54 of FIG. 1). If the transport operation (phases 56, 58, 60) is allowed, the signal on the permission line becomes high. After the end of the transport operation, the request signal goes low: then the release phase can start (62). When this too is completed, the consent signal goes low and a next arbitration operation (64) can be started again when the request line goes high. The signaling ACK is formed by the positions S8, S9 in FIG.

10 10c (see below).

Of the processors, one is predestined to initial ruler by a fixed wire signal. This initial state is activated, for example, by a global reset signal, for example after switching on the supply voltage. Therefore, all processors are put in the combination of positions S1, S6, S8, S10, S15, S22, which are shown in Figs. 10a-10f are shown. The positions of each of these figures separately can be defined by a number of register bits, in which a logical state in a register is detected in a conventional manner by means of a decoder connected to the bottom, for example, the five positions in Fig. 10a will be detected by at least three register bits. are being displayed . When the reset signal has expired, arbitration can begin after all processors have also assumed the above six initial positions. For the time being, the outgoing line A has been "1" in all processors; also the B, M and X lines are "1" (Fig. 9a indicating the start of the arbitration). After a "reset" signal, Y = 1 is also always, which is shown in FIG. 9a by a broken line. In addition, the arbitration bus on all 8 lines is controlled with a "1": D (0: 7) rl. After the end of the reset signal (RESET), all processors then go from position S1 to position S2 (A1 is true, that is, line A carries a "1", and also the initialization of the relevant module is completed, that Vil I say is true). This is shown in Figure 10a, which indicates the overall state of affairs with respect to the successive stages of the arbitration decision. Position S2 then means: "I am ready 800 2 3 44 PHN 9730 16 to decide". Stand SI has the character of a hold.

Then, the initial "elder" processor goes from state S1Q to state S12, because state S9 is not "5". After all, I = IM = X = Y = 1, while he left position SI (sT). The ruler has thus manifested itself as such, it appears from the table in Fig. 9d that in position S12 the signal on line A becomes "0" (see also Fig. 9a). Generally, FIG. 9d refers to the "ruler" portion of the three-ten wire synchronizing gear. Then, the initial ruler goes from position S15 to position S16, because he has left position S10 (S10 is true) and I and IM are also true. In position S16, the "initial ruler" sends a "0" on the Y line, which transition is shown in broken line in FIG. 9a, whereupon all other processors also move from position S15 to position S16, because I and Y1 are both Thus, the initialization of the entire arbitration system has ended: position S15 has no role thereafter. If a request signal is now generated, arbitration begins. 20 The procedure described below is carried out, both if only one single processor, as if multiple processors produce a request signal If a request arises, the respective processor moves from state S16 to S17 The respective Fig. 10e shows of the three wire synchronization gear in particular the "non-ruler" part In position S17 the signal on the line X also becomes zero .. In Fig. 9a it is indicated by the dotted lines that this is due to the different processors with mutually different delay times and furthermore with a time of 30d. Some steepnesses are being realized. Then, all processors that do not produce a request signal from state S2 go back to state SI for as long as the arbitration lasts (this also applies to the ruler). At the same time, the arbitrating processors go from position S6 to position 35 S7, because 2e have both position S2 and position S17. Position S7 controls the supply of the entire priority number to the arbitration bus (see Fig. 9a, bottom line), in which 800 2 3 44 I PHN 9730 17 indicate the oblique parallel stripes that indicate the signals on the different lines of the arbitration bus. can change at different times and in different directions. When these signals have settled, some of the lines of the arbitration bus can carry a high signal and others a low signal. (This is indicated by a double-running line at the bottom right in Fig. 9a). Then (with different delay times) all processors participating in the arbitration go from mode S17 to mode S18 (Fig. 10e), making the signal on the Y line high again; because positions S7 and S2 are "true".

A little earlier (on the basis of positions 56 and SI), the processors not participating in the arbitration had also gone to position S18, so that after some time the signal on line Y becomes 15 again (Fig. 9a), then all processors go from position S22 to position S23. The positions S23 to S30 form, as it were, a counter. Also, the "prevailing" processor goes from state S12 to state S13, causing line M to become low (Fig. 9a). Subsequently, all processors 20 go from state S18 to state S19, and the processors participating in the arbitration to state S3 (after all, the others are in state Sli). In S3 it is decided on the "winner" and the "losers" of the arbitration, respectively. For this purpose, the combinatorial functions "g" and "h" are first evaluated. Both of these functions are defined in the box in Fig. 10a. The function "g" indicates whether the bit indicated by the position of the counter of Fig. IQf of the priority number differs from the relevant bit present on the arbitration bus. The function "h" indicates whether there is just equality between all bits of its own priority number (pO ...... P7) and the corresponding bits on the arbitration bus (D10 ...... D17). The logical function h.g therefore cannot be true. Figures 9b and 9c now show the sig needle diagrams for an "odd" and an "even" decision stroke of the arbitration, respectively. These are distinguished from each other only by the polarity of the signal on the line M and the interchange of the signal patterns on the lines X and Y.

800 2 3 44 PHN 9730 18

If now the function "g" is true and the processor was in position S19, it means that it can never become the arbitration winner and thus goes back to position SI.

If the function "h" is true and the processor was in position S19 5 then it is the "winner" and goes to position S5. If neither function "g", "h" is true and the processor was in position S19, the situation for the processor in question is undecided and goes to position S4 (another processor may have identified itself as "winner") "and 10 have gone to position S5).

Figures 9b, 9c now indicate the situation that no "winner" has been recognized. In Fig. 9b the signal on line M first goes low (see also Fig. 9a). The following happens with regard to the still participating processors.

From position SI9 they first go to position S16 because S4 is "true": then the signal on the X-line becomes "1" again. Therefore, if the X and Y lines are both low, one or more participating processors can take back their priority number, whereby the potential of the different lines of the arbitration bus can change. This is indicated in fig. 9b in the same way as in fig. 9a. Under control of position S16, the still participating processors go from position S4 to position S3 (for a next decision round) and from position S23 to position S24 (the latter changes the ranking number of the bit to which the function "0" refers). , the "ruler" processor goes from position S13 to position S12, because the X-line is high and the Y-line is low: as a result, the line M becomes high again, and the odd decision stroke (first, third, etc.): When M goes high again, it is also the beginning of the next even decision stroke (second, fourth, etc.). All still participating processors first go from position S16 to position S17 (A1 and S2 are false): X becomes low again: from position S17 the actual decision is now taken to go to positions S1, S4, 35 and S5, respectively. Then (if no winner is present) the signal on line Y becomes 1 again in position S18, in signal S13 the signal on line M returns to 0 and the even decision phase has ended. Under control of position S18, 800 2 3 44 * PHN 9730 19 position S25 is also reached. For instance, a decision is made twice when going through positions S16 to S19.

If in the foregoing it is detected by another processor 5 that he is the winner, this position reaches Ξ5, whereby the signal on line B becomes low: this is indicated by a broken line in fig. 9b, 9c. When this happens, the other processors immediately leave position S3 upon reaching positions S17 and S19, and go to position S1. Furthermore, in Fig. 10e they either go directly to position S16 (under control of position S4), or via positions S18, S19 to position Slé, as will be explained later.

Fig. 9d, 9e gives the end of the arbitration in 15 and an odd and an even decision stroke.

v

Fig. 9d thus forms the continuation of FIG. 9b: So the decision was made while all participating processors were in positions S3, S7, S8 and S19. The winning processor thus goes to position S5, as a result of which the signal on line B becomes zero 20: this processor then also goes back to the starting position Sé, whereby it withdraws its priority number from the ar-bitrabus. All other processors go to position Slé either under control of position S4 or under control of position S6. They achieve the latter because 25 can successively be reached from position S3 first from position S3 and thereby again from position Sé. The line X thus becomes "1". The "old" ruler of the arbitration now moves from position S13 to S12, making line M high. All processors now go to position S17, making line X low.

They then reach position S18 because Sé is true and S2 is false, and line Y becomes high. The old ruler of the arbitration now moves to position S14, making the signal on line M low. Under control thereof, all still participating processors go to position S19 and then to position 35 Slé, whereby line Y first becomes low, and then line X becomes high. Then the old ruler can move to position SltjA, in which he makes line A high again. The latter results in all processors going to position S22 (fig. 10f) 800 23 44 PHN 9730 20 and the old ruler going to position S10. As a result, he makes line M high again and is therefore no longer recognizable as ruler. The new ruler is thus known and can proceed to the previously discussed selection phase. A further consequence is that all processors come to position S2 (except for the new ruler who is in position S5). Finally, the new ruler enters position S9, in which it generates the consent signal for its own data processing device (Fig. 10c). Furthermore, under the control of position S9, the new ruler enters position Sll via position S10.

A subsequent arbitration can be started when the request signal from the data processing device belonging to the new ruler disappears. Then the procedure according to Fig. 9a is restarted, however, the signal on line Y is low from the beginning. The following transitions then occur: S9 S8, S5 -> S2,

Sll -S12.

Fig. 9e gives a pendant of fig. 9d, whereby the winner, however, designates himself in position S17. Then only the positions S18 and S19 need to be passed through before S16 is reached. The procedure is therefore slightly faster.

25 30 35 800 2 3 44

Claims (3)

Calculator system, comprising a number of first processors (120/121, 122/123) which are interconnected by: a. A data bus (124) to each time transport a multi-bit data word in parallel between a first processor and at least one further design of the calculator system; b. a control bus (126, 128, 130, 132, 134) containing a number of parallel-connected control lines; wherein each processor is provided with first means (57) for supplying its multi-bit priority number to a multi-bit arbitration bus interconnecting the processors before realizing a desired data transport, and the arbitration bus is provided with second means for in the case of a plurality of priority numbers received together, by means of forming a logical function per significance level of the bits thereof, determining the highest priority number therefrom and supplying a permission signal to the associated processor, excluding further processors characterized in that each processor includes 20; c. detection means (SI) for a start signal to then supply its priority number to the arbitration bus for a data transport desired by that processor, and a cycle tracking element (Fig. 9f) with a series of a number of positions, which is by said start signal in the first position of said series (S23) and by a progress signal in a next position of the series; d. a comparison element (S3), in each case under control of a position of the cycle tracking element, in each case comparing its own priority number with the priority number formed by means of said logic function on said arbitration bus, and, in case of equality, a "winner" signal (S5) to shape; e. in order to control, in control of a position "p" of said series 35 of positions of the cycle tracking element, the bit (p = 1, 2 ....) from the top of the own priority number with the corresponding priority number in the significance level p 800 2 3 44 PHN 9730 22 bit formed on the arbitration bus, and in the absence of said "winner" signal equally to form said "progress" signal (S4), but in case of inequality said first means can be deactivated (SI) ; 5 f. a second detector to detect any "winner" signal (B = 0) generated in said calculator system by another processor and then deactivate said first means; 9. third means (117, 119) for realizing the desired data transport under the control of its own "winner" signal and, at the end thereof, for starting said signal first. forms, for feeding to all / processors of the calculator system. Calculator system according to claim 1, characterized in that from said starting signal up to said "winner" signal the data bus functions as an arbitration bus. Calculator system according to claim 1 or 2, characterized in that for a priority number of n bits (pl ...... pn), in which pl is the most significant, the priority numbers are chosen from the set: (pl ....... pi, pi + 1 ........ pj, pj + 1 ....... pn), with i ^ 0, j ^ 1 + 1> y ^ n where the bits (pl ..... pi) can have an arbitrary value, the bits (pi + 1 ..... pj) all have the lowest bit value and 25 the bits (pj01 ....... pn) all have the highest bit value, where i has the same value for all processors and j has a selectable value, so that the set has at most a number of 9 = 21. (n + 1 - i) contains 30 elements to be used, and that the number of positions of said series is at least equal to (i + 1). 35 800 2 3 44