JPS593774B2 - Conflict handling method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a contention processing method, particularly to a contention processing method in a system in which a plurality of devices compete to occupy a set of signal buses.

2. Description of the Related Art In many information processing systems, a configuration is adopted in which a central processing unit, a main storage device, an input/output control device, etc. mutually exchange information via a set of signal buses.

Since it is impossible for this type of signal bus to handle multiple sets of information exchanges at the same time, the devices that require information exchange compete with each other, and any device with priority will monopolize the signal bus and displace other devices. After the communication is blocked, the desired information exchange is executed. Other devices that require information exchange will wait until the information exchange is completed and the signal bus is unblocked. FIG. 1 is a diagram showing an example of a conventional competition processing method for this type of signal bus.

In FIG. 1, a central processing unit 1 and an input/output control unit 21
, 22 and 23 are connected by a common signal bus 5, and each input/output control device 21, 22 and 23 competes with each other while occupying the signal bus 5 and exchanges information with the central processing unit 1. do. The input/output control devices 21, 22, and 23 that wish to occupy the signal bus 5 store the request signal R in their respective request registers 31, 32, and 33, and all the input/output control devices 21, 22, and 23 The request signal R is delivered to the central processing unit 1 via a single request line 3 shared by the central processing unit 1. Any one of the central processing units 21, 22, and 23 that received the request signal R from the request line 3 receives the signal bus 5.
It is determined that the permission signal A is stored in the permission register 2, and each input/output control device 21, 22 and 2
The permission signal A is sent to the permission line 4 which connects 3 in a chain.
The permission signal A first reaches the input/output control device 21 via the permission line 4. The input/output control device 21 receives the request signal R.
, the switching circuit 41 is activated and the permission line 4 is sent out.
The permission receiving circuit 51 receives the permission signal A arriving from the. In this case, the permission signal A is not transmitted to the input/output control devices 22 and 23 via the permission line 4. If the input/output control device 21 does not send out the request signal R, the permission signal A that has reached the input/output control device 21 will be sent to the input/output control device via the inoperable switching circuit 41 and the permission line 4. Reach 22.

When the input/output control device 22 is sending out the request signal R,
The switching circuit 42 is operated, and the permission receiving circuit 52 receives the permission signal A coming from the permission line 4. In this case, the permission signal A is not transmitted to the input/output control device 23 via the permission line 4. If input/output control devices 21 and 2
2 has not sent out the request signal R, the permission signal A that has reached the input/output control device 22 reaches the input/output control device 23 via the inoperable switching circuit 42 and the permission line 4. In this case, the input/output control device 23 that is sending out the request signal R receives the permission signal A by the permission receiving circuit 53 via the switching circuit 43 in operation. Any one of the input/output control devices 21, 22, and 23 that receives the permission signal A closes the gate 61, 62, or 63, occupies the signal bus 5, and exchanges information with the central processing device 1. . As is clear from the above explanation, in the conventional contention processing method, the input/output control device 21 always has the highest priority in receiving the permission signal A sent from the central processing unit 1, and the input/output control device 21 has the highest priority. The device 22 has the highest priority, and the input/output control device 23 has the lowest priority.

Therefore, a request for occupancy of the signal bus 5 is sent to each input/output control device 21,
22 and 23, the input/output controller 21
is always occupied with the highest priority, and the input/output control device 23 is always forced to wait. In order to equalize the priorities of the input/output control devices 21, 22, and 23, there is no other way than to change the chaining order of the permission lines 4 as appropriate, such as providing a plurality of permission lines 4 with different chaining orders and switching them. Requires complex and uneconomical measures. An object of the present invention is to eliminate the drawbacks of the conventional contention processing method as described above, and to enable the occupancy priority of each device sharing a set of signal buses to be easily changed without providing many permission lines. The goal is to realize a conflict handling method.

The purpose of this is to send the request signal to each device in a system including a plurality of devices that compete with each other to occupy a set of signal buses, and is equipped with a means for sending a request signal to a shared request line. means for detecting the presence of a request signal on a line; means for alternately connecting the request signal sending means and the request signal detecting means to the request line at an adjustable period specific to each device; and the request signal detecting means. means for prohibiting the transmission of the request signal when the request signal is detected by the request signal; and means for prohibiting the transmission of the request signal when the request signal reading means does not detect the request signal in the next cycle after the request signal sending means operates. This is accomplished by providing means for determining the request signal and continuously operating the request signal sending means during the occupancy period.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a diagram showing a conflict processing method according to an embodiment of the present invention, FIG. 3 is a diagram showing a conflict processing circuit shown in FIG. 2, and FIG. 4 is a diagram for explaining the operation of FIG. FIG. 3 is a signal sequence diagram. As in FIG. 1, in FIG.
, 22 and 23 compete with each other to occupy the signal bus 5 and exchange information with the central processing unit 1. Input/output control devices 21, 22, and 2 that wish to occupy the signal bus 5
3 sends a request signal R from competition processing circuits 71, 72 and 73 to the shared request line 3. However, the input/output control device 21, 22, or 23 that sent out the request signal R receives a permission signal A that determines that it is permitted to occupy the signal bus 5, and sends the permission signal A from the central processing unit 1 to each input/output control device. 2
1, 22, and 23 does not exist, and the competition processing circuits 71, 72, and 73 included in each input/output control device 21, 22, and 23 monitor the signal state of the request line 3. It is determined whether the signal bus 5 can be occupied.
Next, the operation process of the competition processing circuit 71 will be explained with reference to FIGS. 3 and 4, focusing on the input/output control device 21. Third
In the figure, a competition processing circuit 7 included in the input/output control device 21 is shown.
1 is shown, other input/output devices 22 and 23 (not shown) are also provided with competition processing circuits 72 and 73 of the same type, and are connected to the request line 3.

The contention processing circuit 71 serves as a king as a request signal R sending unit 81.
．． It is composed of a reading section 91 and a pulse circuit 13. The pulse circuit 13 has a period specific to the input/output control device 21 as shown in FIG. 4, that is, odd time intervals Tl, T3, T5.
,..., logic becomes 1 at T37, even time interval T2
, T4, T6, . . . The pulse train P1 which becomes logic 0 at T38 is output. Note that a pulse circuit (not shown) in the input/output control device 22 generates a pulse train P2 having a period of 3 time periods as shown in FIG.
The pulse circuit (not shown) in FIG.
A pulse train P3 whose period is a time interval is output. In FIG. 3, normally the gate 4 is in a conductive state, and the pulse train P1 outputted from the pulse circuit 13 makes the gates 83 and 93 conductive alternately every hour, and the sending part 81 and the reading part 91 are connected to the pulse train. It is possible to alternately interlock with request line 3 in synchronization with P1. Current interval T, input/output control device 2
1, when a request to occupy the signal bus 5 occurs, the contention processing circuit 71
The occupancy request signal Q1 is inputted to the logic 1 through the path 11 of the occupancy request signal Q1.
On the other hand, since no request signal R is sent from any input/output control device during the time period T1 (the request line 3 is +V, V), the transistor 92 of the reading section 91 converts the no-signal state into the gate 9.
3 to the counting control section 94. The counting control section 9
4 outputs a logic 1 to the path 97 and makes the gate 85 conductive, so the occupancy request signal Q1 is output to the request register 84.
is set to logic 1. When the time interval T2 is reached in this state, the gate 83 becomes conductive, the output of the request register 84 is input to the transistor 82, and the request signal R (0v) is sent to the request line 3. Furthermore, when the time interval T3 is reached, the gate 83 is blocked, so the request signal R stops being sent out, and the gate 93 becomes conductive, so the reading section 91 reads the request line 3 again.
Linked with. Since the request signal R is not sent from the other input/output control devices 22 and 23 to the request line 3 during the time interval T3, the transistor 92 of the reading section 91 detects the no-signal state through the gate 93 to the counting control section. 94. When the counting control unit 94 receives a no-signal state again following the time interval T1, it outputs a logic 1 to the path 95. The logic 1 output blocks the gate 14, which has been in the conductive state up to the husband, and the gate 83 continues to be in the conductive state, so that the request signal R is continuously sent to the request line 3. That is, the input/output control device 21 receives the occupation request Q of the signal bus 5 generated in the time interval T1,
On the other hand, by sending the request signal R from the competition processing circuit 71 to the request line 3 in the time interval T2, and detecting a no-signal state on the request line 3 in the following time interval T3, it is determined that the occupancy request Q1 has been satisfied. Considering this, the request signal R is continuously sent to the request line 3 from the time interval T4, and the signal bus 5 is occupied. Time interval T8
When the occupation of the signal bus 5 ends, a termination signal is input to the path 12, the request register 84 is set to logic 0 via the gate 86, and the request signal R being sent to the request line 3 is stopped.
Release signal bus 5. In addition, the counting control section 94 is restored by the end signal, and the output to the path 95 is erased to make the gate 14 conductive again, and the pulse train P is again turned on.
1, the sending section 81 and the reading section 91 are made alternately interlocked with the request line 3. Next, in the time interval Tl, occupancy requests Ql, Q2, and Q3 for the signal bus 5 are generated in all the input/output control devices 21, 22, and 23.

During the time interval T, l, the competition processing circuit 71 of the input/output control device 21 detects that the request line 3 is in a no-signal state by the reading section 91, and prepares to send out the request signal R from the sending section 81. Subsequently, in the time interval Tl2, the competition processing circuit 71 sends the sending unit 8
1, a request signal R is sent to the request line 3. Similarly, the competition processing circuit 72 of the input/output control device 22 detects the no-signal state of the request line 3 in the time interval Tll, and
3, a request signal R is sent to the request line 3. Furthermore, the contention processing circuit 73 of the input/output control device 23 outputs a request line 3 to the time interval T, l.
Detects the no-signal state of time intervals T, 2, Tl3 and T
, 4, and sends a request signal R to the request line 3. On the other hand, the competition processing circuit 71 of the input/output control device 21 stops the request signal R from the sending circuit 81 during the time period T, 3, and causes the reading section 91 to interlock with the request line 3; Control device 22
Since the request signal R is being sent from 23 and 23, the transistor 92 of the reading section 91 detects the request signal R and transmits the signal detection state to the counting control section 94 via the gate 93. The counting control unit 94 outputs a logic 1 to a path 96,
Logic 0 is set in the request register 84 through the gate 86 of the sending section 81, and the request signal R is not sent from the sending section 81 to the request line 3 during the time interval T,3. That is, after sending the request signal R in the time interval Tl2, the request signal R is sent to the request line 3 in the time interval Tl3.
By detecting this, it is determined that the request for occupancy of the signal bus 5 cannot be satisfied yet, and the signal state of the request line 3 is monitored at a specific period according to the pulse train P, and waits for an opportunity to send the request signal R again. . Similarly, the input/output control device 22 also has a time interval Tl2.
After sending the request signal R to the request line 3 at Tl3, the signal state of the request line 3 is monitored in the time interval Tl4, and the request signal R sent from the input/output control device 23 is detected, and if the signal bus 5 is still occupied. It is determined that the request cannot be met, and the signal state of the request line 3 is monitored at a specific period according to the pulse train P2, and an opportunity to send out the request signal R again is waited for. On the other hand, input/output control device 23
sends the request signal R to the request line 3 in time intervals Tl2, Tl3, and Tl4, and then monitors the signal state of the request line 3 in the time interval Tl5, but the input/output control device 2
Since the request signal R is not sent from 1 or 22,
It is determined that the signal bus 5 occupancy request Q3 has been satisfied, and the request signal R is continuously sent to the request line 3 from the time interval Tl6 to occupy the signal bus 5 and perform information exchange. That is, the time interval Tl,
The input/output control device 2 simultaneously requests occupation of the signal bus 5.
Among the input/output control devices 1, 22, and 23, the input/output control device 23 having the pulse train P3 occupies the signal bus 5 with the highest priority. When the input/output control device 23 finishes occupying the signal bus 5 in the time period T22 and the request signal R being sent to the request line 3 stops, the input/output control device monitors the signal state of the request line 3 in the time period T23. 21 and 22 detect a no-signal state, the input/output control device 21 sends the request signal R to the request line 3 in the time period T24, and the input/output control device 22 sends the request signal R in the time period T24 and T25. Send to request line 3.

The input/output control device 21 monitors the signal state of the request line 3 during the time interval T25, but detects the request signal R being sent from the input/output control device 22, and determines that the occupancy request Q1 of the signal bus 5 cannot be satisfied yet. Then, the transmission of the request signal R in the time interval T26 is stopped, and the signal state of the request line 3 is monitored again in synchronization with the pulse train P1. On the other hand, the input/output control device 22
6, it monitors the signal state of request line 3, detects that there is no signal, judges that the occupancy request Q2 of signal bus 5 has been satisfied, and continuously sends request signal R2 to request line 3 from time interval T27. The signal bus 5 is then occupied and information is exchanged. That is, among the input/output control devices 21, 22, and 23 that requested occupancy of the signal bus 5 during the time interval Tll, the input/output control device 22 having the pulse train P2 occupies the signal bus 5 with priority next to the input/output control device 23. do. Occupancy of the signal bus 5 by the input/output control device 22 ends in time interval T30, and the request line 3
When the request signal R that is being sent is stopped, only the input/output control device 21 issues the occupancy request Q1 of the signal bus 5 after the time period T3l.
The signal bus 5 is occupied and information is exchanged in the same process as in time interval T1. That is, among the input/output control devices 21, 22, and 23 that requested the occupation of the signal bus 5 during the time interval Tll, the input/output control device 21 having the pulse train P1 occupies the signal bus 5 with the lowest priority. As is clear from the above description, according to this embodiment, the input/output control devices 21, 22, and 23 that share the signal bus 5 each have a pulse train P, , P of a natural period.
2 and P3, the input/output control device 23 is given the highest priority and the input/output control device 21 is given the lowest priority to the request for occupancy of the signal bus 5.

The periods of the pulse trains Pl, P2, and P3 of each input/output control device 21, 22, and 23 are determined by each competition processing circuit 71.
, 72 and 73 by adjusting the pulse circuit 13 and the like. Therefore, the pulse trains Pl, P
By changing the cycles of P2 and P3, the priorities given to the input/output control devices 21, 22, and 23 can also be easily changed. However, the occupancy of the signal bus 5 according to the priority order is determined by only one request line 3, and other lines such as a grant line are not required. In addition, Figures 2 to 4
The figure is merely one embodiment of the present invention; for example, the number of input/output control devices that share the signal bus 5 is not limited to three, and the effects of the present invention do not change even if there is an arbitrary plurality of input/output control devices. Furthermore, the effects of the present invention do not change even if the device that shares the signal bus is not limited to the input/output control device. As described above, according to the present invention, a plurality of devices that compete to occupy a signal bus can determine their request and occupancy using a single shared request line, saving control lines, and signal Since the priority order for occupying the bus is determined, the priority order can be easily adjusted by changing the natural period.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional conflict processing method, FIG. 2 is a diagram showing a conflict processing method according to an embodiment of the present invention, FIG. 3 is a diagram showing the conflict processing circuit shown in FIG. 2, and FIG. This figure is a signal sequence diagram for explaining the operation of FIG. 2. In the figure, 1... central processing unit, 2...
... Permission register, 21, 22, 23 ... Input/output control device, 3 ... Request line, 31, 32, 33
...Request register, 4...Permission line, 4
1, 42, 43... switching circuit, 5...
Signal bus, 51, 52, 53... Permission receiving circuit, 61, 62, 63... Gate, 71, 72,
73... Competition processing circuit, 81... Sending section, 91... Reading section, 13... Pulse circuit, 82, 92... transistor, 83,8
5, 86, 93, 14... Gate, 94...
... Counting control section, 11, 12, 95, 96, 97...
...Route, Q,, Q2, Q3...Occupation request (signal), Pl, P2, P3...Pulse train, R
...Request signal.

Claims (1)

[Claims] 1. In a system that is equipped with a means for sending a request signal to a shared request line and has a plurality of devices competing to occupy a set of signal buses, each of the devices is provided with a means for sending a request signal to the request line. means for detecting the presence of a signal; means for alternately connecting the request signal sending means and the request signal detecting means to the request line at an adjustable period specific to each device; and the request signal detecting means detecting the request signal. means for prohibiting transmission of the request signal when detecting the request signal, and determining that the signal bus can be occupied when the request signal reading means does not detect the request signal in the next cycle after the request signal sending means operates; and means for continuously operating the request signal sending means during the occupancy period.