JP3481445B2 - Competition mediation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contention arbitration method, and more particularly to a contention arbitration circuit for contention arbitration at the time of transfer of an independent element between a plurality of processors and a memory and a plurality of processors as an internode connection device. The present invention relates to a contention arbitration method for performing contention arbitration together with data transfer between a plurality of nodes connected via the same.

[0002]

2. Description of the Related Art In the conventional contention arbitration method, the object of arbitration is often a transfer request to one type of transfer destination.
In the case of the case described in "Japanese Patent Laid-Open No. 6-195313", a device capable of coping with various cases is incorporated. However, basically, it is possible to prevent the disorder of the priority order in all priority circuits by using the function of switching the priority order for the transfer request function to one type of transfer destination, and the deterioration of the access performance due to contention. However, it does not support an example in which the target of arbitration is a transfer request to a plurality of types of transfer destinations.

As an example of a transfer request to a plurality of types of transfer destinations, the structure is different from that of "Japanese Patent Laid-Open No. 6-195313".
An example of a conventional competitive arbitration circuit for high-speed crossbar switch control is shown in the circuit diagram of FIG.

This conventional high-speed crossbar switch control contention arbitration circuit is applied to a conventional information processing apparatus for performing the same service as that of the present invention shown in the block diagram of FIG.

First, the configuration of FIG. 6 will be described. As a whole, a plurality of processors 100, 101, 102, 1
03, a memory 104 shared by the processors 100, 101, 102, 103, and the processors 100, 1
The crossbar network 105 that connects 01, 102, and 103 and the memory 104 is a unit node, and this node is an information processing device that is connected to a plurality of nodes via an internode connection device 106. Further, in the crossbar network 105, input buffers 107, 108, 109, 110 provided corresponding to a plurality of processors, and transfer of independent elements between the plurality of processors 100, 101, 102, 103 and the memory 104, respectively. Time arbitration and processors 100, 101, 102, 1
03 instructs the contention arbitration circuit 111 that outputs a select signal by also performing contention arbitration during data transfer with a plurality of nodes connected via the internode connection device 106, and the transfer output by the contention arbitration circuit 111. A plurality of input buffers 107, 108, 109, 11 according to the select signal
The data selector section 112 selects one element from elements sent from 0 and outputs it to either the memory 104 or the internode connecting device 106.

Next, the configuration of FIG. 7 will be described. The input buffers 107 to 110 are connected to a processor (not shown), receive transfer request data, and output data and element consecutive number information (hereinafter referred to as TAG). The request type recognition circuit 113 receives the TAGs from the input buffers 107 to 110, sets “1” in the bit corresponding to the requested port, and sends it to the selector 114. The selector 114 uses the output of the logical sum circuit (hereinafter referred to as OR) 115 as a select signal and selects the output of the request type recognition circuit 113 when it is "0", and selects the output value of the register 116 when it is "1". The priority encoder 117 is a fixed priority type. Inverter 118
Is an inverted value of the output value of the priority encoder 117. The logical product circuit 119 includes the selector 11
The logical product of the output value of 4 and the output value of the inverter 118 is calculated. The register 116 inputs the output value of the logical product circuit 119, and the OR 115 takes the logical sum of the register output values. The distribution circuit 120 distributes the output of the OR 115 into 4 bits and outputs it as a Hold signal.

Next, the operation will be described. FIG. 8 is an operation diagram showing the operating state of the input buffer in clock units, and FIG. 9 is an explanatory diagram showing the bit state of each signal for each clock. 6 to 9 will be used for the description.

First, it is assumed that at the timing of clock 0, "0000" is buffered in the register 116 and the request as shown in FIG. 8A is buffered in the input buffers 107-110. Where A1, A
2, D1 and D2 are 2 element continuous 2T requests, and
1, B2, B3, B4, C1, C2, C3 and C4 indicate 4T requests of four consecutive elements.

At clock 1, the value of register 116 is "0".
Since it is 000 ", the output value" 0 "of the OR115 is distributed by the distribution circuit of 701 and is output as a Hold signal of" 0000 ". The input buffers 107 to 110 each receive the Hold signal of" 0 ", Request group A1, by sliding the buffered contents one step
B1, C1, and D1 are output to the contention arbitration circuit 111 and the data selector 112. The state of the input buffer at this time is shown in FIG. In the contention arbitration circuit 111, the request type recognition circuit 113 receives the information portion of each request (hereinafter referred to as TAG). The request type recognition circuit 113 identifies the TAG and outputs "1111" because all the requests are valid. The selector 114 inputs the output value of the OR 115 whose value is “0” as the select signal, and outputs the output value of the request type recognition circuit 113 ”.
1111 ”is selected and the priority encoder 117 is selected.
To enter. Priority encoder 117 has "1"
111 "is input, arbitration is performed according to a specific priority, and" 1000 "is output as a select signal. At this time, the priority encoder 117 determines that the leftmost bit of the input 4 bits has the highest priority. In the data select 112, the select signal "100 output from the priority encoder 117
0 "is input to select the data A1 of the input port # 0 and output it to the internode connecting device 106. Inverter 3
02 is the inverted value “0111” of the select signal “1000”
Is output. The AND circuit 303 outputs the output value “1111” of the selector 114 and the output value “011” of the inverter 302.
The logical product of "1" is obtained and "0111" is output to the register 116. The state at this time is shown in clock 1 of FIG.

At clock 2, the value of the register 116 is "0".
Since it is "111", the output value of the OR115 is "1", and "1111" is output as the Hold signal. In the input buffers 107 to 110, the Ho values "1" are output.
Since the Id signal is received, the states of the input buffers 107 to 110 do not change. The selector 114 outputs O as a control signal.
The output value "1" of R115 is input and the value "0111" of the register 116 is selected. The priority encoder 117 inputs the output value “0111” of the selector 114 and outputs “0100” as a select signal. The data selector 112 receives the select signal “0100”, selects the data B1 in the input buffer 108, and outputs it to the internode connecting device 106. The inverter 118 receives the select signal and outputs the inverted value “1011”.
The AND circuit 119 outputs the output value “011” of the selector 114.
1 ”is ANDed with the output value“ 1011 ”of the inverter 118, and“ 0011 ”is output to the register 116.
The state at this time is shown as clock 2 in FIG.

At the timing of clock 3, since the register value is "0011", the output value of OR115 is "1", and "1111" is output as the Hold signal. Each of the input buffers 107 to 110 has a Ho value of "1".
Since the Id signal is received, the state of the input buffer does not change. The selector 114 inputs the output value “1” of the OR 115 as a control signal and selects the value “0011” of the register 116. The priority encoder 117 inputs the output value “0011” of the selector 114 and outputs “0010” as a select signal. The data selector 112 receives the select signal “0010” and receives the input buffer 1
The data C1 of 09 is selected and output to the internode connecting device 106. The inverter 118 inputs the select signal and outputs the inverted value “1101”. AND circuit 119
Is the output value “0011” of the selector 114 and the inverter 1
The logical product with the output value "1101" of 18 is calculated and "000"
1 "is output to the register 116. The state at this time is shown as clock 3 in FIG.

At the timing of clock 4, since the register value is "0001", the output value of OR115 is "1" and "1111" is output as the Hold signal. Each of the input buffers 107 to 110 has a Ho value of "1".
Since the Id signal is received, the state of the input buffer does not change. The selector 114 inputs the output value “1” of the OR 115 as a control signal and selects the value “0001” of the register 116. The priority encoder 117 inputs the output value “0001” of the selector 114 and outputs “0001” as a select signal. The data selector 112 receives the select signal "0001" and receives the input buffer 1
The data D1 of 10 is selected and output to the internode connecting device 106. The inverter 118 receives the select signal and outputs the inverted value "1110". AND circuit 119
Is the output value “0001” of the selector 114 and the inverter 1
The logical product of 18 output values "1110" is calculated and "000"
0 "is output to the register 116. The state at this time is shown by clock 4 in FIG.

At the timing of clock 5, since the register value is "0000", the output value of OR115 is "0", and "0000" is output as the Hold signal. In the input buffers 107 to 110, the Ho value is "0".
Since the ld signal is received, the buffered request is slid one step, and new requests A2, B2,
C2 and D2 are sent to the contention arbitration circuit 111 and the data selector 112. The state of each input buffer at this time is shown in FIG. In the contention arbitration circuit 111, the request type recognition circuit 113 receives the TAG sent from the input buffer. Request type recognition circuit 113
Identifies the TAG and outputs "1111" because all the requests are valid. The selector 114 inputs the output value of the OR 115 whose value is “0” as the select signal, and outputs the output value “111” of the request type recognition circuit 113.
1 ”is selected and input to the priority encoder 117. In the priority encoder 117,“ 111 ”is input.
1 "is input, arbitration is performed according to a specific priority order, and" 1000 "is output as a select signal. The data selector 112 inputs the select signal" 1000 "output from the priority encoder 117 to input the data A2 of the input buffer 107. Is output to the internode connecting device 106. The inverter 118 outputs the inverted value "0111" of the select signal "1000" The AND circuit 119 outputs the output value "11" of the selector 114.
11 ”and the output value“ 0111 ”of the inverter 118 are ANDed, and“ 0111 ”is output to the register 116.
The state at this time is shown in the clock 5 of FIG.

At the timing of clock 6, clock 2
Input buffer 1 performs the same operation as the timing
The data B2 of 08 is output to the internode connecting device 106. The state at this time is shown in the clock 6 of FIG.

At the timing of clock 7, clock 3
Input buffer 1 performs the same operation as the timing
The data C2 of 09 is output to the internode connecting device 106. The state at this time is shown by the clock 7 in FIG.

At the timing of clock 8, clock 3
Input buffer 1 performs the same operation as the timing
The data D2 of 10 is output to the internode connecting device 106. The state at this time is shown by the clock 8 in FIG.

At the timing of clock 9, since the register value is "0000", the output value of OR115 is "0", and "0000" is output as the Hold signal. Each of the input buffers 107 to 110 has an H value of "0".
Since the old signal is received, the buffered request is slid one step, and new requests B3 and C3 are sent.
To the contention arbitration circuit 111 and the data selector 112. The state of the input buffer at this time is shown in FIG. In the competitive arbitration circuit 111, the input buffer 1
The request type recognition circuit 113 receives the TAG transmitted from 07 to 110. The request type recognition circuit 113 identifies the TAG and outputs "0110".
The selector 114 inputs the output value of the OR 115 whose value is “0” as the select signal, selects the output value “0110” of the request type recognition circuit 113, and inputs it to the priority encoder 117. The priority encoder 117 inputs “0110”, performs arbitration according to a specific priority order, and outputs “select signal” as a select signal.
The data selector 112 inputs the select signal “0100” output from the priority encoder 117, selects the data B3 in the input buffer 108, and outputs the data B3 to the internode connecting device 106.
The inverter 118 outputs the inverted value “1011” of the select signal “0100”. The logical product circuit 119 takes the logical product of the output value “0110” of the selector 114 and the output value “1011” of the inverter 118, and stores it in the register 116.
0010 "is output. The state at this time is shown by clock 9 in FIG.

At the timing of the clock 10, since the value of the register 116 is "0010", the output value of the OR 115 becomes "1", and "1111" is output as the Hold signal. Since the input buffers 107 to 110 each receive the Hold signal whose value is "1", the state of the input buffer does not change. The selector 114 outputs O as a control signal.
The output value "1" of R115 is input and the value "0010" of the register 116 is selected. The priority encoder 117 inputs the output value “0010” of the selector 114 and outputs “0010” as a select signal. The data selector 112 receives the select signal “0010”, selects the data C3 in the input buffer 109, and outputs it to the internode connecting device 106. The inverter 118 inputs the select signal and outputs the inverted value “1101”.
The AND circuit 119 outputs the output value “001” of the selector 114.
The logical product of “0” and the output value “1101” of the inverter 118 is calculated and “0000” is output to the register 116.
The state at this time is shown in the clock 10 of FIG.

At the timing of clock 11, since the register value is "0000", the output value of OR115 is "0".
Then, "0000" is output as the Hold signal.
Since the input buffers 107 to 110 each receive a Hold signal having a value of "0", the buffered request is slid one step and new requests B4 and C are added.
4 is sent to the contention arbitration circuit 111 and the data selector 112. The state of the input buffer at this time is shown in FIG. In the contention arbitration circuit 111, the TAG sent from the input buffer is recognized by the request type recognition circuit 113.
Receive at. The request type recognition circuit 113 identifies the TAG and outputs "0110". The selector 114 inputs the output value of the OR 115 whose value is “0” as the select signal, and outputs the output value of the request type recognition circuit 113 ”.
0110 ”is selected and the priority encoder 117 is selected.
To enter. "0" in the priority encoder 117
110 "is input, arbitration is performed according to a specific priority order, and" 0100 "is output as a select signal. In the data selector 112, the select signal" 0100 "output by the priority encoder 117 is input, and the data B4 of the input buffer 108 is input. Is output to the internode connecting device 106. The inverter 118 outputs the inverted value "1011" of the select signal "0100" .The AND circuit 119 outputs the output value "01" of the selector 114.
10 ”and the output value“ 1011 ”of the inverter 118 are ANDed and“ 0010 ”is output to the register 116.
The state at this time is shown in the clock 11 of FIG.

At the timing of the clock 12, since the value of the register 116 is "0010", the output value of the OR 115 is "1", and "1111" is output as the Hold signal. Since the input buffers 107 to 110 each receive the Hold signal having a value of "1", the state of each input buffer does not change. The selector 114 inputs the output value “1” of the OR 115 as a control signal and selects the value “0010” of the register 116. The priority encoder 117 inputs the output value “0010” of the selector 114 and outputs “0010” as a select signal. The data selector 112 receives the select signal “0010”, selects the data C4 in the input buffer 109, and outputs it to the internode connecting device 106. The inverter 118 inputs the select signal and outputs the inverted value “1101”.
The AND circuit 119 outputs the output value “001” of the selector 114.
The logical product of “0” and the output value “1101” of the inverter 118 is calculated and “0000” is output to the register 116.
The state at this time is shown by the clock 12 in FIG.

The processing of the request group is completed by the above series of operations. The order of data output to the inter-node connection device 106 is shown in FIG. 9 (b). Figure 9 (b)
Looking at requests B1 to B4, it can be seen that they are not continuously sent to the processor.

Since the operation is performed as described above, the data transmission order is as shown in FIG. 9 (b).

FIG. 10 is a comparison diagram showing the operation results of the circuit of the present invention and the conventional circuit in a time chart format. FIG. 10 (a) shows an operation result of the embodiment of the present invention.
The 0-minute diagram (b) shows the operation result of the circuit shown in FIG. 7.

FIG. 10 shows the operation result when an instruction is executed for the circuit shown in FIG. 7 such that processing using 4T request data takes 4 cycles and processing using 2T request data takes 2 cycles. It is shown in FIG.

[0025]

In the conventional contention arbitration method described above, when there is competition between consecutive elements sent from a plurality of processors, the consecutive elements become discontinuous and the internode connecting device is connected. It will be sent out. Therefore, when executing a command using the data received by the processor of another node, it is necessary to wait until all the discontinuous request elements arrive, which causes a problem of increasing the processing time.

An object of the present invention is to continuously send consecutive elements for each request even if there is competition between consecutive elements sent from a plurality of processors, so that the processing time of the entire information processing apparatus is increased. It is to provide a competitive arbitration method capable of shortening.

[0027]

According to the contention arbitration method of the present invention, a plurality of processors, a memory commonly used by the plurality of processors, and a crossbar network for connecting the plurality of processors to the memory are provided. units and the nodes consisting the conflict arbitration method of the nodes in the information processing apparatus formed by connecting a plurality of said nodes via between said node connection device, the crossbar network, in response to a plurality of said processors plurality input buffer provided, each conflict arbitration and when transfer elements are separate data between a plurality of the processors and the memory, a plurality of said processors connected through between said node connection device each between the node of Germany
Perform both standing the elements and competition arbitration when transfer of the data for each clock, and conflict arbitration circuit for outputting a select signal for selecting instruction to one of said elements to be transferred, the output of the conflict arbitration circuit before sent from a plurality of said input buffer in accordance with the select signal instructing the transfer of
Select one element from among the serial element, is composed of a data selector unit to output any one of said memory and said node connecting unit, wherein the processor sends SakiSo
In the memory or between the node connecting device is a location, and sends the transferred data composed of arbitrary number of elements, before
In the case of storing in the input buffer, the number of elements and the destination device are added to each element of the transfer data for transmission, and the contention arbitration circuit is added to the transfer data.
The destination device of the transfer data is an internode connection device.
If the said from the large consisting transfer data number of elements of the transfer data are competing requests transfer order element minutes continuously instructs transfer of the processor selected by the conflict arbitration between processors controls the data selector so as to deliver all of the elements of the transferred data, and adapted to deliver data continuously for the number of elements.

In the contention arbitration method of the present invention, the contention arbitration circuit outputs an active holding signal to the input buffer in which an element other than the processing target exists during the processing of the element and is stored . It may be controlled to hold the element.

[0029]

[0030]

According to the contention arbitration method of the present invention, when the destination device of the transfer data added to the transfer data is a memory, the contention arbitration circuit activates one element of the processor selected by the contention arbitration between the processors. Contention arbitration between processors may be performed again each time the data selector unit is controlled to be sent.

In the contention arbitration method of the present invention, the input buffer stores the transfer data sent from the processor,
Arbitrating circuit sends a transmission destination apparatus and the number of elements in, sends out an element to the data selector section, the holding signal outputted from the conflict arbitration circuit may hold the elements when the active are stored .

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the apparatus to which the present invention is applied, first, a unit node is a plurality of processors 1, 2, 3, 4 and a memory 5 commonly used by the processors 1, 2, 3, 4 and a processor 1, 1. This is an information processing device that is configured by a crossbar network 6 that connects between the memory cells 2, 3, 4 and the memory 5, and that this node is connected to a plurality of nodes via an internode connection device 7. Further, the crossbar network 6 has input buffers 8, 9, 1 provided corresponding to a plurality of processors.
0, 11 and a plurality of processors 1, 2, 3, 4 and the memory 5 each arbitrate arbitration at the time of transfer of an independent element, and the processors 1, 2, 3, 4 configure the internode connection device 7. A contention arbitration circuit 12 that outputs a select signal together with contention arbitration during data transfer with a plurality of nodes connected via a plurality of input buffers, and a plurality of input buffers according to a select signal that the transfer output from the contention arbitration circuit 12 directs. 8,
The data selector section 13 selects one element from the elements sent from 9, 10, and 11 and outputs it to either the memory 5 or the internode connecting device 7.

An outline of the operation will be described below with an example of instruction transfer between nodes.

Processors 1, 2, 3 and 4 use data and TA
The 2T request composed of G and 2T consecutively output and the 4T request composed of 4 consecutive elements are outputted to the input buffers 8, 9, 10, and 11. Input buffer 8,
Reference numerals 9, 10, and 11 are FIFO control buffers for buffering 2T requests and 4T requests.
G is the contention arbitration circuit 12, and data is the data selector unit 1.
Output to 3. In addition, input buffers 8, 9, 10, 11
Input the Hold signal output from the contention arbitration circuit 12, if the Hold signal is "0", slide the buffered request one step further and output the next request, and if the Hold signal is "1", buffer the request. Hold the contents that are ringed. The contention arbitration circuit 12 inputs the TAG sent from the input buffers 8, 9, 10, and 11 to perform contention arbitration, and sends a select signal to the data selector unit 13. In addition, the contention arbitration circuit 12 checks the contention among a plurality of requests sent from the input buffers 8, 9, 10, and 11 and sends the data in the input buffer having a high priority to the inter-node connection device 7 with priority. A select signal is sent to the data selector unit 13 so that each input buffer is individually set to Ho depending on the processing state of the conflict request.
Send the ld signal to control the input buffer. The data selector unit 13 inputs the select signal sent from the contention arbitration circuit 12, selects data, and sends it to the inter-node connection device 7.

Next, the configuration of the competitive arbitration circuit will be described. FIG. 2 is a circuit diagram of the competitive arbitration circuit shown in FIG.

The input buffers 8, 9, 10, 11 are connected to a processor (not shown) to receive transfer request data and output data and TAG. The contention arbitration circuit 12 of the present embodiment has four request input ports and
It shall be able to process T and 4T requests.

The contention arbitration circuit 12 individually recognizes the requests input to the four request receiving ports (input ports), and outputs "1" to the bit corresponding to the port to which the 4T request is input on the signal line 51. Then, the request type recognition circuit 14 that outputs “1” to the bit corresponding to the port that inputs the 2T request to the signal line 52, and
The output signal of the input OR circuit (hereinafter referred to as 2-input OR) 15 is input as a selection signal, and if the selection signal is "0", the value of the signal line 51 is selected, and if the selection signal is "1", the competition information The selector 17 which selects and outputs the output signal of the holding register 16 and the output signal of the input OR circuit 15 are input as selection signals. If the selection signal is "0", the value of the signal line 52 is selected and the selection signal is If it is "1", a selector 19 for selecting and outputting the output signal of the register 18 for holding the competition information,
The value of the output signal line 53 of the counter control circuit 20 is input as a selection signal. When the selection signal is "0", the output signal of the selector 17 is selected, and when the selection signal is "1", the selector 1 is selected.
Select the output signal of 9 and output the priority encoder input selector 21 and the output signal of the priority encoder input selector 21 and set only the bit corresponding to the youngest request receiving port (input port) number to "1", A fixed-priority priority encoder 22 that outputs a select signal to the data selector unit 13, an inverter 23 that inputs the output value of the priority encoder 22 and outputs an inverted value thereof, and an output signal of the priority encoder input selector 21. An AND circuit 24 that outputs a logical product with the output signal of the inverter 23, and an H that holds and outputs the output value of the inverter 23
The output signal of the register 25 for generating the old signal and the output signal of the AND circuit 26 is input as a selection signal, and the value of the selection signal is "0".
In the case of, a selector 27 for inputting the competition information holding register that selects the output signal of the selector 17 and selects and outputs the output signal of the AND circuit 24 when the value of the selection signal is "1",
The output signal of the AND circuit 28 is input as a selection signal. When the value of the selection signal is "0", the output signal of the selector 19 is selected. When the value of the selection signal is "1", the output signal of the AND circuit 24. A competitive information holding register input selector 29 for selecting and outputting to the competitive information holding register 18, and a competitive information holding register 16 for holding and outputting the output value of the competitive information holding register input selector 27. A competition information holding register 18 for holding and outputting the output value of the selector 29 for inputting the competition information holding register, an output signal of the competition information holding register 16 and an output signal of the competition information holding register 18. A four-input logical sum circuit (hereinafter, referred to as a four-input OR) 30 for calculating a logical sum of the four kinds of signals of the value of the signal line 51 and the value of the signal line 52 for each bit, and 4
The input OR 30 and the output signal of the register 25 for generating the Hold signal are logically ANDed to obtain the input buffers 8, 9, 10, and 1.
1, a logical product circuit 31 outputting as a Hold signal,
A 4-input O that outputs the logical sum of the output signals of the register 16 for holding the competition information to the signal line 54 and the 2-input OR 15
A logical sum of R32 and the output signal of the register 18 for holding the competition information and outputting to the signal line 55 and the 2-input OR15, the logical sum of the output value of the 4-input OR32 and the output value of the 4-input OR33. 2 input OR15 which outputs to the selectors 17 and 19 as a selection signal, OR34 which outputs the OR of the output value of 4 bits of the selector 17 to the counter control circuit 20, and 4 bits of the selector 19.
Of the output values of the OR 35 and the output signals of the ORs 34 and 35 and the state value
The output signal of the 0 "recognition circuit 36 is input, and values are output to the output signal line 53 and the signal lines 56 and 57 according to the definition defined in advance between the input and the operation shown in FIG. Together with a counter control circuit 20 which issues an instruction to set a value or a subtraction instruction to the subtraction counter 37,
According to an instruction from the counter control circuit 20, a function of setting a value in the counter or subtracting "1" from the counter value and receiving a subtraction instruction when the counter value becomes "0""
It has the function of holding 0 "and the counter value is" 0 ".
The subtraction counter 37 that outputs to the recognition circuit 36 and the state value “1” recognition circuit 38, and the counter value output from the subtraction counter 37 are input, and when the counter value is “1”, the logical product circuits 26 and 28 are set to “1”. A state value "1" recognition circuit 38 that outputs "," and a counter control circuit 2 when the counter value output by the subtraction counter 37 is "0"
A state value “0” recognition circuit 36 which outputs a value “1” to 0,
State value "1" AND circuit 26 for outputting the logical product of the output value of the recognition circuit 38 and the value of the signal line 56 to the competition information holding register input selector 27 as a selection signal, and the state value "
It is composed of a logical product circuit 28 which takes the logical product of the output value of the 1 ″ recognition circuit 38 and the value of the signal line 57 and sends it as a selection signal to the competition information holding register input selector 29.

Next, the operation of the first embodiment of the present invention will be described. 3 and 4 are operation diagrams showing the operation state of the input buffer in clock units, and FIG. 5 is an explanatory diagram showing the bit state of each signal for each clock. 1 to 5 will be used for the description.

FIG. 3 (a) is an image of the first request group stored in the input buffer. A1, A
2, D1 and D2 indicate a 2T request, and B1,
B2, B3, B4, C1, C2, C3 and C4 indicate 4T requests. In the initial state, it is assumed that the registers of the contention arbitration unit are all 0 value.

At the first clock, requests A1 and B
The TAG units of 1, C1, D1 are sent to the contention arbitration unit. H
Initial value of register 25 for generating old signal "0000"
In response, the AND circuit 31 outputs the value "0" as the Hold signal.
000 ". The request type recognition circuit 14 inputs the TAG from each input port to identify the request type, and sets the bit corresponding to the port to which the 4T request B1 or C1 is input to" 1 "value". "0110" is output to the selector 17, and the value "1" is obtained by setting the bit corresponding to the port to which the 2T request A1, D1 is input to "1".
001 "is output to the input selector selector 19. When the clock is 0, the register 16 for holding the conflict information,
Since the value of 18 is "0000", 4-input OR32, 33
Has an output value of "0", and the values of the signal lines 54 and 55 are also "0". The output value of 4-input OR 32, 33 is "
Since it is "0", the output value of the two-input OR15 is "0".
Since the output value of the 2-input OR15 is "0", the selector 1
Reference numerals 7 and 19 select and output the output values of the signal lines 51 and 52. The ORs 34 and 35 are the output signal “0110” of the selector 17 and the output signal “100” of the selector 19, respectively.
1 "is input and both OR34 and 35 output" 1 ".
When the clock is 0, the counter value of the subtraction counter 37 is "
Since it is 0, the state value "1" recognition circuit 38 outputs "0", and the state value "0" recognition circuit 36 outputs "1". The counter control circuit 20 is predetermined as shown in FIG. Based on the relationship between the input state and the operation, the value "0" is output as the select signal to the priority encoder input selector 21 via the signal line 53, and the subtraction counter 37 is set to "3". Since the selector 21 receives "0" as the select signal from the counter control circuit 20, it selects the output value "0110" of the selector 17. The priority encoder 22 performs the arbitration of the contention arbitration information input from the priority encoder input selector 21 and the contention. Only the bit corresponding to the youngest input port in the arbitration information is set to "1". "0100" to be output to the data selector section 13 as the select signal. The data selector section 13 receives the select signal, B1 of the input buffer 9
The data part of is selected and output to the internode connecting device 7.
The select signal output from the priority encoder 22 is also input to the register 25 for generating a Hold signal via the inverter 23. By passing through the inverter 23 and the AND circuit 24, new competition information "0010" which is not selected in the first clock is generated, and the selector 27 and the selector 29 for inputting the competition information holding register are generated.
Entered in. The output value of the state value "1" recognition circuit 38 is "
Since it is "0", the output values of the AND circuits 26 and 28 are "
It becomes 0 ", and the selector 2 for inputting the conflict information holding register
Reference numerals 7 and 29 respectively select the output values of the selectors 17 and 19 and send them to the registers 16 and 18. At this time, the value of each register and the output data are shown in clock 1 of FIG. 5 (a) and FIG. 5 (b). The state of the input buffer is shown in FIG.

At the second clock, the values of the registers 16 and 18 are received, and the output values of the 4-input ORs 32 and 33 are both "
Since it is "1", the output value of the 2-input OR15 is "1".
Since the output value of the input OR15 is "1", the selectors 17,1
Reference numeral 9 selects the output values of the register 16 and the register 18, respectively. OR 34, 35 and state value "0" recognition circuit 3
Since the output values of 6 are "1", "1", and "0" respectively,
Based on the predetermined relationship between the input state and the operation shown in FIG. 5 (c), the value is selected as the select signal to the priority encoder input selector 21 via the signal line 53.
The output value “0110” of the selector 17 is input to the priority encoder 22 and “0100” is output as a select signal.
Since the output values of 6 and 28 are "0", the selectors 27 and 29 select the output values of the selectors 17 and 19, respectively, and send them to the conflict information holding registers 16 and 18. At this time, the value of each register and the output data are shown in the clock 2 in FIG. 5 (a) and FIG. 5 (b). The state of the input buffer is shown in FIG.

At the third clock, the output values of the 4-input ORs 32 and 33 are both "" upon receiving the values of the registers 16 and 18.
Since it is "1", the output value of the 2-input OR15 is "1".
Since the output value of the input OR15 is "1", the selectors 17,1
Reference numeral 9 selects the output values of the register 16 and the register 18, respectively. OR 34, 35 and state value "0" recognition circuit 3
Since the output values of 6 are "1", "1", and "0" respectively,
Based on the predetermined relationship between the input state and the operation shown in FIG. 5 (c), the value is selected as the select signal to the priority encoder input selector 21 via the signal line 53.
0 ”is output. The output value“ 0110 ”of the selector 17 is input to the priority encoder and“ 0100 ”is output as a select signal.
Becomes "1", and the output of the state value "1" recognition circuit 38 becomes "1". Therefore, the output value of the AND circuit 26 becomes "1",
The output value of the AND circuit 28 becomes "0". Selector 27
Then, the output value "0010" of the AND circuit 24 is selected and sent to the register 16. The selector 29 selects the output value “1001” of the selector 19 and sends it to the register 18. At this time, the value of each register and the output data are shown in clock 3 of FIG. 5 (a) and FIG. 5 (b). The state of the input buffer is shown in FIG.

At the 4th clock, the values of the registers 16 and 18 are received and the output values of the 4-input ORs 32 and 33 are both "
Since it is "1", the output value of the 2-input OR15 is "1".
Since the output value of the input OR15 is "1", the selectors 17,1
Reference numeral 9 selects the output values of the register 16 and the register 18, respectively. OR 34, 35 and state value "0" recognition circuit 3
Since the output values of 6 are "1", "1", and "0" respectively,
Based on the predetermined relationship between the input state and the operation shown in FIG. 5 (c), the value is selected as the select signal to the priority encoder input selector 21 via the signal line 53.
The output value "0010" of the selector 17 is input to the priority encoder and "0010" is output as a select signal. The selector 27 selects the output value "0010" of the AND circuit 24. , To the register 16. The selector 29 selects the output value “1001” of the selector 19 and sends it to the register 18. At this time, the value and output data of each register are shown in FIG. ) Clock 4 and the state of the input buffer is shown in FIG.

At the 5th clock, the values of the registers 16 and 18 are received, and the output values of the 4-input ORs 32 and 33 are both "
Since it is "1", the output value of the 2-input OR15 is "1".
Since the output value of the input OR15 is "1", the selectors 17,1
Reference numeral 9 selects the output values of the register 16 and the register 18, respectively. The count value of the subtraction counter 37 becomes "0", and the output values of the ORs 34 and 35 and the state value "0" recognition circuit 36 are "1", "1", and "1", respectively.
Based on the predetermined relationship between the input state and the operation shown in the diagram (c), the value "0" is output as the select signal to the priority encoder input selector 21 via the signal line 53, and at the same time the subtraction counter 37 is output. "3" is set. Selector 1 for priority encoder 22
The output value "0010" of No. 7 is input, and "0010" is output as the select signal. Since the output values of the AND circuits 26 and 28 are "0", the selectors 27 and 29 select the output values of the selectors 17 and 19, respectively, and send them to the competition information holding registers 16 and 18. At this time, the value of each register and the output data are shown in clock 5 of FIG. 5 (a) and FIG. 5 (b). The state of the input buffer is shown in FIG.

At the sixth clock, the output value "0110" of the selector 17 is input to the priority encoder 22 and "0010" is output as a select signal.
Since the output values of the AND circuits 26 and 28 are "0", the selectors 27 and 29 select the output values of the selectors 17 and 19, respectively, and send them to the competition information holding registers 16 and 18. At this time, the value of each register and the output data are shown in the clock 6 of FIG. 5 (a) and FIG. 5 (b). The state of the input buffer is shown in FIG.

At the 7th clock, the output value "0010" of the selector 17 is input to the priority encoder 22 and "0010" is output as a select signal.
Since the value of the subtraction counter 37 becomes "1" and the output of the state value "1" recognition circuit 38 becomes "1", the output value of the AND circuit 26 is "1" and the output value of the AND circuit 28 is "0". "It becomes. In the selector 27, the output value of the AND circuit 24 is “000”.
0 "is selected and sent to the register 16. At this time, the value of each register and the output data are shown in the clock 7 of FIG. 5A and FIG. 5B. The state of the input buffer is shown in FIG. It is shown in diagram (g).

At the 8th clock, the value "0" in the register 16
The 4-input OR 32 receiving "000" has an output value of "0" and the 4-input OR receiving the value "1001" of the register 18
Since the output value of 33 is "1", the output value of the 2-input OR15 is "1". Since the output value of the 2-input OR 15 is "1", the selectors 17 and 19 select the output values of the register 16 and the register 18, respectively. The output values of the ORs 34 and 35 and the state value "0" recognition circuit 36 are "1" and "," respectively.
Since it is 1 "or" 0 ", the value" 0 "is selected as a select signal to the priority encoder input selector 21 via the signal line 53 based on the relationship between the predetermined input state and the operation shown in FIG. The output value “0010” of the selector 17 is input to the priority encoder, and “0100” is output as a select signal, and the selector 29 outputs “1001” of the selector 19.
Is selected and sent to the register 18. At this time, the value of each register and the output data are shown in FIG. 5 (a) and (b).
Clock 8 of FIG. Also, the state of the input buffer is shown in FIG.
It is shown in diagram (h).

At the 9th clock, the value "00" in the register 16
The output value of the 4-input OR 32 receiving "00" becomes "0", and the 4-input OR receiving the value "1001" of the register 18
Since the output value of 33 is "1", the output value of the 2-input OR15 is "1". Since the output value of the 2-input OR 15 is "1", the selectors 17 and 19 select the output values of the register 16 and the register 18, respectively. The output values of the ORs 34 and 35 and the state value "0" recognition circuit 36 are "0" and "," respectively.
Since it is 1 "or" 1 ", the value" 1 "is selected as a select signal to the priority encoder input selector 21 via the signal line 53 based on the relationship between the predetermined input state and operation shown in FIG. 5C. Is output, the subtraction counter 37 is set to "1", the output value "1001" of the selector 17 is input to the priority encoder 22, and "1000" is output as a select signal. , 28 output "0", the selectors 27, 29 respectively select the output values of the selectors 17, 19 and send them to the conflict information holding registers 16, 18. At this time, the values and output data of the respective registers are output. Figure 5
It is shown in the clock 9 of the charts (a) and (b). The state of the input buffer is shown in FIG.

The state values and output data from 10 clocks to 12 clocks are shown in FIGS. 5 (a) and 5 (b). Further, the states of the input buffers are shown in the order of clocks in the diagrams (j) to (l) of FIG.

By performing the above operation, even if contention occurs between the elements, it is possible to output to the internode connecting device 7 while maintaining the continuity of the elements. For example, a time chart when an instruction string is executed in which processing using 4T request data sent to another internode connecting device takes 4 cycles and processing using 2T request data takes 2 cycles is shown. Shown in Fig. 10 (a)
become that way.

An example in which the processors 1 to 4 send data to the memory 5 will be shown. Since the processors 1 to 4 send the element whose destination device name is the memory 5, the contention arbitration circuit 12 of the present invention sends data to send one element of the processor selected by the contention arbitration between the processors.
Each time the selector unit is controlled , competition arbitration between processors is performed again, so that data is sent to the memory 5 in units of individual elements. The result of processing this data by the contention arbitration method according to the embodiment of the present invention is shown in FIG.

[0055]

As described above, according to the present invention, when an input buffer provided corresponding to a plurality of processors in a crossbar network and an element independent from each other between a plurality of processors and a memory are transferred. And a contention arbitration circuit that outputs a select signal by performing contention arbitration and contention arbitration at the time of data transfer with a plurality of nodes connected by a plurality of processors via an internode connection device, and a contention arbitration circuit that outputs a select signal. The contention arbitration circuit is provided with a data selector section that selects one element from the elements sent from a plurality of input buffers according to a select signal instructing transfer and outputs the element to either the memory or the internode connecting device. Requesting the transfer and instructing the transfer in order from the one with the largest number of consecutive elements among the competing data, Even if a conflict between elements of successive transmitted from the processor, by transmitting continuously successive elements for each request, there is the effect that the processing time of the entire information processing apparatus becomes possible shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a contention arbitration circuit shown in FIG.

FIG. 3 is an operation diagram (a to h) showing the operation state of the input buffer in clock units.

FIG. 4 is an operation diagram (i to l) in which the operation state of the input buffer is displayed in clock units.

5A and 5B are explanatory views showing a bit state of each signal for each clock.

FIG. 6 is a block diagram of a conventional information processing apparatus that implements a service similar to that of the present invention.

FIG. 7 is a circuit diagram of a conventional high-speed crossbar switch control competitive arbitration circuit.

FIG. 8 is an operation diagram showing the operation state of the input buffer in clock units.

FIG. 9 is an explanatory diagram showing a bit state of each signal for each clock.

FIG. 10 is a comparison diagram showing the operation results of the present invention and the conventional circuit in a time chart format.

[Explanation of symbols]

1, 2, 3, 4 processor 5 memory 6 Crossbar network 7 Node connection device 8, 9, 10, 11 input buffer 12 Competitive Arbitration Circuit 13 Data selector part 14 Request type recognition circuit 15 2-input logical sum circuit (2-input OR) 16, 18, 25 registers 17, 19, 27, 29 Selector 20 Counter control circuit 21 Priority Encoder Input Selector 22 Priority encoder 23 Inverter 24, 26, 28, 31 AND circuit 30, 32, 33 4 input OR circuit (4 input OR) 34, 35 OR circuit (OR) 36 State value "0" recognition circuit 37 Subtraction counter 38 Status value "1" recognition circuit 51, 52, 54, 55, 56, 57 signal lines 53 Output signal line

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (4)

(57) [Claims] 1. A plurality of processors, a memory used this plurality of processors common, said plurality of processor units comprising a crossbar network for connecting between the memory and the node, the node is said node in conflict arbitration method in the information processing apparatus formed by connecting a plurality of the <br/> node through between connecting device, the crossbar network has an input buffer provided in correspondence to the plurality of processors, a plurality each between the processor of the respective conflict arbitration and when transfer elements are separate data between the memory and a plurality of said nodes a plurality of the processors that are connected to each other through between the node connecting device Is an independent day
Performs both elements and competition arbitration when transfer of a data for each clock, and conflict arbitration circuit for outputting a select signal for selecting instruction to one of said elements to be transferred, the transfer to the output of the conflict arbitration circuit select one element from among the elements transmitted from a plurality of said input buffer in accordance with said selector <br/> preparative signal for instructing to output to one of said memory and said node connecting unit And a data selector unit, wherein the processor is the destination device, the memory, or
Between the node connecting device, and sends the transferred data composed of any number of elements, if <br/> stored in the input buffer, wherein the number of elements sent to the elements of each of said transfer data
The contention arbitration circuit adds the destination device and sends the data.
If the data transmission destination device is an internode connection device,
If the transfer directs requests to conflicting the transfer from the large consisting transfer data number of elements of the transfer data continuously element minutes in order to, said selected processor transferred conflict arbitration between processors conflict arbitration method characterized by controlling the data selector unit to deliver all of the elements of the data, and sends data continuously for the number of elements. Wherein said contention arbitration circuit, so as to hold the element outputs an active hold signal, is stored to the input buffer that is present in the elements other than the process target during the processing of said element The contention arbitration method according to claim 1, wherein the contention is arbitrated. Wherein the conflict arbitration circuit, the case where the transmission destination device of the transfer data added to the transfer data is the said memory, one of the of the processor selected by the conflict arbitration between the processors conflict arbitration method of claim 1, wherein the performed again arbitrating between said processor each time controlling said <br/> data selector so as to deliver an element. Wherein said input buffer stores the transfer data sent from the processor, and sending the number of elements and said transmission destination device to the conflict arbitration circuit, the de-<br/> Taserekuta unit It said element sends out a rating when the holding signal is active output from the conflict arbitration circuit
The contention arbitration method according to claim 1, wherein the stored elements are retained.