CN100356355C - Arbitration device and arbitration method thereof - Google Patents
Arbitration device and arbitration method thereof Download PDFInfo
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- CN100356355C CN100356355C CNB031420168A CN03142016A CN100356355C CN 100356355 C CN100356355 C CN 100356355C CN B031420168 A CNB031420168 A CN B031420168A CN 03142016 A CN03142016 A CN 03142016A CN 100356355 C CN100356355 C CN 100356355C
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Abstract
The present invention provides an arbitration device and an arbitration method thereof. A main device in a bus system is provided with an important main device and a secondary main device, and the arbitration device is provided with a first stage arbitration module and a second stage arbitration module. The second stage arbitration module can arbitrate bus use requirements sent out from the secondary main device, and the first stage arbitration module can arbitrate the arbitration results of the second stage arbitration module and the bus use requirements sent out from the important main device together. Therefore, different arbitration occasions are set by aiming at different bus use requirement levels so as to increase the arbitration efficiency and increase the bus use efficiency. The arbitration device has the ability of reverse arbitration, and can avoid the mutual collision of data reading return under the precondition of increasing the bus use efficiency.
Description
Technical field
The present invention relates to a kind of moderator and referee method, relate in particular to a kind of bus that is applied in many device systems each equipment to be sent and use request fast and effeciently to arbitrate, thereby can improve the moderator and the referee method of bus efficiency.
Background technology
The appearance that the fast development of production process of semiconductor has promoted deep sub-micron technique in the development of IC design industry, particularly production process of semiconductor has greatly been shifted the system-on-a-chip design onto in the forward position of integrated circuit (IC) design.The system-on-a-chip technology is that a plurality of processors that were dispersed in the past on a plurality of different chips are integrated in on the chip piece, to form the complete system of a perfect in shape and function, performance optimization.Because the physical area of system-on-a-chip and encapsulation stitch have all had minimizing by a relatively large margin with respect to multichip system, make the production cost of total system also reduce significantly.And on the other hand, the intellecture property in the system (IP) multiplex technique has also shortened the design cycle of system-on-a-chip, and the design cost of system also is minimized.
Various processors may be comprised in the system-on-a-chip, as central processing unit (CPU), digital signal processor (DSP) and various special IC (ASIC) etc., and storage unit, even the subsystem of establishing processor cores in various may be comprised.The complicacy that the expansion of total system scale makes system than before multichip system also greatly improve, thereby how rationally and effectively in the regulating system each processor or operating in of subsystem become a considerable problem in the total system design process.Bus architecture is the intercommunication mutually that is used for reaching each processor in the system or subsystem, comprises that instruction transmits and the data transmission, so the design of bus architecture has fundamental influence for the collaborative work of total system.
Signal in bus system between a plurality of equipment sends request to bus in transmitting, and the equipment that requires to carry out the signal transmission is called main equipment; The target device that main equipment requires to carry out the signal transmission with it then is called slave unit.For the communication of many equipment, the bus that adopts moderator to come a plurality of equipment are sent in the bus system uses request to judge, and determines the equipment that gives the bus right of possession corporeal right according to various algorithms.According to the configuring condition of moderator, bus architecture mainly is divided into two big class, i.e. distributed bus and centralized buses at present.Wherein the distributed bus framework is the moderator to the correspondence of each equipment disposition in the system, is vied each other to decide by which equipment on the bus by each moderator and obtains the authorization and take bus; Centralized bus is meant for total system and only adopts a unified moderator, and according to default arbitration mode, the bus that equipment all on the bus is sent is used request to concentrate and made judgement, determine to license the equipment of bus by this moderator.Understandable is that especially for centralized bus system, moderator is for bus service efficiency decisive role.
In case main equipment sends bus to moderator and uses request and acquisition bus grant in the prior art, before the transfer operation of this master devices request is finished, will occupy bus with this main equipment always, the bus request that other main equipments propose then can not get response.Therefore, the designer tends to main equipment is provided with certain priority level, and when moderator was arbitrated, under the equal conditions, the bus that the higher main equipment of priority level sends used request preferentially to meet with a response.The bus use request that the designer who also has proposes main equipment is sent is divided into different priority levels, and moderator uses the priority level of request by each bus, and determines the bus of preferentially making response to use request.But moderator is being done when arbitration, if use request to arbitrate to the bus of each different brackets simultaneously, will make the hardware of moderator and the algorithm all can more complicated, and arbitration cycle is prolonged.
On the other hand, for the bus system of supporting the separate type read operation, for example, bus master with a plurality of threads, some threads of a certain main equipment may send read operation, and before making response, also allow other threads of this main equipment to send signal transfer operation (wherein also comprising read operation certainly) with the corresponding slave unit of its operation.In this case, have a plurality of threads and send data at the corresponding slave unit of waiting for its read operation, and the corresponding slave unit of the read operation of early sending may need long data setup time, if the precedence of sending by read operation is carried out the carrying out that data are returned the read operation that will influence other threads.In order to improve the service efficiency of bus, we can allow read data to get over preface to return, promptly for off-the-shelf read data, no matter can send the precedence of read operation request, and preferentially return in design.But the preface more of this read data is returned and different slave units also might be occurred in the situation of synchronization with bus release read data, thereby causes the each other conflict of read data when returning.Can increase the visit time-delay so on the contrary, and bus efficiency is reduced.
In order to address the above problem, the present invention proposes a kind of moderator and referee method of improvement, both can carry out the forward arbitration, can oppositely arbitrate again.In the forward arbitration, can use the request grade and set up different arbitration opportunitys at different buses; In oppositely arbitrating, arbitration is made in the request that can return the read data of a plurality of slave units.
Summary of the invention
The object of the present invention is to provide a kind of moderator and referee method of improvement, use the request grade and set up different arbitration opportunitys, arbitrate efficient to improve, and improve the bus service efficiency at different buses.
Another purpose of the present invention is to provide a kind of moderator and referee method of improvement, has reverse arbitration ability, under the prerequisite that improves the bus service efficiency, and the mutual conflict of avoiding read data to return.
A kind of moderator of the present invention is used for centralized bus system the bus use request that each equipment sends is arbitrated, and each equipment in the described bus system is divided into main equipment and slave unit, and wherein said moderator comprises:
Forward phase one arbitration modules;
Forward subordinate phase arbitration modules,
Described main equipment also is divided into important main equipment and less important main equipment, the bus that described subordinate phase arbitration modules is sent less important main equipment uses request to arbitrate, the bus that described phase one arbitration modules is sent the arbitration result and the important main equipment of described subordinate phase arbitration modules uses request to arbitrate together
Described forward phase one arbitration modules comprises arbitration state machine, this arbitration state machine have correspond respectively to first and second the arbitration opportunity first and second arbitrate states, and the bus request that main equipment sends is divided into first rank and the second level bus is used request, wherein said second level bus is used the priority of request to be higher than the first rank bus and is used request, wherein said first arbitration uses request to arbitrate to described first and second grades of other buses opportunity simultaneously, and described second arbitration only uses request to arbitrate to the bus of second level opportunity.
A kind of referee method of the present invention, being used for centralized bus system arbitrates the bus use request that each equipment sends, each equipment in the described bus system is divided into main equipment and slave unit, it is characterized in that described referee method comprises phase one arbitration and subordinate phase arbitration
Described main equipment also is divided into important main equipment and less important main equipment, the bus that described subordinate phase arbitration is sent less important main equipment uses request to arbitrate, the arbitration of described phase one uses request to arbitrate together to the bus that the arbitration result and the important main equipment of described subordinate phase arbitration sends
Use arbitration state machine to arbitrate in the described phase one arbitration, this arbitration state machine have correspond respectively to first and second the arbitration opportunity first and second arbitrate states, and the bus request that main equipment sends is divided into first rank and the second level bus is used request, wherein said second level bus is used the priority of request to be higher than the first rank bus and is used request, wherein said first arbitration uses request to arbitrate to described first and second grades of other buses opportunity simultaneously, and described second arbitration only uses request to arbitrate to the bus of second level opportunity.
According to an aspect of the present invention, bus system comprises main equipment, slave unit and the moderator that links to each other with bus respectively.Main equipment sends bus to moderator and uses request, after the arbitration of moderator process, uses request to authorize to the bus of choosing, and the main equipment that then sends this bus use request occupies bus and carries out data transfer operation with corresponding slave unit.The bus that main equipment sends uses request to become different priority levels by software arrangements, and moderator is set different arbitration opportunitys in arbitration state machine.Only use request to arbitrate opportunity in the arbitration that gap periods is short, use request and ignore the lower bus of priority to the bus of tool higher priority; Than long arbitration opportunity, the bus of tool higher priority is used the bus of request and tool lower priority to use and is asked and can be arbitrated by moderator simultaneously in gap periods.
According to another aspect of the present invention, bus system is supported the read operation of separate type, sends the bus of return data operation at different slave units simultaneously and uses under the request situation, and moderator is arbitrated the return data request of operating according to certain algorithm.In one embodiment of the invention, use request to set different priority levels by software arrangements to the bus of each slave unit return data operation, moderator is arbitrated according to priority level.
According to one embodiment of present invention, moderator carries out the layering arbitration to a plurality of equipment on the bus, require lower request in more rudimentary arbitration modules, to arbitrate to response speed, and the arbitration result that request that response speed is had relatively high expectations and more rudimentary arbitration modules obtain is arbitrated in higher arbitration modules.Moderator comprises phase one arbitration modules and subordinate phase arbitration modules, and correspondingly, the arbitration operation of moderator comprises phase one arbitration and subordinate phase arbitration.Main equipment in the bus system further is divided into important main equipment and less important main equipment, and the bus that moderator sends less important main equipment in the subordinate phase arbitration uses request to arbitrate, and arbitration result is sent into the arbitration phase one again.To arbitrate bus that the important main equipment of arbitration result on bus of subordinate phase send the phase one in arbitration uses and asks to arbitrate.
In the phase one of moderator arbitration modules, also further be provided with filtrator, various filter element can be set in filtrator the bus use request that main equipment sends is filtered, through the effectively request participation arbitration of bus use request conduct of filtrator.Comprise slave unit busy condition filter element in one embodiment of the invention, send the SBusy signal by the slave unit that temporarily can't carry out data transfer operation and give filtrator.Bus uses request to be judged by filtrator earlier before arbitrating, if the target slave unit of data transfer operation is the pairing slave unit of SBusy signal, then this bus uses request to be left in the basket.Be provided with last-minute plea controlled filter unit for reaching bus streamline arbitration in another embodiment of the present invention, make the request conductively-closed of last clock period of the stream bursts of each well afoot.Be provided with pairing read-write operation filter element in another embodiment of the present invention, when bus is handled the read-write operation of pairing, make it be in latch mode when bus is done read access, will be left in the basket if the read-write operation bus that has other main equipments to send pairing is used request this moment.
One aspect of the present invention has proposed a kind of arbitration opportunity of classification, has both improved the response speed to the data transfer operation of need preferential answering, has improved arbitration efficient again, thereby has improved bus efficiency on the whole.
Another aspect of the present invention is that the bus system of supporting the separate type read operation has been proposed a kind of reverse arbitration mechanism.Simultaneously when bus is sent data and returned request, oppositely arbitration mechanism can be avoided because data collision causes the situation of bus obstruction, thereby has also improved the service efficiency of bus from another point of view at a plurality of slave units.
The invention will be further described below in conjunction with accompanying drawing.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same-sign is represented respective element or step among the embodiment among the figure, wherein:
Fig. 1 is the bus system structural drawing of one embodiment of the invention;
Fig. 2 is the moderator structural representation of one embodiment of the invention;
The sequential chart of the example that Fig. 3 arbitrates for the subordinate phase arbitration modules of one embodiment of the invention;
Fig. 4 is the fundamental diagram of the moderator middle filtrator of one embodiment of the invention;
Fig. 5 is the slave unit busy condition filter element sequential chart of the moderator middle filtrator of one embodiment of the invention;
Fig. 6 latchs controlled filter unit sequential chart for the bus of the moderator middle filtrator of one embodiment of the invention;
Fig. 7 is the last-minute plea controlled filter unit sequential chart of the moderator middle filtrator of one embodiment of the invention;
Fig. 8 is the forward arbitration sequential chart on opportunity of one embodiment of the invention;
Fig. 9 is the arbitration state machine fundamental diagram of one embodiment of the invention; With
Figure 10 is the reverse arbitration sequential chart on opportunity of one embodiment of the invention.
Embodiment
Figure 1 shows that the bus system of one embodiment of the invention.This bus system exemplarily comprises a bus, and the main equipment A that links to each other with this bus respectively, main equipment B, main equipment C, main equipment D, slave unit A, slave unit B, slave unit C and slave unit D.Bus be provided with a moderator respectively with bus on each equipment be coupled mutually, make arbitration in order to the bus use request that each equipment that is connected on the bus is proposed.
In bus system, the several main equipment configuration of cells in the system can be become a main equipment on the bus, and this several main equipments unit can be called a thread of the main equipment on this bus with a plurality of main equipments unit.Adopt the bus system of multithreading to be equivalent in advance the main equipment inside on a bus and arbitrate, thereby can improve the service efficiency of moderator on the bus.
In the present embodiment, main equipment A has 3 threads, and bus master B has 2 threads, and wherein each thread can be CPU, DSP, ASIC or subsystem etc.Main equipment C and main equipment D then do not comprise a plurality of threads, and they can be respectively a kind of in CPU, DSP, ASIC or the subsystem etc.
Present embodiment also is divided into main equipment important main equipment and less important main equipment.Main equipment A and main equipment B are important main equipment, and main equipment C and main equipment D are less important main equipment.Generally speaking, can be made as important main equipment to the main equipment that the bus response speed is had relatively high expectations, the equipment of handling in real time as need etc., and be not that too high equipment is made as less important main equipment response speed is required.Slave unit can be synchronous dynamic random access memory (SDRAM) or direct memory access (DMA) (DMA) etc.
When the bus that moderator sends main equipment A, B, C and D uses request to make response, will give corresponding main equipment the number of the main equipment of response by the AMNum signal wire.In the present embodiment, corresponding as follows respectively to the code name that main equipment is encoded: 0 is main equipment A, and 1 is main equipment B, and 2 is main equipment C, and 3 is main equipment D.In addition, main equipment A and main equipment B are furnished with a thread identification signal wire MthreadID respectively.When certain thread among main equipment A or the main equipment B sends bus and uses request to obtain the moderator response, moderator is given corresponding main equipment the number of the main equipment of response by the AMNum signal wire, and by the MThreadID signal wire corresponding thread number is sent to corresponding thread in this main equipment simultaneously.
Main equipment all is respectively equipped with the various types of signal line with slave unit and links to each other with moderator, is used for transmitting all kinds of control signals in the data transfer operation.As the MDstnum signal is the number that main equipment is given the request slave unit of moderator.In the present embodiment, the code signal of 4 slave units is corresponding as follows respectively: 0 is slave unit A, and 1 is slave unit B, and 2 is slave unit C, and 3 is slave unit D.
The bus that main equipment sends uses request to be divided into different ranks, and each main equipment has a MReq bus request signal line to link to each other with moderator in the present embodiment, and the MReq signal that this signal wire transmits can be used to represent the rank of bus use request.Use request signal to be divided into first and second grades of other bus request by the MReq bus that MReq bus request signal line sends, other bus request of the first order is REQ in the present embodiment, the bus request of second level is CREQ and LREQ, and it is deciphered shown in following table one.
Table one
| MReq | Signal | Explanation |
| 00 | IDLE | There is not request |
| 01 | REQ | General read-write requests |
| 10 | LREQ | The pairing read-write operation request, general and MCmd cooperates.If MCmd is 0, be the read operation of requirement LOCK; If MCmd is 1, be the write operation of removing LOCK. |
| 11 | CREQ | Mandatory read-write requests. |
Wherein MCmd is the read-write operation id signal, and is high low for reading for writing.
The MReq bus is used in the request signal, and therefore CREQ and LREQ, if the MReq that main equipment sends is CREQ or LREQ, often can obtain response than REQ more quickly than REQ priority height.Wherein, the request of LREQ is a kind of read-write operation request of pairing, and what its was asked is the atomic operation of a read-write operation, and owing to this read-write operation need carry out continuously, and therefore the operation that can not insert other is made as the higher request of a kind of priority level with it.
MReq can be set by modes such as programmings when data transmission each time flexibly, so the bus that main equipment sends uses the priority level of request to determine by actual demand.In other embodiments, the bus of MReq uses request signal can set certain grade on demand, and its coding also can change thereupon, to this present technique field personnel's easy to understand and realization.
Also adopted the data mode of a kind of stream bursts (Stream Burst) form in the present embodiment between main equipment and the slave unit, the data mode of stream bursts form is described in detail in Chinese patent application number 03129415.4, this patented claim and the application are submitted to by same applicant, and are incorporated into this by reference and fully.This data mode can transmit mass data once, can comprise a plurality of single data (Single) and a plurality of bursty data (Burst) in the data that each stream bursts transmits.Single data in the same stream bursts or the continuous bursty data of sufficient address can be described as a segmentation burst, and the address between the segmentation burst can be discontinuous, and the different segmentations bursts in stream bursts in the present embodiment can also send to different target slave units.The length that also can require the segmentation burst in an embodiment of the present invention is 2 integral number power, and address align.
Data corresponding to the stream bursts form transmit, each thread in each main equipment or the main equipment is provided with delivery status MLast signal wire, and the MLast signal that transmits in this signal wire has pointed out that this thread in this main equipment or the main equipment requires the state of the data transfer operation of carrying out.For the stream bursts data transfer operation has defined first, second, third and the four or four kind of state, correspond respectively to CONT in the present embodiment, SAME, four kinds of signals of DIFF and LAST are encoded to it respectively as shown in table two.
Table two
| MLast[1:0] | Signal | Explanation |
| 00 | CONT | Represent that a segmentation burst does not finish. |
| 01 | LAST | The end of a stream bursts of expression. |
| 10 | SAME | Represent the end of a segmentation burst, predict next segmentation burst and the same slave unit of this segmentation burst access, and the grade of request of access identical (promptly all being REQ or CREQ). |
| 11 | DIFF | Represent the end of a segmentation burst, predict the next segmentation burst slave unit different, perhaps the grade difference of request of access with this segmentation burst access. |
In data transfer operation, represent segmentation burst also in transport process with the CONT signal, so the pairing data of CONT signal transfer address still is continuous, do not need to do again arbitration.The LAST signal represents then that a complete stream bursts has transmitted and finishes that just need moderator again to all bus to use request do arbitration if will carry out data transfer operation this moment.
SAME and DIFF signal are represented all that segmentation burst has transmitted and are finished, and a stream bursts finishes as yet.Its difference mainly is, the SAME signal is to be used for predicting the next segmentation burst slave unit identical with this segmentation burst access, just address and this segmentation burst may be discontinuous, and next segmentation burst is identical with the grade of this segmentation burst access request, promptly all is REQ or CREQ etc.The DIFF signal then is to be used for predicting the next segmentation burst slave unit different with this segmentation burst access, or the grade of next segmentation burst and the request of this segmentation burst access is inequality.
Similarly, the kind of the data transfer operation state that the coding of MLast also can be according to actual needs adjusts.
When the equipment requirements on the bus uses bus to carry out data transfer operation, at first can send bus and use request to give moderator, judge the request that can preferentially carry out by moderator according to default algorithm.The arbitration that moderator of the present invention can carry out comprises the forward arbitration and oppositely arbitrates two parts.Forward arbitration is meant that the bus that main equipment is sent uses request to arbitrate; Oppositely arbitration is meant needs return data and the bus sent uses request to arbitrate to slave unit in read operation.
With reference to figure 2, moderator comprises forward subordinate phase arbitration modules, forward phase one arbitration modules and reverse arbitration modules in the present embodiment.Give corresponding master device and slave unit behind each signal process forward decoder decode of forward arbitration; Oppositely each signal of arbitration is given corresponding slave unit and main equipment through behind the reverse decoder decode.Forward subordinate phase arbitration modules is to use request to arbitrate to the bus that less important main equipment sends, and arbitration result is sent into the phase one arbitration modules again; The bus that the phase one arbitration modules is then sent important main equipment uses the arbitration result of request and subordinate phase to arbitrate together.In other embodiments, also can omit subordinate phase.
In the subordinate phase arbitration modules not when carrying out arbitration process, be that the subordinate phase arbitration modules is when being in nonbusy condition, the subordinate phase of forward arbitration can begin to carry out new arbitration, and the arbitration algorithm that is adopted can be to be familiar with the various algorithms that person skilled is known.For the sake of simplicity, in the present embodiment, forward subordinate phase arbitration modules is to adopt fixedly precedence algorithm to arbitrate, promptly each less important main equipment is set a definite priority level, when having two or more less important main equipments to file a request at one time, then choose the higher main equipment of priority level to enter the phase one.In the example as Fig. 3, main equipment C and main equipment D are less important main equipment, and its priority level is set at 1 grade and 2 grades respectively.The signal of main equipment C comprises MReq3, and MLast3 and MDstnum3 point out the number of rank, data transfer state and the target slave unit of asking respectively, and similarly, the signal of main equipment D comprises MReq4, MLast4 and MDstnum4.When main equipment C and main equipment D proposed bus simultaneously and use request, according to priority level, the bus that moderator will preferentially choose main equipment C to propose was used request.In the sequential after the bus of main equipment C is used request response end, moderator will use request to make response to main equipment D bus at this moment.The arbitrating signals that the subordinate phase arbitration modules is sent comprises A2Req, and A2Last, A2Dstnum and A2Mnum etc. indicate bus to use the main equipment number of request rank, data transfer state, target slave unit number and response respectively.These arbitrating signals are sent into the phase one arbitration modules and are participated in arbitration as arbitration result.In the present embodiment, suppose that not having other buses when the phase one arbitration modules is arbitrated uses arbitration result that the request participation is arbitrated or the subordinate phase arbitration modules is sent preferentially to be chosen, then send arbitrating signals by the forward demoder, comprise the bus grant signal AGrant shown in the figure and authorize main equipment signal AMNum etc., come successively to respond the bus of main equipment C and main equipment D and use request.
The phase one of forward arbitration at first requires all requests that need participate in arbitrating through the filtrator in the moderator.Filtrator can shield the current request that can't carry out get off according to filtercondition.Be called effective request and passed through the request that filtrator can continue to participate in arbitrating.The present embodiment middle filtrator mainly comprises three filter elements.
First is slave unit busy condition (SBusy) filter element.The slave unit that bus uses request to be visited is current just can pass through filtrator when not being in busy condition, and for example the reception buffer of the slave unit of being visited of requirement in the present embodiment can receive the order that main equipment sends.Filtercondition hereto, each slave unit has disposed a reception buffer in the present embodiment, is used for receiving reception instruction and the related data that moderator provides.Here said reception buffer can be first-in first-out register (FIFO).When the spatial accommodation of the impact damper of slave unit near empty, be that the remaining space of impact damper is can only support that the length of a bursty data or a bursty data add the length of 1 data length the time, send corresponding slave unit busy status signal SBusy signal by this slave unit and give moderator, point out the number of this slave unit in the SBusy signal.
Second is pairing read-write requests control (LREQ) filter element, is to use at the bus of the LREQ type in the present embodiment to ask.Read access for a LREQ request just can be responded when requiring bus not to be in latch mode.If bus is in latch mode, will mask the read access of this LREQ request.At this, bus is in latch mode, just mean that main equipment or other threads that other are before arranged have sent a LREQ request, and this request is being carried out in the read operation process.In the time of so just can preventing that new LREQ request from obtaining bus grant and carry out the read access operation and previous LREQ operation is made a mistake.
The 3rd filter element is last-minute plea controlled filter unit, can be used to guarantee that bus system can handle the effect that a plurality of buses is used request and reached the streamline arbitration continuously.Request for last clock period of each stream bursts that is transmitting, the data transfer state signal ALast signal that moderator need be judged this stream bursts to be determining next arbitrate state, so moderator will shield the request of last clock period of this stream bursts.
Other filter element also can be set in filtrator among other embodiment of the present invention.
As can see from Figure 4, the filtrator of moderator is provided with three control ports, is connecting slave unit busy status signal line, bus latch signal control line and last-minute plea control signal wire respectively.The input end of filtrator receives the bus of autonomous device to use request, the output terminal output of filtrator be the request that through filtrator and not conductively-closed is fallen, be called effective request, moderator will adopt arbitration algorithm that effective request is arbitrated.
Fig. 5-7 is respectively the exemplary sequential chart of three filter element work in the filtrator.As shown in Figure 5, at the Sbusy filter element, after moderator will be delivered to the SBusy signal latch of SBusy control end from each slave unit earlier, filtrator carried out mask operation in conjunction with current SBusy signal and MDstnum signal again, and wherein the MDstnum signal has been indicated slave unit that this request will visit.If there is the number of the indicated slave unit of MDstnum signal identical, just represent that slave unit that this request visits is current can't receive order that filtrator just shields this request at this moment with the slave unit of SBusy effect.As can see from Figure 5, the MReq0 signal uses request signal for the bus that main equipment A sends, and the MDstnum signal indicates the slave unit of this request visit, the effective request signal of MVReq0 signal for exporting behind the process filtrator.The next clock period of Sbusy0 signal after latching comes into force, and makes the operation conductively-closed (be MVReq0 be IDLE) of MReq0 to last clock period of the visit of slave unit A (corresponding MDstnum signal is 0); And the Sbusy1 signal that does not occur coming into force at the filtrator during the visit to slave unit B (corresponding MDstnum signal is 1), therefore the visit to slave unit B is shielded.
Latch the controlled filter unit in bus, be to latch control end in bus to apply an ALock signal, if bus is in latch mode, then the ALock signal is put height, and make mask with the MReq signal of input end and operate, if bus is at latch mode and the MReq signal is shown as LREQ, then filtrator will shield this request.In the exemplary embodiment as shown in Figure 6, the bus request signal that MReq0 and MCmd0 send for main equipment A; AReq and ACmd are the response signal that moderator sends, and expression obtains the rank and the writable status of power request respectively, and AGrant is the authorization signal of moderator; MVReq0 is effective request of the main equipment A that sends of output terminal.During the AGrant signal was height, when AReq is the LREQ type, and ACmd was when being low (being expressed as read request), and bus latchs the ALock signal of control end and puts height; And ACmd is during for high (being expressed as write request), and bus latchs the control end signal and puts low.The ALock signal when being high bus be in latch mode, this moment, moderator will be not be arbitrated other the read operation of LREQ.First LREQ request of MReq0 is read operation among the figure, and the ALock signal is high in first clock period of this LREQ request, and therefore the LREQ that reflects in this clock period from MVReq0 has fallen with regard to conductively-closed.
For last-minute plea controlled filter unit, in one embodiment of the present of invention for the request of last clock period of each stream bursts that is transmitting, moderator can be judged together in conjunction with AGrant, AMNum and ALast signal, when the AGrant signal effective, and AMNum refers to the current main equipment that bus is carried out the stream bursts transmission that occupies, and the request that ALast indicates this main equipment has proceeded to the request of last clock period, and moderator just masks the request of last clock period of this stream bursts.As shown in Figure 7, the MReq0 signal uses request signal for the bus that main equipment A sends, the data transfer state that ALast signal indication moderator sends after to the decoding of this bus request signal, from the AMNum signal sequence current as can be seen occupying bus be main equipment A.The sequential of MVReq0 signal has demonstrated corresponding to the request conductively-closed of last clock period of ALast signal among the figure.
The phase one of forward arbitration is not all can carry out new arbitration at any time, and just can arbitrate when just allowing to arbitrate satisfying certain condition.Generally speaking, the most important condition that can arbitrate is that current moderator is in idle condition the phase one.In the present embodiment, moderator provides Arb_state signal, when this signal is IDLE, and the current idle condition that is in of expression moderator, the i.e. arbitration operation of current no well afoot.
The classification of phase one arbitration in the present embodiment, comprised for first and second arbitration opportunitys, i.e. REQ arbitration opportunity and CREQ arbitration opportunity.Corresponding to these two arbitration opportunitys, machine control signal when being respectively equipped with first and second arbitrations, i.e. machine control signal during AREQ_arb and ACREQ_arb arbitration.
In the present embodiment, the data mode of employing is the stream bursts form, and has stipulated that the MLast signal sends the segmentation bursty data delivery status sign indicating number of main equipment to moderator.Wherein the MLast signal has three kinds of values to be used for representing that current segmentation burst finishes: LAST represents that a complete stream bursts finishes; SAME represents that a stream bursts does not finish as yet, and current segmentation burst finishes, and the slave unit of next segmentation burst access is identical with current segmentation burst; DIFF represents that a stream bursts does not finish as yet, and current segmentation burst finishes, and the slave unit of next segmentation burst access and current segmentation burst are inequality.In the arbitration state machine, when these three kinds of segmentation burst end code occurring, just may enter arbitrate state.In the present embodiment, a stream bursts process can only be interrupted by CREQ level other other request, and other other requests of REQ level can not be interrupted a stream bursts.When the LAST signal occurring, AREQ_arb signal and ACREQ_arb signal are simultaneously effectively; When SAME or DIFF signal occurring, have only the ACREQ_arb signal effective.
Fig. 8 exemplarily with arbitration during opportunity ordered pair this illustrate.The ALast signal is the signal that the forward demoder of moderator sends after the moderator arbitration at the MLast signal that main equipment sends, have four class values corresponding to the MLast signal, be CONT, SAME, DIFF and LAST, the arbitrate state that can be used to the next clock period moderator of auxiliary judgment is to accelerate the bus pipeline processes.The ALast signal has three examples among the figure, is respectively LAST, SAME and DIFF.Stream bursts of LAST signal indication finishes, and two signals of AREQ_arb and ACREQ_arb simultaneously effectively; SAME and DIFF only represent that all a segmentation burst finishes, and stream bursts does not finish, and has only the ACREQ_arb signal effective.
The ACREQ_arb signal all occurs when effectively the segmentation burst in the middle of stream bursts end and stream bursts finishes, and the AREQ_arb signal effectively only occurs when stream bursts finishes, obviously, ACREQ_arb signal effective ratio AREQ_arb signal effectively occurs more frequently, in other words, CREQ arbitrates the time interval on opportunity than the REQ arbitration time interval weak point on opportunity.
Referring to Fig. 9, the arbitration state machine of present embodiment comprises first, second and the three or three state, i.e. ARBLEVEL1, ARBLEVEL2 and IDLE altogether.Wherein ARBLEVEL1 and ARBLEVEL2 are respectively previously described first and second arbitration opportunitys, i.e. REQ arbitration opportunity and CREQ arbitration opportunity.State transition condition between each state is shown in following table three:
Table three
| |
Neither one effectively request is CREQ or LREQ, and having 1 effective request at least is |
| Condition | |
| 2 | When AREQ_arb is effective, and the effective request of neither one is REQ, CREQ or |
| Condition | |
| 3 | Having 1 at least, effectively to ask for instructions be CREQ or |
| Condition | |
| 4 | When AREQ_arb is effective, and the effective request of neither one is REQ, CREQ or LREQ |
| Condition 5 | When effective and AREQ_arb is invalid at ACREQ_arb, have at least 1 effectively request be CREQ or LREQ, and note AEnterST2 is 1 |
| Condition 6 | When ACREQ_arb is effective, and neither one effectively request be CREQ or |
| LREQ, and AEnterST2 is 1, simultaneously the AEnterST2 zero clearing |
Can see that from the progress of work of the arbitration state machine of Fig. 9 moderator is not all to arbitrate at any time, only under ARBLEVEL1 and two states of ARBLEVEL2, just arbitrate.When the Arb_state signal is IDLE, and satisfy condition 1, promptly have only other the effectively request and do not have CREQ or other the effective request of LREQ level of REQ level, when the AREQ_arb signal was effective simultaneously, moderator entered the ARBLEVEL1 arbitrate state.Under the ARBLEVEL1 arbitrate state, moderator can use request to arbitrate to REQ, CREQ and other bus of LREQ level that main equipment sends.When the Arb_state signal is IDLE, and satisfy condition 3, as long as CREQ or other the effective request of LREQ level are promptly arranged, and whether no matter other the effective request of REQ level arranged, and have the ACREQ_arb signal effective simultaneously, then moderator enters the ARBLEVEL2 arbitrate state.Under the ARBLEVEL2 arbitrate state, moderator only uses request to arbitrate to CREQ or other bus of LREQ level that main equipment sends, and other bus of REQ level uses request not participate in arbitration.
Can see also that from Fig. 9 two states of ARBLEVEL1 and ARBLEVEL2 also can be changed mutually in certain condition in the arbitration state machine.Therefore, in the present embodiment, introduce the AEnterST2 signal, be used for writing down interrupted arbitration scene.When moderator is just arbitrated under the ARBLEVEL1 state, owing to effective request of higher level occurs,, need the conversion arbitrate state under the ARBLEVEL2 state as CREQ or LREQ request, note AEnterST2 signal is 1.Like this, be under 1 the situation at the AEnterST2 signal, after the arbitration operation under the ARBLEVEL2 state is finished, there are not CREQ or other the effective request of LREQ level if having only other the effective request of REQ level, moderator will not arbitrated again, but turn back to original arbitration scene, and when returning with the zero clearing of AEnterST2 signal.When the conversion arbitrate state is arbitrated, need to keep the scene, inside of moderator, the semaphore that keeps temporarily is placed in the impact damper, and the semaphore that keep mainly contains moderator and gives the number AMNum of response main equipment of main equipment and number ASNum of the response slave unit that moderator is given slave unit etc.Directly be transformed into ARBLEVEL2 state following time from the IDLE state, after moderator is finished arbitration task under the ARBLEVEL2 state, moderator will be arbitrated whole effective requests again.
Moderator carries out in the arbitrated procedure, when the ACREQ_arb signal is effective, if moderator is directly to be transformed under the ARBLEVEL2 state under the ARBLEVEL1 state, for preventing that the corresponding slave unit that effective bus uses request to visit from having the situation of overflowing, and judges the situation that slave unit is current with slave unit busy status signal SBusy signal as basis for estimation in the present embodiment once more.The reception buffer of slave unit is current can't receive the time, this slave unit promptly sends the SBusy signal, moderator with the SBusy signal latch after, use the signal MDstnum of expression target slave unit number in the request to carry out mask operation with bus, when if the two pairing slave unit is consistent, then this bus uses request that conductively-closed is fallen.
Under the ARBLEVEL1 state, moderator adopts general algorithm, and all kinds of buses that each main equipment is sent use request to arbitrate liberally, therefrom select a request, and to sending the main equipment transmission authorization signal of this request, the beginning data transmitted after main equipment was received authorization signal.Under the ARBLEVEL2 state, it is that the request of CREQ and LREQ is arbitrated to priority level that moderator will adopt general algorithm, therefrom select a CREQ or LREQ request, and the main equipment that sends this request is transmitted authorization signal, main equipment begins data transfer operation after receiving authorization signal.Other request of REQ level will be left in the basket under the ARBLEVEL2 state.The general algorithm here refers to that single cycle arbitration algorithm or other are the known arbitration algorithm of present technique field personnel, do not repeat them here.
Moderator shown in Figure 2 also comprises a reverse arbitration modules.Main equipment A and main equipment B have multithreading in the present embodiment, and when a thread was obtained the authorization the use bus, moderator can provide the number of main equipment and the number of this thread.The request of a thread is not performed when complete, for example when the slave unit at its data place of reading is also unripe, therefore allow other threads in the same main equipment to send request, the situation that the read data of several different threads requests returns simultaneously from each self-corresponding different slave unit may occur.In other embodiments, the situation returned simultaneously from the different slave units at place separately of the read data that several different master devices request also may occur.The reverse arbitration modules of moderator can use request to arbitrate to the bus that each different slave units return read data in this case.Be similar to the forward arbitration, after the reverse request that moderator sends slave unit was oppositely arbitrated, moderator can provide effective authorization signal ARGrant signal, authorized the slave unit of choosing to occupy bus and carried out data return.The ARGrant signal is shared by each slave unit, is effective when high level state.
Present embodiment also is divided into important slave unit and less important slave unit with slave unit, as, slave unit A, slave unit B and slave unit C are important slave unit, and slave unit D is less important slave unit.Carry out reverse data when transmitting or carry out reverse data to transmit target be the data of less important main equipment when transmitting at less important slave unit, the data transfer rate of employing is lower than the data transfer rate between important main equipment and the important slave unit.For example, the data transfer rate when between important main equipment and important slave unit is 1 data/clock period, less important slave unit carry out reverse data when transmitting or reverse data when to transmit target be less important main equipment data transfer rate be 1 data/2 clock period.In speed is that moderator was not arbitrated during the reverse datas of 1 data/2 clock period transmitted, so the reverse arbitration of moderator also has arbitration opportunity.
Figure 10 exemplarily describes the arbitration of reverse arbitration opportunity.The ARSNum signal indication carries out the slave unit that reverse data transmits among the figure, ARGrant signal indication moderator sends response to slave unit and the corresponding main equipment that reverse data transmits, the target main equipment that ARMNum signal indication reverse data transmits, arbitration signal ARArb forbid on opportunity are represented when low to allow arbitration is made in effective request of the slave unit of reverse transmission.As can be seen from Figure 10, slave unit A is important slave unit, and main equipment B is important main equipment, and when main equipment B carried out the reverse data transmission, the ARArb_forbid signal was low, can arbitrate at slave unit A; Slave unit B is during main equipment C carries out the reverse data transmission, because main equipment C is less important main equipment, the ARArb_forbid signal will uprise, and can not arbitrate; Slave unit C and D are less important slave unit, and when the two and any main equipment carried out the data transmission, the ARArb_forbid signal all can uprise, and can not arbitrate.
Reverse request also is divided into different brackets in the present embodiment, comprises other reverse request of SREQ level and other reverse request of CSREQ level, and wherein other reverse request priority of CSREQ level is higher than other reverse request of SREQ level.When moderator is arbitrated reverse request, at first respond other reverse request of CSREQ level.Same other reverse request of level then decides by the fixed priority order of the slave unit that sends reverse request.For example, the fixed priority order of slave unit A, B, C and D can be set from high to low, like this, if slave unit A, B, C and D send reverse request simultaneously, and all effective, then moderator is with the reverse request of preferential answering slave unit A; And if having only B and C to send reverse request simultaneously and when being effective request, moderator is with the reverse request of preferential answering slave unit B.In other embodiments, also can adopt general algorithm that reverse request is arbitrated, its variation should belong to the present invention equally.
The foregoing description is just in order further more clearly to describe the present invention, but not limitation of the present invention.Be to be understood that the present invention is not limited to the elaboration that embodiment does, anyly all should be included within the spirit and scope in this invention based on modification of the present invention and equivalent of the present invention.
Claims (10)
1. a moderator is used for centralized bus system the bus use request that each equipment sends is arbitrated, and each equipment in the described bus system is divided into main equipment and slave unit, it is characterized in that described moderator comprises:
Forward phase one arbitration modules;
Forward subordinate phase arbitration modules,
Described main equipment also is divided into important main equipment and less important main equipment, the bus that described forward subordinate phase arbitration modules is sent less important main equipment uses request to arbitrate, the bus that described forward phase one arbitration modules is sent the arbitration result and the important main equipment of described subordinate phase arbitration modules uses request to arbitrate together
Described forward phase one arbitration modules comprises arbitration state machine, this arbitration state machine have correspond respectively to first and second the arbitration opportunity first and second arbitrate states, and the bus request that main equipment sends is divided into first rank and the second level bus is used request, wherein said second level bus is used the priority of request to be higher than the first rank bus and is used request, wherein said first arbitration uses request to arbitrate to the described first and second rank buses opportunity simultaneously, and described second arbitration only uses request to arbitrate to the second level bus opportunity.
2. moderator as claimed in claim 1 is characterized in that it is general read-write requests that the described first rank bus is used request, and it is the read-write operation request or the mandatory read-write requests of pairing that described second level bus is used request.
3. moderator as claimed in claim 1, it is characterized in that described forward phase one arbitration modules also comprises filtrator, be provided with filter element in the filtrator, the bus that is used for that main equipment is sent uses request to filter, and the bus of process filtrator uses request as effectively asking to participate in arbitration.
4. moderator as claimed in claim 1, it is characterized in that adopting between described main equipment and the slave unit data mode of stream bursts form, have one or more segmentation bursts in the stream bursts, and the stream bursts data transfer operation has first, second, third and the four or four kind of segmentation bursty data delivery status, and wherein the first segmentation bursty data delivery status represents that a segmentation burst does not finish; The second segmentation bursty data delivery status is represented the end of a stream bursts; The 3rd segmentation bursty data delivery status represents that a segmentation burst finishes, and stream bursts does not finish, but the slave unit of next segmentation burst access is identical with current segmentation burst; The 4th segmentation bursty data delivery status represents that a segmentation burst finishes, and stream bursts does not finish, but the slave unit of next segmentation burst access is different with current segmentation burst.
5. moderator as claimed in claim 4, machine control signal when it is characterized in that described first and second arbitrations are respectively equipped with first and second arbitrations opportunity, machine control signal is simultaneously effectively during described first and second arbitrations when the described second segmentation bursty data delivery status, and when the described the 3rd or the 4th segmentation bursty data delivery status, have only described second when arbitration machine control signal effective, the time interval on described first arbitration opportunity is longer than the time interval on described second arbitration opportunity.
6. moderator as claimed in claim 1 is characterized in that described arbitration state machine judges the situation of slave unit by a slave unit busy status signal.
7. as the described moderator of above-mentioned arbitrary claim, it is characterized in that described moderator also includes reverse arbitration modules, be used for the reverse request of the operation of the return data of a plurality of equipment is arbitrated.
8. moderator as claimed in claim 7, it is characterized in that described reverse request is divided into the first rank reverse request and second level reverse request, wherein the priority of the first rank reverse request is lower than the reverse request of second level, when described reverse arbitration modules is arbitrated reverse request, at first respond the reverse request of second level, other reverse request of same level is then decided with the fixed priority order of the slave unit that sends reverse request.
9. referee method, being used for centralized bus system arbitrates the bus use request that each equipment sends, each equipment in the described bus system is divided into main equipment and slave unit, it is characterized in that described referee method comprises phase one arbitration and subordinate phase arbitration
Described main equipment also is divided into important main equipment and less important main equipment, the bus that described subordinate phase arbitration is sent less important main equipment uses request to arbitrate, the arbitration of described phase one uses request to arbitrate together to the bus that the arbitration result and the important main equipment of described subordinate phase arbitration sends
Use arbitration state machine to arbitrate in the described phase one arbitration, this arbitration state machine have correspond respectively to first and second the arbitration opportunity first and second arbitrate states, and the bus request that main equipment sends is divided into first rank and the second level bus is used request, wherein said second level bus is used the priority of request to be higher than the first rank bus and is used request, wherein said first arbitration uses request to arbitrate to the described first and second rank buses opportunity simultaneously, and described second arbitration only uses request to arbitrate to the second level bus opportunity.
10. referee method as claimed in claim 9 is characterized in that also including reverse arbitration, is used for the reverse request of the operation of the return data of a plurality of equipment is arbitrated.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090037635A1 (en) * | 2006-03-17 | 2009-02-05 | Shanghai Magima Digital Information Co., Ltd. | Bus arbitration device |
| CN101026556B (en) * | 2007-01-10 | 2010-04-21 | 华为技术有限公司 | Arbitrating method and device for supporting service quality |
| CN101471856B (en) * | 2007-12-26 | 2011-01-12 | 无锡江南计算技术研究所 | Arbitration method and arbitrator |
| CN101887382B (en) * | 2010-06-28 | 2016-11-23 | 南京中兴软件有限责任公司 | The referee method of dynamic priority and device |
| CN102207918B (en) * | 2011-06-07 | 2014-04-23 | 北京北大众志微系统科技有限责任公司 | On-chip bus arbitration method and on-chip bus arbitration device |
| CN108183845A (en) * | 2017-12-06 | 2018-06-19 | 山东航天电子技术研究所 | A kind of bus contention method based on bit arbitration |
| CN108304333B (en) * | 2017-12-26 | 2021-04-13 | 中国科学院长春光学精密机械与物理研究所 | One-master multi-slave bus |
| CN108197046A (en) * | 2017-12-30 | 2018-06-22 | 盛科网络（苏州）有限公司 | A kind of system and method for realizing atomic operation |
| JP7139866B2 (en) * | 2018-10-18 | 2022-09-21 | トヨタ自動車株式会社 | vehicle arbitration system |
| CN111090600B (en) * | 2019-12-09 | 2021-07-16 | 苏州浪潮智能科技有限公司 | Bus sharing method |
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| CN1067323A (en) * | 1991-05-28 | 1992-12-23 | 国际商业机器公司 | Personal computer with local bus arbitration |
| CN1184973A (en) * | 1996-12-10 | 1998-06-17 | 国际商业机器公司 | Method and apparatus for equalizing grants of data bus to primary and secondary devices |
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