NL7908654A - ANALOG / DIGITAL INVERTER WITH STAGE APPROACH OF THE ANALOGUE SIGNAL TO BE CONVERTED BY A DIGITAL SIGNAL. - Google Patents

Description

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Analog / digital converter with a cascading approach to convert the analog signal into a digital signal.

The invention relates to an analog / digital converter with a graduated approximation of an analog signal to be converted by a digital signal, wherein at one input of a comparator the analog signal and at the other input of the comparator the output signal of a digital / analog converter is supplied, which digital / analog converter is supplied with the digital signal at its input.

Such analog / digital converters are known from the book of Lange 'Digital-Analog-bzw. Analog-Digital-Wandlung "Oldenbourg verlag, Munich, Wien, page 25 to 45. These may be analog / digital converters with a continuous step-wise approach, whereby the digital value is changed by further counting of a forward counter Likewise, it may be a successful approach in which the various digital locations of a memory are queried sequentially by a control logic.

The memory can work in pure binary as well as in BCD code.

In all this method, the accuracy of the generated digital value is determined by the lowest bit (LSB) of the unit making up the digital value, ie, for example, the counter or the memory.

The object of the invention is now with a digital / analog converter of the type mentioned in the present invention, the resolving power compared to the known digital / analog converters without considerably increasing the amount of additional material.

According to the invention, this object can be fulfilled in that a sawtooth function is added to the analog signal or to the output signal of the digital / analog converter, the maximum value of which is approximately equal to the magnitude of the lowest bit of the digital / analog converter, the approximate duration of which corresponds to a multiple of the stepped approximate duration, and that during the period of the sawtooth function, the arithmetic modulated value of a 7908654. >. ". 2 number of digital signals occurring after a cascading approximation are formed.

By adding a sawtooth function with the maximum value of approximately the least significant bit of the digital / analog converter, for example with the analog signal and by calculating the arithmetic mean over a number of transformations during the occurrence of the sawtooth function, increases the resolution. The more transformations are involved in the average value, the greater the increase in the resolving power. For example, do you use an 8-bit digital / analog converter with a 12-bit linearity and determine the solution?

Omnipower over 2 = 16 transformations, this results in a resolving power corresponding to that of a 12 This 15 inverter. An advantage of the digital / analog conversion according to the invention therefore consists in the use of a simpler (with less resolving power) and thus cheaper digital / analog converter. Moreover, assuming the above example, only an 8 bit bus coupler is necessary. This number of 8 bits is standardized for many coupling circuits. Furthermore, the approximation program need only be designed for this 8 bit. In addition, only a 12 bit addition of the inverter results is necessary.

If the maximum value of the sawtooth function does not actually correspond to the least significant bit of LSB, or if its duration is not exactly equal to a multiple of a transformation period, the resultant increase in the resolution is slightly reduced, but this does not change the 50 principle.

As the sawtooth function, a continuously rising function can be used, such as is provided, for example, by a conventional sawtooth generator. according to a further embodiment of the invention, for the sawtooth function, a step function can also be used with steps of the same size, the duration of each step being equal to the duration of the stepwise approach. For example, the average must be determined over 2m transformations. , then the greatest improvement of the resolving power arises with a 40 stage function with 2m stages each with a size of 1 / 2m LSB.

7908854 3 • For each conversion in the context of the 2m transforms, the signal value at the input of the comparator to which the sawtooth function is applied changes over the 2m part of the lowest bit of the digital / analog-5 converter. For a given number of transformations, a digital value is initially created which would also be obtained without the sawtooth function. This digital value corresponds to an analog value which generally differs from the value of the analog signal to be converted. If the sum of this deviation and the sawtooth function corresponds to the value of the least significant bit LSB, the determined digital value changes in this and the following approaches, ueze is increased by an ISB. The ratio between the number of transformations from which the increased digital value results and the total number of transformations involved in the formation of the average value can now be determined the additional digital positions of lower dignity.

The sawtooth function can also be supplied from the outside, just like the analog signal to be converted. In a preferred embodiment of the invention the procedure is such that the digital / analog converter is briefly controlled before the start of each approximation such that its output signal determined by a memory element (sample and hold circuit), possibly after voltage division. corresponds to the required step value of the step function. An external function provider can therefore be omitted.

In order to make the analog / digital conversion according to the invention as insensitive as possible to disturbing alternating voltages, it is preferable to adjust the period of time in which the arithmetic mean value is formed to the period duration of any disturbing added to the analog signal. AC voltage. This achieves a quasi-integrating analog-to-digital conversion, as has already been described for known analog-to-digital converters in the book "Prozessrechner" by Anke, Kaltenecker, Oetker, Oldenbourg verlag, München, Yiien, 1970, p. 114 and " 115

For an analog / digital converter with a digital 4-0 value converter, a comparator and a digital / analog converter 7908654 4 »• ^. In order to carry out the analog / digital conversion according to the invention, it is recommended that the digital value converter and the digital / analog converter are designed for n bits, the converter having a linearity of n + m bits and that an adder for n + m bits is present, to which the signals of the digital value shaper are applied after each of the 2m cascading approximations. As a digital value generator, on the one hand, forward counters controlled by a clock pulse generator can be used, or a digital memory controlled by means of a control logic. Particularly preferred embodiments arise when the digital value generator and the option are part of a microprocessor. .

15. In the hitherto known embodiments, analog-to-digital conversion only always involved a single analog signal to be converted, however, the analog-to-digital conversion according to the invention or an analog-to-digital converter operating according to this method can advantageously are also used for k analog signals. For example, a microprocessor and a digital / analog converter as well as k input ports and k comparators may be present. Instead of the k input ports, an input port and a digital multiplexer can be used, ie k comparators can be replaced by a single comparator and an analog multiplexer.

In principle, any digital / analog converter can be used for the analog / digital conversion according to the invention. For example, one chooses a digital / analog converter J> 0 mer with resistors of a certain value, as is known from the book by Lange "Digital-Analog bzw. Analog-Digital-Wandlung" Oldenbourg Verlag Munich Wien 1974-, p. 23, Figure 5, then the sawtooth function can simply be switched to the non-inverting input of the summation amplifier and thus be added to the analog output signal of this digital / analog converter.

In the following, with reference to Figures 1 to. and explaining the invention in more detail. Figure 1 shows the time processing of the analog / 40 digital conversion according to the invention.

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Accordingly, Figure 2 shows the results of eight transformations during the occurrence of a sawtooth function.

FIGS. 3 ^ show two different embodiments of an analog / digital converter for each analog signal to be converted. FIG. 5 shows an analog / digital converter for a number of analog signals.

Figure 1 shows the time processing of a step-by-step approval. For the sake of clarity, for example, a 4-bit resolution has been chosen, ie it is assumed that a digital / analog converter with also only four digital positions is used. In the upper part 15 of figure 1, the output voltage of such a digital / analog converter is plotted with respect to time t. At the same time, an analog signal IL to be converted is plotted as a straight line with respect to the time axis. In the lower part of figure 1, the output signal of a comparator, which results from the output signal of the digital / analog converter and the analog signal to be converted, is also shown with respect to time. It is assumed here that the output signal of the comparator has the value 1 as long as the output signal of the digital / analog converter is smaller than the analog signal to be converted.

The cascading approvation begins at time t ^.

In each other, the individual digital positions of the digital / analog converter are scanned. At time t £ 30 approximation has ended. For this special example, the binary number 1010 is created, corresponding to the decimal value 10.

In Fig. 2, again with respect to Gfe time, but now with a different time scale, the results of 8 transformations 35 occurring at equal mutual intervals T / 8 are shown. A monotonic increasing sawtooth function with a period duration T and a maximum value of the least significant bit LSB of the digital / analog converter is added to the analog signal to be converted. The in-40 intervals 1/8 correspond to the duration t ^ -t ^ j 7908654 6

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* Of a full cascading approximation or transformation as illustrated in Figure 1.

As further shown in figure 2, the eight transformations shown in the binary system result in three times 5 the values 1010 and five times the values 1011. In the decimal system, therefore, three times the value 10 and five times the value 11 arise. The value of these acbt transformations is in the decimal system 10, 625 and in the binary system 1010, 101. It is also assumed that the individual transformations are made with a digital / analog converter with four digital positions. As can be seen from these results, an increase in resolution by three binary positions is achieved compared to the transformation as illustrated in Figure 1.

Figure 3 shows an analog / digital converter according to the invention provided with a digital value converter 1, composed of a clock pulse generator 2, a control logic circuit 3 and a digital memory 4. For each cascading approximation, the control logic arrangement sets up the digital memory 4- zero. First, the arc-worthy position of the memory, so dQ is set to 1. The other digital positions remain at 0. This digital signal is supplied to a digital / analog converter, to which, in addition to a reference voltage Uref, a voltage UBt corresponding to the sawtooth function is supplied. The analog output signal of the digital / analog converter 5 is applied to one input of a comparator 6, while the analog input Ue is applied to the other input. If the analog signal U_ is greater than the analog output voltage of the digital / analog converter 5, the highest digital position dn of the digital memory remains equal to 1; in the other case dQ becomes equal to 0. Then the next digital position is set and again the comparison with the analog signal U_ is carried out. This is continued until the digital position d, j of the digital memory 4 is reached. The first transformation has thus ended. Via the control logic, the digital 40 value determined in this way is applied to an adder 7 · Subsequently, 7908654 - - Ss 7 starts a new conversion.

The digital memory and the digital / analog converter 3 are designed for n hits. If an average value must now be formed over 2m transformations, the adder 7 must be designed for n + m hits. At the end of "2" transformations, a value then arises in the adder 7, which, by simple displacement of the decimal point for the last m digital positions, corresponds to the average mean value. This value is determined via an indication. unit 8 made visible or executed.

In this example, the duration of the sawtooth function is equal to 2nL times the individual transformations.

The maximum value of the sawtooth function corresponds to the size of the lowest bit of the digital-15 / analog converter 3.

In the exemplary embodiment of FIG. 4, the digital value converter, adder and indicator unit are parts of a microprocessor 101. In addition, as in the exemplary embodiment of FIG. 3, a digital / analog converter 3 and a comparator 6 are provided. The sawtooth function supplied to the digital / analog converter 3 in this exemplary embodiment consists of a step function whose separate stages are generated for each conversion by means of the microprocessor 10 and the digital / analog converter 3 itself. For this purpose, the switch S1 is closed for each conversion under the control of the microprocessor. At the same time, a digital input signal is applied to the digital / analog converter, the corresponding analog value of which is a measure of the respective stage 30 of the stage function. This analog signal is stored for the subsequent conversion. In the simplest case, a capacitor C1 is sufficient for this, but a sampling / holding device can also be used. In this embodiment, the capacitor voltage is connected to a voltage divider with the resistors R1 and R2. The actual sawtooth voltage U ^ is taken off in this clamping divider.

Figure 5 shows an analog-to-digital converter similar to that of Figure 4-, but output for k analog signals up to and including ·. If this embodiment 4-0 assumes that the digital-to-analog converter 5 7908654 # 5¾.

8-- t- is an 8 bit converter, and one wants to achieve a resolution of about 12 bit, then the great advantage is that one also suffers from an 8 bit bus coupling between the microprocessor 10 and the digital / analog -5 converter 5. This 8 bit bus coupling corresponds to the usual value at the outputs of microprocessors. Also, the approval program executed in microprocessor 10 need only be for 8 bits. In addition to the partly simpler and thus cheaper circuit elements, the desired resolving power thus also results in the advantage of a faster analog / digital conversion. In the case of a higher resolution digital / analog converter, the individual digital positions should be controlled in two successive steps via the 8 bit bus coupler of the '15 output port. In that case, the approximation program should also be intended for the larger number of digital positions.

7908654

Claims (6)

1. Analog / digital conversion with cascading approximation of an analog signal to be converted by a digital signal, wherein at one input of a comparator the analog signal and at the other input of the comparator the output signal of a digital Analog converter is supplied, with the digital signal being supplied to the input of the digital / analog converter, characterized in that with the analog signal or 10 with the output signal of the digital / analog converter (5) a sawtooth function is added, the maximum value of which is approximately equal to the size of the least valuable bit of the digital / analog converter (5) and whose approximate duration corresponds to a multiple of the duration required for the cascading approximation, and that during the time of the sawtooth function the arithmetic mean value of a number of digital signals occurring each time after a cascading approximation is formed. Analog / digital conversion according to claim 1, characterized in that the sawtooth function is a step function with steps of the same size and that the duration of each step is equal to the duration of the step approximation. Analog / digital converter according to claim 2, characterized in that the digital / analog converter (5) is briefly controlled before the start of each approximation such that it is supplied to memory device (sample) and sample controller. output signal 30, possibly after voltage division, corresponds to the required step value of the step function. 4-. Analog / digital conversion according to any one of the preceding claims, characterized in that the time required for determining the arithmetic mean is tuned to the period of time of a disturbing AC voltage added to the analog signal. 4 * »* EVERCLnSION-S. Analog / digital converter with a digital value converter, a comparator and a digital / analog converter for carrying out the analog / digital conversion according to any one of the preceding claims, characterized by 7908654 jfi. the digital value converter (1) and the digital / analog converter '(5) are for n bits, the converter (5) having a linearity of n + ia bits and an adder (7) for n + m bits are provided to which the signals of the digital value shaper (1) are applied after each of the 2m stepwise approvals. Analog / digital converter according to claim 5, characterized in that the digital value converter (1) and the adder (7) form parts of a microprocessor (10). ************** 7008654 -