GB2227895A - Analog-to-digital converter - Google Patents

Abstract

An A/D converter is provided, particularly for use in microprocessors having elements which are limited to processing to a predetermined number of bits of resolution. A two-stage comparison is made at 13 with a threshold supplied by a digital to analog converter 11 and which is shifted by half of the least significant bit from the first comparison to the second. The result is at least one extra bit of resolution. <IMAGE>

Description

Analog-to-Digital Converter This invention relates to an analog-to-digital converter, such as for use in a microprocessor of predetermined architecture, e.g. one having an eight-bit data bus structure, or other predetermined bus width.

Eight-bit analog-to-digital converters are convenient to use with eight-bit data buses and an example can be found in the Motorola MC68HC05 microprocessor. It is often, however, desirable to achieve a higher resolution than can be given directly from the converter. This is particularly the case when the accuracy of the A/D converter is the limiting factor with regard to the accuracy of a chain of elements. As an example, many applications using external analog parameters require overall accuracy better than 1%. An eight-bit A/D converter having non-lir.earity of + or - 1/2 of the least significant bit (LSB) has a resolution of 0.4%. This means that a maximum of 0.6% accuracy must be obtained for the rest of the devices along the chain, for example pressure sensors, amplifiers, etc., to be within the tolerance of 1%.If it were possible to use a 9-bit A/D converter, an improvement of 0.2% resolution would be achievable in the converter, allowing the maximum accuracy in the rest of the chain to be reduced to 0.8%. A broadening of this order of magnitude of the tolerance for these other components can be significant, because it allows for the use of cheaper transducers, operational amplifiers and other external passive components.

In order to achieve 9-bit accuracy in an 8-bit architecture A/D converter and microprocessor, it would be necessary to have a separate storage location for the extra bit. This would require substantial redesign of the A/D converter.

It would be desirable to provide a simple means of achieving greater resolution in an A/D converter having elements which are limited to processing a predetermined, lower number of bits of resolution.

According to the present invention, an analog-to-digital converter is provided for converting an input signal to digital form, comprising: a digital-to-analog (D/A) converter for providing an analog reference signal; a comparator for comparing the input signal with the reference signal; means responsive to the comparison for providing the D/A converter with a digital data byte which is representative of the input signal to a predetermined number of bits of resolution so as to determine a first digital value of the level of the signal to that resolution; means for storing the first digital value; means for shifting the level of the reference signal independently of the comparison by an amount equal to a fraction of the incremental change in reference signal resulting from a change in the least significant bit (LSB) of the data byte;; means for comparing the input signal with the shifted reference signal and determining at least a second digital value of the level of the input signal; and means for calculating the level of the input signal, from the digital values so obtained, to a resolution greater than the predetermined number of bits.

By this means, a 2-stage conversion can be carried out to give one additional bit of resolution. The resulting resolution is greater than for the basic comparison operation.

The level shifting means may be arranged to shift the relevant level by an amount equal to half of the incremental change in reference signal resulting from a change in the least significant bit of the data byte. It will be appreciated, however, that the shift could be, for example, 1/4 of the incremental change, in which case four digital values of the level of the signal would be necessary, giving two extra bits of resolution.

In order to achieve the level shift, an extra capacitor may be provided in the D/A converter, which can be alternately introduced to the circuit to give an offset of + or - 1/4 of the least significant bit. Thus it can be seen that the invention has the advantage of requiring very little additional circuitry.

A preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates an analog-to-digital converter in accordance with the invention; Figure 2 represents part of the D/A converter of Figure 1 and Figure 3 is a conversion diagram of the A/D converter of the invention.

Referring to Figure 1, the A/D convertor of the preferred embodiment comprises a successive approximation register 10, a D/A converter 11 having an output 12 and a comparator 13 having positive and negative inputs 14 and 15 and an output 16. The register 10 has an input 20 and a data bus 21 connected to a memory and logic unit 22.

The convertor operates as follows. An analog voltage to be converted is applied to input 14 of comparator 13.

Simultaneously, register 10 provides a digital data byte on bus 21 to D/A converter 11, which provides a reference signal on its output 12. This reference signal is applied to the negative input 15 of comparator 13 and, according to the result of the comparison, a positive or negative signal results at output 16. This signal is applied to input 20 of register 10. The operation of register 10 in response to this signal is described in Application Note 716, Part V, of T. Henry publised by Motorola Inc. In this manner, the data in register 10 represents a digital conversion of Vin, to the best resolution the circuit can provide.

The circuit so far described operates in accordance with the prior art.

D/A converter 11 comprises a number of capacitors which, when selected by respective data bits from register 10 contribute towards the voltage at output 12. The capacitor circuit of D/A converter 11 of the preferred embodiment of the present invention is shown in Figure 2. From this figure, one capacitor is shown for each of the data bit lines of bus 21 from register 10. The capacitors have different values according to the weighting of the data bit which each one represents, as shown in the diagram. Thus, the capacitor 23 corresponding to the least significant bit is shown as having unit capacitance, the capacitor corresponding to the next most significant bit has double the unit capacitance and so on.

For convenience of size the fourth and fifth capacitors are separated by a series capacitor 24, which, together with capacitor 25, create a difference weight of 16 between the upper and lower blocks of capacitors and need not be described in detail. At the left hand end of the array of capacitors, there can be seen a capacitor 26 having a value equal to half the value of capacitor 23, and a further capacitor 27 equal to 1/4 of the value of capacitor 23. Capacitor 27 is additional to those capacitors to be found in prior art D/A converters.

Whereas in prior art converters capacitor 26 provides a permanent offset to the signal on output 12 equivalent to half of the incremental voltage change of the D/A converter (i.e.

half of the least significant bit voltage change), in the present invention this capacitor 26 can selectively be switched into the circuit by switching means (not shown). In addition, capacitor 27 provides a continuous offset of one quarter of the incremental voltage change. In other words, the total offset can be one quarter or three quarters of the voltage representing the least significant bit. This is represented in the diagram of Figure 3, where long dashed lines show the situation where capacitor 26 provides no offset, while the short dashed lines show the situation where capacitor 26 provides a positive offset. The bold lines represent the equivalent diagram for a prior art converter.

The result of the extra capacitor is to shift the output of D/A converter by + or - one quarter LSB.

As an alternative to the circuit described, capacitor 26 can provide a permanent offset of 1/2 LSB while capacitor 27 selectively provides a positive or negative 1/4 LSB offset.

The operation of the preferred embodiment of the converter is as follows. Capacitor 26 is switched out of the circuit and the conversion is carried out as before, giving a first value of the level of Vin on bus 21. This value is stored in memory and logic unit 22. Capacitor 26 is now switched into the circuit, whereby it provides a positive offset of 1/2 LSB over and above the offset of capacitor 27, and the conversion is carried out once again, to provide a second value of the level of Vin. The first and second values are simply added in digital addition means within the memory and logic unit 22, and the result of the addition is a representation of Vin to nine bits of resolution. The quantisation error is + or - 1/4 LSB (as opposed to + or - 1/2 LSB for the prior art).

The order of switching could, of course, be reversed to give the additional offset first.

It will, of course, be understood that the above description has been given by way of example only, and that modifications of detail can be made within the scope of the invention.

Claims (7)

1. An analog-to-digital (A/D) converter for converting an input signal to digital form, comprising: a digital-to-analog (D/A) converter for providing an analog reference signal; a comparator for comparing the input signal with the reference signal; means responsive to the comparison for providing the D/A converter with a digital data byte which is representative of the input signal to a predetermined number of bits of resolution so as to determine a first digital value of the level of the signal to that resolution; means for storing the first digital value; means for shifting the level of the reference signal independently of the comparison by an amount equal to a fraction of the incremental change in reference signal resulting from a change in the least significant bit (LSB) of the data byte;; means for comparing the input signal with the shifted reference signal and determining at least a second digital value of the level of the input signal; and means for calculating the level of the input signal, from the digital values so obtained, to a resolution greater than the predetermined number of bits.

2. An A/D converter according to claim 1, wherein the D/A converter comprises a plurality of capacitors, including one capacitor corresponding to each of the bits of the data byte, the capacitors corresponding to higher order bits being of higher effective value than those corresponding to lower order bits, wherein the level adjusting means comprises a further capacitor having an effective value of a fraction of the value of the capacitor corresponding to the LSB and wherein means are provided for controlling the contribution of the further capacitor to the level of the reference signal.

3. An A/D converter according to claim 2, wherein the value of the further capacitor is half that of the capacitor corresponding to the LSB.

4. An A/D converter according to claim 3, wherein means are provided for providing a continuous offset contribution to the level of the reference signal equivalent to one quarter of the LSB.

5. An A/D converter according to claim 4, wherein the value of the further capacitor is one quarter of the capacitor corresponding to the LSB and the means for controlling the contribution of the further capacitor are arranged to alternately make that contribution positive or negative.

6. An A/D converter according to any one of the preceding claims, wherein addition means are provided for adding the first and second digital values of the input signal levels, thereby providing the greater resolution value of the signal.

7. An A/D converter substantially as hereinbefore described with reference to the accompanying drawings.