NL7713708A - Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang. - Google Patents

Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.

Info

Publication number
NL7713708A
NL7713708A NL7713708A NL7713708A NL7713708A NL 7713708 A NL7713708 A NL 7713708A NL 7713708 A NL7713708 A NL 7713708A NL 7713708 A NL7713708 A NL 7713708A NL 7713708 A NL7713708 A NL 7713708A
Authority
NL
Netherlands
Prior art keywords
type
buffer memory
variable output
information buffer
fixed input
Prior art date
Application number
NL7713708A
Other languages
English (en)
Dutch (nl)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL7713708A priority Critical patent/NL7713708A/xx
Priority to GB7847708A priority patent/GB2009980B/en
Priority to DE19782853240 priority patent/DE2853240A1/de
Priority to FR7834813A priority patent/FR2411468A1/fr
Priority to JP53153607A priority patent/JPS5921055B2/ja
Publication of NL7713708A publication Critical patent/NL7713708A/xx
Priority to US06/157,132 priority patent/US4314361A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
NL7713708A 1977-12-12 1977-12-12 Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang. NL7713708A (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL7713708A NL7713708A (nl) 1977-12-12 1977-12-12 Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.
GB7847708A GB2009980B (en) 1977-12-12 1978-12-08 Data buffer memory
DE19782853240 DE2853240A1 (de) 1977-12-12 1978-12-09 Datenpufferspeicher vom typ first-in, first-out mit festem eingang und variablem ausgang
FR7834813A FR2411468A1 (fr) 1977-12-12 1978-12-11 Memoire tampon d'informations du type " file d'attente " comportant une entree fixe et une sortie variable
JP53153607A JPS5921055B2 (ja) 1977-12-12 1978-12-12 デ−タバツフアメモリ
US06/157,132 US4314361A (en) 1977-12-12 1980-06-06 Data buffer memory of the first-in, first-out type comprising a fixed input and a variable output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7713708A NL7713708A (nl) 1977-12-12 1977-12-12 Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.

Publications (1)

Publication Number Publication Date
NL7713708A true NL7713708A (nl) 1979-06-14

Family

ID=19829733

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7713708A NL7713708A (nl) 1977-12-12 1977-12-12 Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.

Country Status (6)

Country Link
US (1) US4314361A (fr)
JP (1) JPS5921055B2 (fr)
DE (1) DE2853240A1 (fr)
FR (1) FR2411468A1 (fr)
GB (1) GB2009980B (fr)
NL (1) NL7713708A (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU575351B2 (en) * 1983-11-07 1988-07-28 Digital Equipment Corporation Data processing system
US5038277A (en) * 1983-11-07 1991-08-06 Digital Equipment Corporation Adjustable buffer for data communications in a data processing system
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
CH671476A5 (fr) * 1986-06-16 1989-08-31 Siemens Ag Albis
US4899307A (en) * 1987-04-10 1990-02-06 Tandem Computers Incorporated Stack with unary encoded stack pointer
GB2232797B (en) * 1989-06-16 1993-12-08 Samsung Semiconductor Inc RAM based serial memory with pipelined look-ahead reading
US5343435A (en) * 1991-06-14 1994-08-30 Integrated Device Technology, Inc. Use of a data register to effectively increase the efficiency of an on-chip write buffer
WO1999009467A2 (fr) 1997-08-20 1999-02-25 Koninklijke Philips Electronics N.V. Organisation de memoire tampon de traitement des trains de donnees transitoires avec gestion logicielle conçue pour des operations d'amenagement multi-niveau
SE9904685D0 (sv) * 1999-12-17 1999-12-17 Switchcore Ab A programmable packet decoder
US6694389B2 (en) * 2001-03-19 2004-02-17 Sun Microsystems, Inc. Method and apparatus for data flow analysis
US6711494B2 (en) * 2001-07-30 2004-03-23 Emulex Corporation Data formatter for shifting data to correct data lanes
US6836852B2 (en) * 2001-10-29 2004-12-28 Agilent Technologies, Inc. Method for synchronizing multiple serial data streams using a plurality of clock signals
KR102532528B1 (ko) * 2016-04-07 2023-05-17 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE755666A (fr) * 1969-09-18 1971-02-15 Burroughs Corp Memoire tampon pour entree d'ordinateur
NL7014737A (fr) * 1970-10-08 1972-04-11
US3736575A (en) * 1972-02-01 1973-05-29 Dyad Systems Inc Single line per bit asynchronous circuit and system
DE2348452B2 (de) * 1973-09-26 1977-12-29 Siemens AG, 1000 Berlin und 8000 München Anschluss taktgebundener datenuebertragungseinrichtungen an ein datenendgeraet, das zur aussendung von daten nach dem start-stop-prinzip ausgelegt ist
DE2414874B2 (de) * 1974-03-27 1977-05-05 Synchrones schieberegister mit serien- und paralleleingabe und grundstelleingang
DE2441584A1 (de) * 1974-08-30 1976-03-11 Siemens Ag Pufferspeicher
US4090256A (en) * 1975-05-27 1978-05-16 Motorola, Inc. First-in-first-out register implemented with single rank storage elements
DE2729361A1 (de) * 1976-07-29 1978-02-09 Motorola Inc Speicherschaltung

Also Published As

Publication number Publication date
JPS5921055B2 (ja) 1984-05-17
GB2009980A (en) 1979-06-20
DE2853240A1 (de) 1979-06-13
FR2411468B1 (fr) 1985-01-18
FR2411468A1 (fr) 1979-07-06
US4314361A (en) 1982-02-02
GB2009980B (en) 1982-04-15
DE2853240C2 (fr) 1989-02-02
JPS5489441A (en) 1979-07-16

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Legal Events

Date Code Title Description
A1B A search report has been drawn up
BV The patent application has lapsed