NL7510186A - Inrichting voor het inschrijven van binaire sig- nalen in uitgekozen geheugenelementen van een mos- -geheugen. - Google Patents
Inrichting voor het inschrijven van binaire sig- nalen in uitgekozen geheugenelementen van een mos- -geheugen.Info
- Publication number
- NL7510186A NL7510186A NL7510186A NL7510186A NL7510186A NL 7510186 A NL7510186 A NL 7510186A NL 7510186 A NL7510186 A NL 7510186A NL 7510186 A NL7510186 A NL 7510186A NL 7510186 A NL7510186 A NL 7510186A
- Authority
- NL
- Netherlands
- Prior art keywords
- binary signals
- mos
- memory
- memory elements
- selected memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Databases & Information Systems (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742443529 DE2443529B2 (de) | 1974-09-11 | 1974-09-11 | Verfahren und anordnung zum einschreiben von binaersignalen in ausgewaehlte speicherelemente eines mos-speichers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL7510186A true NL7510186A (nl) | 1976-03-15 |
Family
ID=5925478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL7510186A NL7510186A (nl) | 1974-09-11 | 1975-08-28 | Inrichting voor het inschrijven van binaire sig- nalen in uitgekozen geheugenelementen van een mos- -geheugen. |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3992704A (xx) |
| BE (1) | BE833310A (xx) |
| CH (1) | CH586946A5 (xx) |
| DE (1) | DE2443529B2 (xx) |
| FR (1) | FR2331121A1 (xx) |
| GB (1) | GB1522183A (xx) |
| IT (1) | IT1042254B (xx) |
| NL (1) | NL7510186A (xx) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4069474A (en) * | 1976-04-15 | 1978-01-17 | National Semiconductor Corporation | MOS Dynamic random access memory having an improved sensing circuit |
| US4069475A (en) * | 1976-04-15 | 1978-01-17 | National Semiconductor Corporation | MOS Dynamic random access memory having an improved sense and restore circuit |
| US4144590A (en) * | 1976-12-29 | 1979-03-13 | Texas Instruments Incorporated | Intermediate output buffer circuit for semiconductor memory device |
| US4081701A (en) * | 1976-06-01 | 1978-03-28 | Texas Instruments Incorporated | High speed sense amplifier for MOS random access memory |
| US4114055A (en) * | 1977-05-12 | 1978-09-12 | Rca Corporation | Unbalanced sense circuit |
| US4096401A (en) * | 1977-05-12 | 1978-06-20 | Rca Corporation | Sense circuit for an MNOS array using a pair of CMOS inverters cross-coupled via CMOS gates which are responsive to the input sense signals |
| US4107556A (en) * | 1977-05-12 | 1978-08-15 | Rca Corporation | Sense circuit employing complementary field effect transistors |
| JPS5939833B2 (ja) * | 1977-05-24 | 1984-09-26 | 日本電気株式会社 | センス増幅器 |
| US4170741A (en) * | 1978-03-13 | 1979-10-09 | Westinghouse Electric Corp. | High speed CMOS sense circuit for semiconductor memories |
| DE2839073C2 (de) * | 1978-09-07 | 1983-02-17 | Siemens AG, 1000 Berlin und 8000 München | Dynamische Stromquelle für Halbleiterbausteine und ihre Verwendung |
| JPS58114391A (ja) * | 1981-12-25 | 1983-07-07 | Nec Corp | センスアンプ回路 |
| US5352937A (en) * | 1992-11-16 | 1994-10-04 | Rca Thomson Licensing Corporation | Differential comparator circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675218A (en) * | 1970-01-15 | 1972-07-04 | Ibm | Independent read-write monolithic memory array |
| US3838295A (en) * | 1973-02-05 | 1974-09-24 | Lockheed Electronics Co | Ratioless mos sense amplifier |
| DE2309192C3 (de) * | 1973-02-23 | 1975-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Regenerierschaltung nach Art eines getasteten Flipflops und Verfahren zum Betrieb einer solchen Regenerierschaltung |
| US3838404A (en) * | 1973-05-17 | 1974-09-24 | Teletype Corp | Random access memory system and cell |
| US3940747A (en) * | 1973-08-02 | 1976-02-24 | Texas Instruments Incorporated | High density, high speed random access read-write memory |
| US3863232A (en) * | 1973-12-26 | 1975-01-28 | Ibm | Associative array |
-
1974
- 1974-09-11 DE DE19742443529 patent/DE2443529B2/de active Granted
-
1975
- 1975-08-05 GB GB32631/75A patent/GB1522183A/en not_active Expired
- 1975-08-28 NL NL7510186A patent/NL7510186A/xx not_active Application Discontinuation
- 1975-09-02 FR FR7526874A patent/FR2331121A1/fr not_active Withdrawn
- 1975-09-03 IT IT26848/75A patent/IT1042254B/it active
- 1975-09-05 CH CH1157875A patent/CH586946A5/xx not_active IP Right Cessation
- 1975-09-05 US US610756A patent/US3992704A/en not_active Expired - Lifetime
- 1975-09-11 BE BE159949A patent/BE833310A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR2331121A1 (fr) | 1977-06-03 |
| DE2443529B2 (de) | 1977-09-01 |
| BE833310A (fr) | 1976-03-11 |
| DE2443529A1 (de) | 1976-03-25 |
| CH586946A5 (xx) | 1977-04-15 |
| DE2443529C3 (xx) | 1978-04-27 |
| US3992704A (en) | 1976-11-16 |
| GB1522183A (en) | 1978-08-23 |
| IT1042254B (it) | 1980-01-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| BV | The patent application has lapsed |